A Comparison Among Three-Level ZVS-PWM Isolated DC-to-DC Converters

Transcription

1 A Comparison Among Three-Level ZVS-PWM Isolated DC-to-DC Converters Eduardo Deschamps Electrical Engineering Department Regional University of Blumenau - FURB P. 0. Box Blumenau - SC - Brazil edudes@furb.rct-sc. br Ivo Barbi Power Electronics Institute - INEP Federal University of Santa Catarina - UFSC P. 0. Box Florianopolis - SC - Brazil ivo@inep.ufsc. br I Abstract - Considering that the designer of high-frequency high-input voltage power supplies not always will find semiconductors capable of sustaining the desired voltage, it has been proposed several topologies based on multilevel converters in which only a fraction of the voltage is applied to each switch. This paper compares five different threelevel ZVS PWM isolated DC-to-DC converter topologies. Basics concepts of each topology are shown along with their advantages and drawbacks. A comparison involving the size of reactive elements employed, stress of the semiconductors devices, number of semiconductors devices employed, simplicity and efficiency is made and summarised. Experimental results are included, in order to verify the theoretical analysis. I. INTRODUCTION On the design of high frequency switching mode power supplies for high power applications, the conventional full-bridge zero-voltage-switching pulse-widthmodulation (FB-ZVS-PWM) converter [ 11 is considered one of the best alternatives. This converter possesses the most desirable characteristics of both the hard switching PWM and the soft switching converters, while avoiding their major drawbacks, such as commutation losses in the first group, and variable switching frequency and high conduction losses in the second group. However, the FB-ZVS-PWM converter is not suitable for high-input voltage applications because the total input voltage is applied across its blocking switches and, in many cases, the designer doesn't have semiconductors able to block high voltage in high power applications available. In order to reduce the voltage stress of the switches, many alternatives have been studied. Among these alternatives are: the series connection of switches and the use of multilevel topologies. In the series connection of the switches the static and dynamic sharing of the voltage across the switches is quite difficult to obtain and requires specific techniques: - static balancing can be simply achieved by connecting large resistors in parallel with'each switch; - dynamic balancing is a more serious problem. The designer must make sure that all switches commutate at the very same instant: otherwise the switch that turns off first (or that turns on last) would have to sustain all of the voltage [3]. With this technique, everything is done to contrive all the switches to commutate at the same time. When this is achieved, the dv/dt generated at each commutation is the sum of the dv/dt generated by all the switches. Such dv/dt will induce important noise that can be dangerous for the surrounding low-level circuits [3]. Recently multilevel cells have drawn tremendous interest in the power industry [2]. They consist in a commutation cell using series-connected semiconductors in which clamping circuits ensure the voltage sharing instead of forcing the switches to commutate at the very same time. Hence, multilevel cells solve the problems of static and dynamic sharing of the voltage across the blocking switches and limits the dvidt to standard values, reducing EM1 problems. CI C2 C; c4 Converter 1 Converter 2 Converter 3 Converter 4 c3 Dor + Dol Dni Lo Lo Ln Converter 5 Fig. 1 - Three-level ZVS-PWM DC-to-DC converters. Ro /98/$ IEEE 1024

2 This paper presents a comparison among five threelevel isolated dc-to-dc converters based on multilevel cells, presented in Fig. 1, which are controlled by pulsewidth inodulation featuring ZVS commutation and half of the input voltage as the maximum voltage applied across the switches. 11. CIRCUITS DESCRIPTION Converter 1 is based on the NPC (Neutral Point Clamped) multilevel inverter [4]. With an appropriate command, the input voltage (Vi) and the clamping diodes Dcl and Dc2 impose the voltage across the blocking switch, of any pair of switches. The gate signals of the switches are presented in Fig. 2 where D is the dutycycle and T, is the switching period. The complete analysis including operation principle, main waveforms, theoretical analysis for this converter is presented in [4]. Fig. 2 - Gate signals for converter I Converter 2 is based on the flying capacitor multilevel cell [2]. The switches are arranged in two pairs (SI,%) and (S2,S3). Within each pair, the switches obey the same rule as the two switches of a conventional commutation cell: they must be in complementary state. With the gate signals shown in Fig. 3 the voltage across the blocking switches is imposed by the input voltage (Vi) and the voltage across the capacitor CC, which will be equal to Vii2. The complete analysis of this converter is presented in [5] I Fig. 3 - Gate signals for converter 2, 4 and 5. Converter 3 is a variation of the topology 2 with the input voltage (Vi) and the capacitors Cil and Ci2 imposing the voltage across the blocking switches. As the switches go through their cycle of switching, as presented in Fig. 4, each switch has Vi12 applied across it while it is off. Cs is a dc-blocking capacitor that blocks the dc voltage from being applied to the series combination L, and TI, allowing a three-level voltage across the power transformer TI. The gate signals for this converter are presented in Fig. 4. For a complete analysis refer to [61. Converter 4 consists in a cascade connection of the primary side of two half-bridge converters. One of the converters is formed by capacitors CI1 and C12, switches SI and S4 and transformer Tr2. The other one is formed by capacitors Ccl and Cc2, switches S2 and S4 and transformer Tr,. The voltage across the blocking switches is imposed by the input voltage (Vi) and the voltage across the capacitors Ccl and Cc2, which is equal to Vi/2. The complete analysis of this converter can be found in [7] Fig. 4 - Gate signals for converter j Converter 5 is a series association of the primary side of two isolated half-bridge inverters with the secondary of their transformers connected in series. The input voltage (Vi) and the voltage across the capacitors C,, to Ci4 impose the voltage across the blocking switches. The complete analysis of this converter is presented in [8]. The gate signals for converters 4 and 5 are the same with those presented for converter 2 in Fig. 3. In all converters the resonant inductance Lr along with snubber capacitors CI to C4 provides a resonant transition permitting zero-voltage tum-on that eliminates tumon switching power losses. The energy stored in L, charges and discharges the snubbing capacitors CI to Cq during a conduction gap that is provided between turning-off one switch and turning-on the other switch of one pair. The action brings the switch voltage to zero before the switch is turned-on. The minimum load current that guarantees zerovoltage switching for converter 1 is defined by (1). where Lm, = L r + Ld (2) Inductance Ld is the leakage inductance of the transformer T,. For converters 2 and 3 the minimum load current is defined by (3). For converters 4 and 5, (3) is also valid but L,,, fined by (4). is de- Lm = LrI + Lr-2 + Ldl + LdZ (4) Capacitors C, to C4 also provide capacitive turn-off snubbing reducing the commutation losses. The diodes D, to D4 conduct inverse-polarity current and clamps the switch at a reverse voltage ( -1 V). The transformer T, (or TI, and Tr2) provides galvanic isolation and voltage transformation between the source and the load S03-7/98/$ IEEE 102s

3 ~ ~~ The output stage of the converters is formed by the association of the secondary windings of the transformers with rectifiers Dol and and an output filter composed of the inductor Lo and capacitor Co. For all the converters the output voltage can be calculated using (5). Vi [ 4.ji.~r~,,~o VO=--. D- (5) n n.vi 1 ' where n is the transformer turns ratio, D is the dutycycle, fs is the switching frequency. From (5), that represents the dc voltage-conversionratio of the converter, it can be noticed that the larger L, is, the larger also is the reduction of the output voltage caused by the reactive voltage drop. As can be observed from (l), (3) and (5) the wider the load range with ZVS is the higher is the reactive voltage drop across resonant inductor L,. A good design involves sacrificing the soft-commutation at light load, where the conduction losses are low, to obtain high efficiency at full-load DESIGN AND EXPERIMENTAL RESULTS In order to compare experimentally the behaviour of the converters, five prototypes were built with the input data presented in Table I. The design procedures of the converters studied in this paper are presented in [4], [5], [6], [7] and [SI. The power stages of the converters implemented are shown in Fig. 5,7,9,1l,and 13. The components used are presented in table 11. The total resonant inductance is composed by the leakage transformer inductances and the external induc- tance L,, yielding for each converter 24pH. The MOSFET's body diodes were used for D1-4 of Fig.1, and the MOSFET's Cos, capacitances (480 pf) were used for cl-4. Experimentally results of an output power Po of 1.5 kw, output current Io of 25 A, input voltage Vi of 600 V and switching frequency fs of 50 khz are shown in Fig. 6, 8, 10, 12 and 14. The figures present, for each converter, the three-level voltage, the current through the resonant inductor and the switches voltage and current. For each case the duty-cycle was set in order to obtain output voltage Vo equal to 60 V for full load (25 A). All the observed waveforms agree well with the theoretical waveforms. It is important to ephasize that the peak voltage across the switches, for all the prototypes, is 300 V, half of the 600 V dc input voltage. All the converters present similar switches voltage and current waveforms and zerovoltage switching. TABLE I INPUT DATA Input voltage - Vi (V) Output voltage - Vo (V) Output power - Po (kw) Switching frequency - fs (khz) Input voltage ripple - AVi (V) Output inductor ripple - Alo (A) I 2.5 I Output voltage ripple - AVO (VI I 0.06 I Clamping capacitor voltage ripple - AVcc (V) Minimum ZVS load range (%) Maximum duty-cvcle - D,,., MI-M~ L,. - L,, - L,.2 COMPONENT c;, - ci2 - Ci3 - ci4 cc- Cct - cc2- cs Dcl-DcZ T, - T,.I - T,.z Do1 - D, c, R, CONVERTER COMPONENTS CONVERTER IRFP V, 20A (Harris) 8pH - ferrite core E IP12 16pH - ferrite core E pH - IP12 (Thornton) ferrite core (Thornton) E42/15 - IP12 (Thornton) 3yF1400V - polyester (Icotron) 7pFi400V - polyester (Icotron) MURS40 400V, SA (Motorola) 2 ferrite cores E65/26 - IP12 (Thornton) Primary: 17 turns - 22AWG Secondary: 10 turns center tapped - 22AWG Ferrite core E65/39-1P 12(Thornton) Primary: 17 turns - 22AWG Secondary: 10 turns center tapped - 22AWG MUR V, 15A (Motorola) MUR V, IA (Motorola) 1 OnFi400V - polypropylene (Icotron) 24kW5 W Lo I 89pH - ferrite core E IP12 (Thornton) C" I 220pF1100V - electrolytic (Icotroti) /98/$ IEEE 1026

4 Vi Cil c- Ci2c3 Dci MI - %M3JE a 1:" 2 D: M4JE Qg dff-jr, M3J Cs Ci2 C M4J Fig. 9 - Power stage diagram of converter 3. (c) Fig Experimental waveforms - converter 3 (D-0.42). (a) upper trace: voltage vllc (250 V/div. Sps/div.), lower trace: current ilr (5 A/div. Spddiv.) (b) upper trace: voltage drain-to-source VDSI (100 Voltddiv. Sps/div.) lower trace: drain current idl (5 A/div. Sps/div.) (c) upper trace: voltage drain-to-source VDSZ (100 Voltddiv. Spddiv.) lower trace: drain current io2 (5 Ndiv. Spddiv.) (c) Fig Experimental waveforms - converter 4 (D=0.42). (a) upper trace: voltage vzlc (250 V/div. Spddiv.) lower trace: current ilr2 (5 Mdiv. Spddiv.) (b) upper trace: voltage drain-to-source VDS~ (100 Voltddiv. Sps/div.) lower trace: drain current (5 Ndiv. Spddiv.) (c) upper trace: voltage drain-to-source VDSZ (100 Voltddiv. 5pddiv.) lower trace: drain current io2 (5 Ndiv. Spsldiv.) /98/$ IEEE 1027

5 input voltage equal to 600V and constant duty-cycle. In general, the measured value at full load (25 A) is above 92%. The main source of losses are diode and MOSFET conduction losses, magnetic and snubber losses. The switching losses at full load are practically zero due to zero-voltage turn-on and capacitive turn-off snubbing.. 2LM R!2 Fig Power stage diagram ofconverter 5 98 r h 5 92 x $ 90.e 4 88 W j c1 + c2-8- c3 + c4 x c Output Current (A) Fig Efficiency as a function of output current (c) Fig Experimental waveforms - converter 5 (D=0.42). (a) upper trace: voltage vi,b+vd (250 Vidiv. 5psidiv.) lower trace: current ilrl (5 Ndiv. 5psidiv.) (b) upper trace: voltage drain-to-source VDSI (100 Voltsidiv. 5psidiv.) lower trace: drain current idi (5 A/div. 5ps/div.) (c) upper trace: voltage drain-to-source VDS~ (100 Voltsidiv. Spsidiv.) lower trace: drain current idz (5 Ndiv. 5psidiv.) The output voltage as function of the load current of the converters for Vi equal to 600 V and constant dutycycle is presented in Fig. 15. The output voltage decreases with an increase of the output current due to the reduction of the effective duty-cycle, caused by the amount of reactive power that circulates in the circuit, as predicted in (5). U a 3 :; ;... ;... j... ;...: IO Output Cui-rent (A) Fig Output voltage as a function of output current. - Cl & c2 - c3 * c4 x c5 Fig. 16 shows the measured efficiency of the power circuits as a function of the output current for constant The efficiency for all the converters clearly decreases for load currents lower than 5 A, when the ZVS commutation is lost and the converter starts to operate with hard-switching. IV. ANALYSIS Table I11 presents a summarised comparison among the five converters analysed. Considering the ZVS load range, converter 1 presents larger ZVS load range than the others. Considering the number of semiconductors devices employed, it is clear that converter 2 to 5 employ less power diodes than converter 1. However, they need extka capacitors for voltage clamping. In high-frequency applications capacitor clamping is more suitable because the total amount of capacitance required can be decreased proportionally with the switching frequency. On the other hand, converter 1 doesn't have problems of voltage balance across the clamping capacitors. The magnetic volume of converters 4 and 5 is higher than the others, but in high-power applications their use can be interesting due to the possibility of sharing the total power processed between the two transformers. From the point of view of switches stresses, all the converters present the same results, with the same peak voltage across the switches (half of the input voltage) and the same volume of heat-sinks. The efficiency measured for the converters are similar, with converters 4 and 5 presenting lower efficiency at full load in comparison with the other converters. This can be explained by the transformer core losses of converters 4 and 5 that are higher. Finally, converters I, 2, 4 and 5 can be naturally extended to more than three-level allowing applications for higher input voltage /98/$ IEEE 1028

6 CONVERTER Active switches (I) A~=AC.AW where: AC = effective core area (tin') ; AW = window area (cm2)- for each transformer thermal resistance heat sink to ambient for two switches in the same heat sink for full load V. CONCLUSIONS This paper presented a comparative analysis among five three-level ZVS-PWM isolated DC-to-DC converters suitable for high-input voltage applications. A comparison involving the size of reactive elements, stress of semiconductor devices, number of semiconductor devices, simplicity and efficiency were made and summarized. Experimental results were presented, in order to verify the theoretical results. The five topologies presented similar characteristics, with slight differences among them. A choice of the best alternative depends on the application where the converter will be employed. In general, for an application of high power and high frequency the converter 2, based on the flying capacitor cell, seems to be more appropriate because presents high efficiency, no need of extra diodes as the converter based on the NPC cell, less volume of magnetics in comparison to converters 4 and 5, that needs two transformers, and can be naturally extended for more than three-levels. VI. ACKNOWLEDGEMENTS The authors would like to thank the Power Electronics Institute s technicians, Luiz M. Coelho and Antcinio L. S. Pacheco for their support in the prototypes building. Special acknowledgemnets are due to the Electrical Engineering Student Fabiana Cavalcante, whose help in the laboratory made possible to obtain the experimental results. This work was developed within the Electrical Engineering Doctorate Program of the Federal University of Santa Catarina at the Power Electronics Institute with financial support of CAPES and FURB. VII. REFERENCES [l] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee and B. H. Cho, Design Considerations for High-Voltage High-Power Full-Bridge Zero-Voltage-Switched PWM Converter, APEC 90 Conference Records, pp , [2] J. S. Lai and F. Z. Peng, Multilevel Converters - A New Breed of Power Converters, IEEE Transactions on Industry Applications, vol. 32 no. 3, MayIJune [3] T. A. Meynard and H. Foch, Multi-level Conversion: High-Voltage Choppers and Voltage-Source Inverters, PESC 92 Confirence Records, pp , [4] J. R. Pinheiro and I. Barbi, The Three-Level ZVS- PWM DC-to-DC Converter, IEEE Transactions on Power Electronics, vol.8, 110.4, pp , October [SI E. Descharnps and I. Barbi, A Three-Level ZVS PWM DC-to-DC Converter Using the Versatile Multilevel Commutation Cell, COBEP 97 Conference Records, pp [6] N. 0. Sold, R. Redl, R. Gules and I. Barbi, DCIDC Converter for High Input Voltage; Four Switches with Peak Voltage of VinI2, Capacitive Turn-off Snubbing and Zero-Voltage Turn-on, To be presented on PESC 98. E. Descharnps and I. Barbi, A New DC-to-DC ZVS PWM Converter for High Input Voltage Voltage Applications, To be presented on PESC 98. E. Deschamps and I. Barbi, Three-Level DC-to-DC ZVS PWM Converters, Power Electronics Institute- INEP Internal Report, /98/$ IEEE 1029