Design of a VLSI Hamming Neural Network For arrhythmia classification

Transcription

1 First Joint Congress on Fuzzy and Intelligent Systems Ferdowsi University of Mashhad, Iran 9-31 Aug 007 Intelligent Systems Scientific Society of Iran Design of a VLSI Hamming Neural Network For arrhythmia classification Behzad Ghanavati Behbod Mashoufi St_b.ghanavati@urmia.ac.ir B.mashoufi@urmia.ac.ir Microelectronics Research Center of Urmia University, Urmia, Iran Abstract: The implantable cardioverter defibrillators (ICDs) detect and treat dangerous cardiac arrhythmia. This paper describes a VLSI neural network chip to be implemented using 0.35 μ CMOS technology which acts as an intercardia tachycardia classification system. The Hamming net used to classify non binary input pattern and also reduce impact of noise, drift and offset inherent in analog application. Keywords: Implantable tachycardia arrhythmia classifier, Neural Network, Hamming Net. 1 Introduction In recently year, Artificial Neural Networks have been studied extensively and applied in medical field, and have been demonstrated to have much better pattern recognition ability. In this paper we present a neural network circuit used in a biomedical application, which is the implantable cardioverter defibrillator (ICDs). Implantable cardioverter defibrillator is a device which monitors the heart and delivers electrical shock therapy in the event of a life-threatening arrhythmia. At present most ICDs use only timing information from leads to classify rhythms [1].This means that they can not distinguish some dangerous rhythms from safe one, as in the case of ventriculartachycardia arrhythmia. [] Our chip is used to distinguish between two types of arrhythmia. The sinus tachycardia (ST) arrhythmia and the ventricular tachycardia (VT) arrhythmia, The ST is a safe arrhythmia occurs during vigorous exercises and is characterized with rate of 10beat/minute. The VT is a fatal arrhythmia with the same rate. They can be separated only by detecting the morphology changes in each one []. A typical waveform from an electrocardiogram (ECG) is shown in figure 1. It consists of several complexes, the P-complex, the QRS-complex, the T-complex and the U-complex [3]. Figure 1: A typical waveform of ECG Most morphology changes appear in the QRScomplex. The QRS-complex for both the ST and VT arrhythmia s are shown in figure. [] Our studies indicate that; only two works are reported using Neural Network to detect such morphology changes [][4].their Networks need to have training system and the weights of their Networks are off-chip learning. Figure : Morphology change of QRS complex for both ST & VT

2 The proposed analog VLSI neural network can detect such morphology changes. It has the following advantages: It is easily interfaced to the analog signals in an ICD (in contrast to digital systems which require analog to digital conversion). Analog circuits are generally small in area. Although temperature variation is a major source of drift problems, no need for temperature compensation as the human body is considered a stable environment. Architecture The chip consists of four building blocks: an amplifier, a sample and hold (S/H) circuit, a mapping circuit and a hamming neural network classifier. Figure 3 represents a block diagram of the chip. The rhythm is first input to an amplifier to be amplified. The Outputs of the amplifier is then input to a sample and hold circuit to obtain 15 samples of the input signal. The 15 samples are input to mapping circuits in parallel to map into unit length [-1 1]. The outputs of mapping circuits are input to Hamming Neural Network, which has two neurons in its output layer each one responds to a type of the input arrhythmia. Figure 4: A competitive cell a = comp( W P) (1) 1, i = i * a i = 0, i i * () i* is number of cell that have highest n i.for our application i=1, In the Hamming Network reference vector determine the weights (w) of the net. So n Calculate Hamming distance between input vector (P) and reference vector. Multiply input vector to weights determined the winner cell. The largest value corresponds to the smallest angle between input and weight vector if they are both of unit length [-1 1].[6] W11 W1... W110 cos θ1 n = WP = P = (3) W 1 W... W10 cos θ 4 Circuit design The design of blocks in figure 3 is given below: 4.1 Amplifier The signal is first input to amplifier shown in figure 5.The frequency range of input signal is from 0.01 to 50 HZ so we used P-type input differential Pair for lower flicker noise.[7][8] Figure 3: Block diagram 3 Hamming Neural Network A Neural Network classifier is implemented using a Hamming net, which is a maximum likelihood classifier net that can be used to determine which of several exemplar vectors is most similar to an input vector.[5] Figure 4 show a simplest structure of a competitive layer. Figure 5: Amplifier The input to the amplifier V in = (V 1 -V ) is the QRS-complex shown in figure shifted by a dc level of 1 volts. The output of the amplifier is then input to the sample and hold circuit. The simulation result of the amplifier for both ST & VT inputs are shown in Figure 6.

3 4.3 Mapping circuit Before applying sampled data to Neural Net we must mapping them into unit length [-1 1]. Figure 10 show schematic of mapping circuit. We use a simple differential pair to create I out which map input (sampled data) to [-I ref, I ref ] by changing V ref and W/L size of input differential Pair or paralleling devices with them we can map any space to unit length.[9] Figures 11 and 1 show simulations of mapping circuit Figure 6: Out put of amplifier for both ST&VT 4. Sample and hold (S& M) circuit The Sample and hold delay circuit consists of 15 cascaded stages, to obtain 15 samples of the input pulse. Figure 7 shows S/H circuit. A schematic of a buffer used in S/H circuit is shown in figure 8. Using two-phase no overlapping clock CK 1,CK for control of S/H.The sampled signal x i is input to mapping circuit through another analog switch m i controlled by CK 3.the timing diagram of CK 1,CK, CK 3 and sampled data are shown in figure 9. Figure 10: Mapping circuit Figure 11: simulation result by changing V ref. Figure 7: Three stage of S/H circuit Figure 1: simulation result by changing W/L. Figure 8: Circuit diagram of buffer used in S/H circuit 4.4 Hamming Neural Network classifier Figure 9: (a) input to S/H circuit (b) sampling signal of the 1 st stage (c) CK1 (d) CK (e) CK3 The hamming net consists of two group of synapse and two layers of neurons. The first group with weight vector W 1 = (W 11, W 1, W 13,, W 110 ) is connected to first neuron layer. The second layer with weight vector W = (W 1, W, W 3,, W 10 ) is connected to second neuron

4 layer, each neuron in the out put layer responds to a class of input arrhythmia. Figure 13 show the structure of Net Winner Take All The function of the WTA is to accept input signals, compare their values and produce a high digital output value (logic one ) corresponding largest input, while all other digital outputs are set to a low output value (logic zero ).[1] Figure 15 shows the block diagram of the WTA circuit. The circuit combines a -input current maximum selector [13] with high speed current comparator [14]. Figure 13: Hamming neural network Synapse The computation of inner product between input signal and the local inter connection weight called synapse is mostly done by using an analog multiplier. [10] We use a low power analog multiplier [11] shown in figure 14 as synapse, since output of synapse is current therefore output of 15 synapses can be summed at a single node of circuit. Figure 15: Winner Take All circuit The current max selector The -input current maximum selector is shown in Figure 16. Figure 16: -input max circuit I wi Figure 14: multiplier as synapse is the current that produced by mapping reference vector (weight) into unit length [-1 1] K Iout = ( ) I xi I wi (4) α W Where K = μc ox ( ) and α = 4K( Vdd Vtn ) L The current I B, of the diode connected transistor M B is used as the current source of the circuit. We assume that I 1 is the largest input current, I 1 =max (I 1, I ). The drain voltage V D1,V D of transistors M 11,M 1 are established by the input currents I 1,I. At steady state, when the voltage difference between V D1,V D fulfil the relation: I B Vdif = VD1 VD (5) β μc ox W Where β = ( ), the output currents are I o1 =I 1 L, I o =0.[13] Thus only one current is equal to the maximum input current, while all the other outputs are zero.

5 4.4.4 High speed current comparator Figure 17 shows the schematic of current comparator. + - Figure 17: current comparator The overall structure of WTA circuit The circuit of the -input WTA is shown in Figure 18. I c1 = = (10) Ic = 0 = (11) This means that only one input current of the current comparators corresponding to maximum current is positive and all the other currents are negative. Thus the digital voltage outputs of the circuit will be at logic Vo1 = ' one' (1) Vo = ' zero' 5 Result Two arrhythmia are input to the system. The first is ST arrhythmia, the second is VT arrhythmia. The behaviour of the system performance in both cases is shown in figure 19 and 0. Figure 18: -input WTA circuit The currents (I 1, I ) are the inputs and the circuit. Each current output (I o1, I o ) of the current maximum selector is mirrored into the corresponding output stage, as well as, into the feedback circuit due to PMOS current mirror M 16,M 6. So the drain current of M 17, M 7 is equal to: Io1 + Io If = ( ) (6) Thus the input current of each comparator is: Io1 + Io Ic1 = Io1 ( ) (7) Io1 + Io Ic = Io ( ) (8) We assume that at steady state the current I 1 is the largest input current I 1 =max (I 1, I ) According to equations (6) the feedback current I f will be: I f = (9) From the equations (6-9) the input current of each current comparator is: Figure 19: output of system for ST input Figure 0: output of system for VT input 6 Conclusion In this paper a VLSI Neural Network for arrhythmia classification is presented. The proposed Hamming Neural Network exhibits a

6 very interesting pattern classification well suiting the tachycardia arrhythmia classification which can not be detected using only timing information of the chip. The proposed Network has the following features: No need for D/A converter between the ECG and the classification system. The system operates in the low frequency range, so that the parasitic of the layout likely have no effect on the operation of the chip. This system can be extended to distinguish m types of arrhythmia s by using m number of neurons in the output layer of the Hamming Neural Network circuit. References [1] Leong, P. H.W and Jabri, M.A A low power VLSI Arrhythmia classifier IEEE Transaction on Neural Networks volume 6, Nov.1995 Page(s): [] R. Coggins, M. Jabri, B. Flower and S. Pickard, A low- Power Network for On-Line Diagnosis of Heart Patients, "IEEE Trans. Micro, pp. 18-5, Jun [3] Y. Suzuki, Self organizing QRS-wave recognition in ECG using neural networks IEEE Trans. Neural network, Vo1.6, No.6, pp , Nov [4] H. Shawkey, H. Elsimary, H. Haddara, H.F. Ragaie, Design of a VLSI Neural Network Arrhythmia Classifier. Proceeding of the sixteenth National Radio Science conference, 1999,NRSC 99. Egypt, page(s): C 7/1-C 710 [5] Laurene Fausett, fundamental of Neural Network. Prentice Hall, 1994 [6] M. B. Menhaj, Computational intelligence (vol1): Fundamental of Neural Networks, Amirkabir center of Publishing, 000 [7] Behzad Razavi, Design of Analog CMOS integrated circuits, McGraw-Hill, 000 [8] Du chen, John G. Harris, Jose C.Principe A Bio-amplifier with pulse output Proceeding 6 th Annual international conference of the Engineering in Medicine and Biology Society.0004.EMBC004 volume, 004, page(s): vol.6 [9] Wilamowski, B. M and Jaeger, R.C and Kaynak, M. O Neuro-Fuzzy Architecture for CMOS Implementation IEEE Trans Industrial Electronics. Volume 46. Issue 6, DEC 1999.page(s): [10] F. A. Salam and M. R. Choi, Analog MOS vector multipliers for the implementation of synapses in artificial neural networks. Journal of Circuits, Systems, and Computers, vol. 1, no,, pp. 05-8, [11] S. T.Lee and K. T. Lau A reconfigurable low-voltage low-power building block for Artificial Neural Network Proc. Int. Conf. on Neural Networks. Volume 3, page(s): , vol.3, [1] S. vlassis and S. siskos High speed and high resolution WTA circuit Proceedings of the 1999 IEEE international symposium on circuits and systems, 1999.ICAS 99.volume page(s):4-7 [13] C.-Y. Huang and B.-D. Liu, Currentmode multiple input maximum circuit for fuzzy logic controllers, Electron. Lett. Vol. 30,no. 3, pp , Nov [14] H.Traff, oven approach to high speed CMOS Current comparators Electron. Let, Vol. 8, no. 3, pp , Jan. 199.