DESIGN AND PHASE-NOISE MODELING OF TEMPERATURE- COMPENSATED HIGH FREQUENCY MEMS-CMOS REFERENCE OSCILLATORS

Transcription

1 DESIGN AND PHASE-NOISE MODELING OF TEMPERATURE- COMPENSATED HIGH FREQUENCY MEMS-CMOS REFERENCE OSCILLATORS A Dissertation Presented to The Acadeic Faculty By Seyed Hossein Miri Lavasani In Partial Fulfillent of the Requireents for the Degree of Doctor of Philosophy in the School of Electrical and Coputer Engineering Georgia Institute of Technology August 010

2 DESIGN AND PHASE-NOISE MODELING OF TEMPERATURE- COMPENSATED HIGH FREQUENCY MEMS-CMOS REFERENCE OSCILLATORS Approved: Dr Farrokh Ayazi, Advisor School of Electrical and Coputer Engineering Georgia Institute of Technology Dr Joy Laskar School of Electrical and Coputer Engineering Georgia Institute of Technology Dr Deepak Divan School of Electrical and Coputer Engineering Georgia Institute of Technology Dr Olivier Pierron School of Electrical and Coputer Engineering Georgia Institute of Technology Dr Kevin T Kornegay School of Electrical and Coputer Engineering Georgia Institute of Technology Date Approved: May 17, 010 ii

3 To y wife, Hoda iii

4 ACKNOWLEDGEMENTS First and foreost, I would like to express y deepest gratitude to y advisor, Professor Farrokh Ayazi, for providing valuable guidance, strong support and excellent resources throughout y PhD progra I was honored to be part of his research tea at GT He has been a great hardworking entor and aspiration for e in becoing a successful research scholar Without his strong support and endless patience, I would have never been able to coplete this research work; for all of the, I a forever grateful I would also like to thank y dissertation coittee ebers Dr Joy Laskar, Dr Kevin Kornegay, Dr Deepak Divan, and Dr Levent Degertekin for their valuable tie and support in successfully copleting this dissertation I also wish to acknowledge the support of y colleagues at Integrated MEMS Lab whose tiely cooperation has been instruental to the progress of this work during the past 5 years I would like to thank Dr Krishnakuar Sundaresan for helping e gaining insight into MEMS oscillator design and initial help with the interface I also want to thank Dr Siavash Pourkaali for introducing e to the world of resonator characterization, Mr Qishu Qin for initial help with capacitive resonators, and Mr Ashwin Saarao for continuing Qishu s work that resulted in excellent high-q capacitive resonators My special thanks go to Dr Reza Abdolvand for his great assistance in providing high perforance piezoelectric resonators even when he was no longer at GT and his willingness to spend long hours in the lab to successfully coplete the tasks on tie iv

5 I also want to thank y dear parents, Ahad and Shirin for providing strong eotional support fro thousands of iles away Last but not the least, I thank y lovely wife, Hoda, who has always been there for e every step in this long journey and has ade great sacrifices to coplete y PhD study She is a great aspiration and ultiate otivation that drives e toward success in y life everyday for which I a forever grateful v

6 TABLE OF CONTENTS ACKNOWLEDGEMENTSiv LIST OF TABLESix LIST OF FIGURES x SUMMARYxvi CHAPTER 1: Introduction 1 11 Origin and History of Reference Oscillators 1 Reference Oscillator Requireents and Clasifications18 11 Short-Ter Stability 68 1 Long-Ter Stability68 13 Absolute Frequency Accuracy68 14 Frequency Tuning 0 15 Wavefor Shape0 16 Power Consuption1 17 Size1 13 Organization7 CHAPTER : High Frequency Microechanical Oscillator Design 30 1 Introduction30 Microechanical Reference Oscillator Block Diagra31 3 Series-Resonant Microechanical Resonator 3 31 Capacitive Microechanical Resonator Piezoelectric Microechanical Resonator37 4 Sustaining Aplifier for Microechanical Oscillators39 5 Autoatic Level Control 46 6 Teperature Copensation Circuit47 7 Microechanical Oscillator Exaples48 71 Capacitive SiBAR Oscillator 48 7 High Frequency TPOS Oscillator 55 8 Conclusion 63 CHAPTER 3: Transipedance Aplifeir Design65 31 Introduction65 3 TIA Configurations66 31 Open-Loop TIA Configuration67 3 Feedback TIA configuration70 33 TIA Perforance Metrics for Microechanical Oscillator Applications Transipedance Gain dB Bandwidth (BW) Noise Linearity77 vi

7 335 Power Consuption Stability78 34 High perforance Techniques Gain Enhanceent79 34 BW Enhanceent output Buffer Inverter Topology Doubly-Terinated (50Ω-Matched) Topology Open-Drain Topology93 36 Design Exaples Regulated Cascode TIA Inverter TIA Multiple-Stage Feedback TIA TIA with Inductive Shunt Peaking TIA with Current Pre-Aplifier Coparison of Different Enhanceent Techniques13 37 Conclusion 13 CHAPTER 4: Electronic Tuning for Lateral MEMS Oscillators Introduction14 4 Electronic Tuning for Series-Resonant Micrechanical Oscillators16 41 Parallel Tuning16 4 Series Tuning Series Tuning in Lateral Microechanical Oscillators Lateral Microechanical Oscillator with Ideal Resonator Lateral Microechanical Oscillator with Practical Resonator nd -Order Parasitic Effects on Tuning Range Tuning Range Enhanceent through Shunt Capacitive Cancellation Active Inductance Cancellation Negative Capacitance Cancellation Case Studies TIA without Tuning Enhanceent TIA with Active Inductance Cancellation TIA with Negative Capacitance Cancellation Coparison of Tuning Enhanceent Techniques Conclusion 156 CHAPTER 5: Teperature Copensation for MEMS Oscillators Introduction158 5 Teperature Copensation Methods for Microechanical Oscillators Material Copensation Electronic Copensation Ipleentation of Open-Loop Electronic Teperature Copensation Syste-Level Ipleentation Circuit-Level Ipleentation Sources of Error 171 vii

8 54 Case Studies Teperature-Copensated 441MHz AlN-on-Si Oscilator Electronically Teperature-Copensated 47MHz AlN-on-Si Oscillator Conclusion 176 CHAPTER 6: Phase-Noise in Series-RLC Lateral MEMS Oscillators Introduction179 6 Analytical Models for Phase-Noise Clasical Linear Tie-Invariant (LTI) Nodel (Lesson s Model)183 6 Linear Tie-Variant (LTV) Model (Hajiiri s Model) Nonlinear Tie-Invariant (NLTI) Model (Saori s Model) Sources of Phase-Noise in Microechanical Oscillators LTI Phase-Noise Model for Series-Resonant Lateral MEMS Oscillators LTI Model for Oscillator with Ideal Lateral MEMS Resonator LTI Approxiation of the 1 st -Order Parasitic Effects on the Phase-Noise LTI Approxiation of the nd -Order Parasitic Effects on the Phase-Noise Case Study High-Frequency Capacitive Microechanical Oscillator High-Frequency Lateral Piezoelectric Microechanical Oscillator03 64 Conclusion 06 CHAPTER 7: Conclusion and Future Directions Contributions08 7 Future Directions Nonlinear Operation for Phase-Noise Iproveent 11 7 Single-Resonator Dual-Frequency Microechanical Reference Oscillator13 73 Ultra-Teperature-Stable PLL-Based MEMS Reference Oscillator Resonator-Based Mechanical Spectru Analyzer0 73 Conclusion REFERENCES 3 viii

9 LIST OF TABLES Table 11 Phase-Noise Requireent for Cellular and Broadband Wireless Standards 3 Table 1 Jitter Requireent for Broadband Optical Standards 6 Table 1: Perforance coparison of icroechanical oscillators 64 Table 31 Perforance coparison of the state-of-the-art CMOS TIAs 1 Table 3 Coparison of different high perforance techniques 15 ix

10 LIST OF FIGURES Fig 11 Miniaturized Quartz Crystal Fig 1 Block diagra of 19MHz icroechanical oscillator [10] 4 Fig 13 Diagra and phase-noise of the teperature-stable 70MHz oscillator [11] 5 Fig 14 Block diagra of 60MHz disk icroechanical oscillator [8] 8 Fig 15 Block diagra of 103MHz teperature-copensated SiBAR oscillator [6] 8 Fig 16 General block diagra of teperature-copensated IBAR oscillator [] 9 Fig 17 SiTie s Ultra-thin high perforance MEMS reference oscillator [3] 10 Fig 18 Co-integration of thin-fil bulk resonator with Si Bipolar process [34] 1 Fig 19 1GHz FBAR VCO and its phase-noise copared to an LC VCO [36] 13 Fig 110 Block diagra of the lateral piezoelectric oscillator [40] 14 Fig 111 Scheatic and easured phase-noise of the 81MHz oscillator [44] 15 Fig 11 Measured TCF of the 81MHz lateral piezoelectric oscillator [44] 15 Fig 113 Chip view and phase-noise of the ulti-frequency ALN oscillator [45] 16 Fig 114 View of the MHz oscillator and its easured phase-noise [46] 17 Fig 115 SNR vs clock jitter for ADCs [55] 6 Fig 1 General block diagra of high frequency icroechanical oscillator [1] 31 Fig Luped RLC odel for a series-resonant icroechanical resonator 33 Fig 3 The response and SEM of a capacitive icroechanical resonator [6] 36 Fig 4 Luped RLC equivalent odel for capacitive SiBAR 36 Fig 5 Response and SEM of a 496MHz piezoelectric MEMS resonator [7] 38 Fig 6 Luped RLC equivalent odel for high-order TPOS resonator 39 Fig 7 Block diagra of the negative-resistance based icroechanical oscillator 40 Fig 8 Negative resistance odel of a crystal oscillator [58] 41 Fig 9 Exaple of cross-coupled topology used in 1GHz FBAR oscillator [36] 4 x

11 Fig 10 Block diagra of the oscillator based on positive feedback loop with TIA 44 Fig 11 Scheatic of the two-stage 018μ CMOS TIA [19] 45 Fig 1 Measured transipedance gain of the two-stage 018μ CMOS TIA [19] 45 Fig 13 General block diagra of ALC circuit [] 47 Fig 14 General block diagra of the teperature copensation circuit 48 Fig 15 Circuit equivalent of the ANSYS odel of the SiBAR 50 Fig 16 Value of A v at resonance vs device thickness 51 Fig 17 Measured frequency response of the 145MHz SiBAR (highest Q) 53 Fig 18 Measured frequency response of the 145MHz SiBAR at V p =14V 53 Fig 19 Micrograph of CMOS TIA Magnified view shows the active area 54 Fig 0 Measured spectru and phase-noise of the 145MHz oscillator 55 Fig 1 Block diagra of the high frequency TPOS oscillator [7] 57 Fig SEM and response of 496MHz and 08MHz AlN-on-Si resonators [7] 58 Fig 3 Scheatic of the three-stage CMOS TIA (biasing is not shown) [7] 59 Fig 4 Frequency response of the tunable CMOS TIA [7] 6 Fig 5 Micrograph of the fabricated die [7] 63 Fig 6 Phase-noise and output spectru of 08MHz and 496MHz oscillators [7] 63 Fig 31 The equivalent luped odel of the TIA 67 Fig 3 Open-loop TIA concept 68 Fig 33 Siplified scheatic of a CG TIA 69 Fig 34 Siplified equivalent circuit for noise calculation in a CG TIA 71 Fig 35 Closed-loop TIA concept 7 Fig 36 Diagra of the feedback TIA with input and output capacitance load 73 Fig 37 Scheatic of the feedback TIA showing the resistor and aplifier noise 74 Fig 38 Siplified scheatic of the feedback TIA with finite output ipedance 75 xi

12 Fig 39 Scheatic of single-stage inverter-based tunable feedback TIA 76 Fig 310 Scheatic of CG TIA with auxiliary PMOS load 81 Fig 311 Siplified scheatic of aplifier with boosted cascode load 8 Fig 31 Block diagra of the cascaded TIA 83 Fig 313 Block diagra of the TIA w/ current pre-aplification for gain boosting 84 Fig 314 Diagra of a ultiple-stage aplifier with local shut-shunt feedback 85 Fig 315 Diagra of a ultiple-stage aplifier that shows Cherry-Hooper concept 86 Fig 316 Scheatic of an RGC TIA 87 Fig 317 Block diagra of TIA showing both series- and shunt-peaking concept 90 Fig 318 Scheatic of an aplifier with capacitive coupling for BW enhanceent 91 Fig 319 Scheatic of inverter buffer with capacitive load 93 Fig 30 Siplified scheatic of a 50Ω-atched output buffer 95 Fig 31 Scheatic of the two-stage RGC TIA 97 Fig 3 Micrograph of the fabricated IC 100 Fig 33 Siplified scheatic of the easureent setup 101 Fig 34 Measured frequency response of the RGC TIA 10 Fig 35 Spectru and phase-noise of the 35MHz oscillator ade with RGC TIA 103 Fig 36 Scheatic of the Inverter TIA 104 Fig 37 Measured frequency response of the Inverter TIA (V DD =3V) 106 Fig 38 Measured frequency response of the Inverter TIA (V DD =5V) 107 Fig 39 Spectru and phase-noise of the 35MHz oscillator ade w/ Inverter TIA 108 Fig 330 Scheatic of the three-stage tunable feedback TIA (biasing not shown) 109 Fig 331 Measured gain of the three-stage feedback TIA 111 Fig 33 Micrograph of the fabricated die 11 Fig 333 Phase-noise of the 08MHz and 496MHz oscillators 11 xii

13 Fig 334 Scheatic of the two-stage differential TIA with inductive shunt peaking 113 Fig 335 Differential transipedance gain of the TIA with inductive shunt peaking 115 Fig 336 Input-referred current noise of the TIA 115 Fig 337 Spectru and phase-noise of the 06MHz AlN-on-Si oscillator 116 Fig 338 Scheatic of the TIA with current aplification stage 119 Fig 339 TIA gain when the S-paraeters are interfaced with ideal current source 10 Fig 340 Measured input-referred noise of the TIA with pf input load 11 Fig 341 Large-signal gain and BW behavior of the TIA (loading = pf) 1 Fig 34 Measured output spectru and phase-noise of 1006GHz oscillator 13 Fig 343 Micrograph of the IC when interfaced with the 74MHz resonator 14 Fig 41 Block diagra of a pierce oscillator 130 Fig 4 Block diagra of the oscillator that uses parallel tuning 131 Fig 43 Scheatic of the three-stage CMOS tunable TIA 13 Fig 44 Output spectru of the 497MHz tunable oscillator 13 Fig 45 Diagra of the tunable icroechanical oscillator that uses series tuning 135 Fig 46 Series tuning liitation for 500MHz lateral icroechanical oscillator 138 Fig 47 Concept of tuning enhanceent based on active inductor cancellation 141 Fig 48 Scheatic and equivalent odel of the single-transistor active inductor 14 Fig 49 Concept of tuning enhanceent based on negative capacitance cancellation 144 Fig 410 Concept of negative ipedance converter (NIC) 145 Fig 411 Scheatic of the single-port negative ipedance generator 145 Fig 41 Electrical odel of the single-port negative capacitance generator 146 Fig 413 Response and SEM view of the 47MHZ AlN-on-Si resonator 148 Fig 414 Scheatic of the tunable TIA w/o shunt parasitic cancellation 149 Fig 415 Chip Micrograph of the TIA without shunt capacitive cancellation 150 xiii

14 Fig 416 AC gain and phase of the tunable TIA w/o shunt parasitic cancellation 150 Fig 417 Frequency vs voltage for the 47MHz oscillator w/o tuning enhanceent 151 Fig 418 Scheatic of the tunable TIA with active inductance cancellation 15 Fig 419 Chip Micrograph of the TIA with active inductance cancellation 153 Fig 40 AC gain and phase of the tunable TIA with active inductance cancellation 153 Fig 41 Frequency vs voltage for the 47MHz oscillator with active inductor 154 Fig 4 Scheatic of the tunable TIA with negative capacitor 155 Fig 43 Chip view of the TIA (and tep copensation) with negative capacitor 156 Fig 44 AC gain and phase of the tunable TIA with negative capacitor 156 Fig 45 Frequency vs voltage for the 47MHz oscillator with negative capacitor 157 Fig 46 Phase-noise of the 47MHz oscillator with negative capacitor 158 Fig 47 Frequency vs the tune voltage for 47MHz oscillators 159 Fig 51 Resonator structure with ebedded silicon oxide layer for TCF reduction 163 Fig 5 Block diagra of teperature-copensated SiBAR oscillator [6] 165 Fig 53 Block diagra of the open-loop electronic teperature copensation 166 Fig 54 Scheatic of the bandgap and PTAT reference generators 169 Fig 55 Siulated and easured output of the bandgap reference 169 Fig 56 Siulated and easured output of the PTAT reference 170 Fig 57 Scheatic of the two-stage OTA with iller copensation 170 Fig 58 Block diagra of the square-root generator [] 171 Fig 59 Scheatic of the linear V-to-I converter 17 Fig 510 Output current of the linear V-to-I converter 173 Fig 511 Output of the square root generator and linear V-to-I converter 173 Fig 51 Response of the teperature-copensated 441MHz AlN-on-Si resonator 175 Fig 513 Frequency drift of the 441MHz icroechanical oscillator 176 xiv

15 Fig 514 Measured phase-noise of the 441MHz icroechanical oscillator 177 Fig 515 Diagra of the electronically teperature-copensated oscillator 178 Fig 516 Variation in oscillation frequency vs teperature in -10ºC to 70ºC range 179 Fig 61 Concept of phase-noise in oscillators 183 Fig 6 Phase-noise spectru of a typical feedback oscillator 184 Fig 63 Linear odel for the phase-noise analysis of feedback oscillator 187 Fig 64 General block diagra of the LTV phase-noise odel 188 Fig 65 Equivalent odel with 1 st -order parasitics for series-resonant oscillator 194 Fig 66 Equivalent odel with nd -order parasitics for series-resonant oscillator 196 Fig 67 Variation in phase-noise perforance with C p 0 Fig 68 Frequency response of the 97MHz capacitive SiBAR 04 Fig 69 Output spectru and phase-noise of the 97MHz capacitive oscillator 05 Fig st - and nd -order odel fit to the phase-noise of the 97MHz oscillator 05 Fig 611 Frequency response of the 463MHz TPOS resonator 06 Fig 61 Frequency response of the 1006GHz TPOS resonator 07 Fig 613 Output spectru and phase-noise of the 463 MHz AlN-on-Si oscillator 08 Fig st - and nd -order odel fit to the phase-noise of the 463MHz oscillator 09 Fig st - and nd -order odel fit to the phase-noise of the 1006GHz oscillator 10 Fig 71 Spectru and phase-noise of the 463MHz oscillator in nonlinear region 16 Fig 7 Block diagra of the single-resonator dual-frequency TPOS oscillator 18 Fig 73 Response of the 1 st /5 th order resonator: air, (a), (c) and vacuu, (b), (d) 19 Fig 74 The block diagra of the switching network 19 Fig 75 Phase-noise and spectru of fundaental ode of the 1 st /5 th oscillator 0 Fig 76 Phase-noise and spectru of higher order ode of the 1 st /5 th oscillator 0 Fig 77 Diagra of the dynaic closed-loop teperature copensation 3 xv

16 Fig 78 General block diagra of the swept-tuned spectru analyzer 4 Fig 79 General block diagra of the echanical spectru analyzer 4 xvi

17 SUMMARY Frequency reference oscillator is a critical coponent of odern radio transceivers Currently, ost reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incopatible with standard icro-fabrication processes Moreover, their frequency liitation (<00MHz) requires large up-conversion ratio in ultigigahertz frequency synthesizers, which in turn, degrades the phase-noise Recent advances in MEMS technology have ade realization of high-frequency on-chip low phase-noise MEMS oscillators possible Although significant research has been directed toward replacing quartz crystal oscillators with integrated icroechanical oscillators, their phase-noise perforance is not well odeled In addition, little attention has been paid to developing electronic frequency tuning techniques to copensate for teperature/process variation and iprove the absolute frequency accuracy The objective of this dissertation was to realize high-frequency teperature-copensated high-frequency (>100MHz) icroechanical oscillators and study their phase-noise perforance To this end, low-power low-noise CMOS transipedance aplifiers (TIA) that eploy novel gain and bandwidth enhanceent techniques are interfaced with high frequency (>100MHz) icroechanical resonators The oscillation frequency is varied by a tuning network that uses frequency tuning enhanceent techniques to increase the tuning range with inial effect on the phase-noise perforance Taking advantage of extended frequency tuning range, and on-chip teperature-copensation circuitry is xvi

18 ebedded with the sustaining circuitry to electronically teperature-copensate the oscillator Finally, detailed study of the phase-noise in icroechanical oscillators is perfored and analytical phase-noise odels are derived xvii

19 CHAPTER 1: Introduction This research study covers the design and ipleentation of high frequency (>100MHz) low phase-noise teperature-copensated integrated icroechanical reference oscillators that are intended as priary replaceent for low frequency quartz crystal reference oscillators in ulti-gigahertz OFDM-based 3G and 4G wireless radio transceivers The oscillators rely on both capacitively- and piezoelectrically-transduced bulk acoustic resonators as the resonating tank Significant effort is ade to explore lowpower low-noise techniques that greatly increase both gain and 3-dB bandwidth (BW) of the CMOS sustaining aplifiers Moreover, electronic frequency tuning techniques with inial effect on the phase-noise perforance are suggested and novel techniques to significantly iprove the frequency tuning range in the presence of parasitic effects fro the resonator are developed To iprove the short-ter teperature stability of the reference oscillator, an on-chip teperature copensation circuitry that extensively relies on the ebedded frequency tuning capability of the oscillator is utilized The output of the teperature copensation block that consists of an accurate teperature sensing unit and a control signal generation unit is appropriately scaled and applied to the frequency tuning network to electronically copensate for the teperature drift of the oscillator in coercial (-10ºC to 70ºC) and industrial (-40ºC to 85ºC) teperature ranges Finally, the phase-noise perforance of icroechanical oscillators is explored in detail Aong iportant factors the effect of different parasitic sources fro resonator and sustaining aplifier including those caused 1

20 by the frequency tuning enhanceent network on the phase-noise perforance is studied and analytically odeled 11 Origin and History of Reference Oscillators Frequency reference oscillator is a pivotal block in the design of radio transceivers as it significantly affects the perforance and size of the transceiver [1] During the past three decades, the reference oscillators have been built based on high-q quartz crystal oscillators [] Their superior stability and absolute frequency accuracy has allowed the to be the industry s preferred choice for frequency synthesis application (Fig 11) However, eerging applications in electronic systes (and ulti-ode radio frequency applications in particular) have created a nuber of challenges that can not be addressed by traditional quartz crystal reference oscillators Fig 11 Miniaturized Quartz Crystal Today s ulti-gigahertz syste-on-chip (SOC) applications require high frequency (>00MHz) integrated reference oscillators that exhibit siilar phase-noise and stability perforance to those of the quartz crystal oscillators This is especially probleatic for higher data transceivers that rely on OFDM-based 3G/4G standards whose error vector agnitude (EVM) requireents calls for very low phase-noise floor [3], [4] The iediate iplication for frequency synthesizers that use low-frequency quartz reference oscillators is to reduce the bandwidth of the loop filter to the point that accoodating

21 the filter on chip ay not be practically feasible Another shortcoing of quartz crystals is inherent incopatibility of their fabrication process with standard integrated circuits such as CMOS Micro-size quartz crystals have helped with reducing the overall for factor of quartz crystal reference oscillators in recent years In addition, soe copanies have invested on integrating the quartz crystals in the sae package with the rest of the electronic circuitry [5] However, the oscillator is still large coparing to the other blocks of the single-chip transceiver fabricated in advanced CMOS processes As the result, ultiode radio transceivers have to rely on a single clock to deliver ultiple reference frequencies with different phase-noise specification [3] This difference in the phasenoise puts a strain on the frequency synthesizer Microechanical oscillators, on the other hand, offer significantly saller for factor, higher frequency of operation, ultiode operation, and potential integration with IC while delivering near-crystal phasenoise/jitter perforance [6]-[8] During the past two decades, researchers have focused on the application of icroechanical oscillators as replaceent for low-frequency quartz crystal reference oscillators The oscillators priarily rely on two types of icroechanical resonators: capacitively-transduced and piezoelectrically-transduced icroechanical resonators Capacitive transducers create an electrical force that will be used to excite a particular resonance ode of the icroechanical structure Piezoelectric icroechanical 3

22 resonators take advantage of electroechanical coupling caused by piezoelectric transduction in certain aterials to excite the resonance ode of the structure A wide variety of capacitive icroechanical resonators have been used to build reference oscillators [9], [6], [8] Earlier prototypes have extensively used flexural-ode capacitive bea resonators operating between 10kHz to 10MHz [9] More recent work has extended the frequency range into the upper HF range (~0MHz) [10] (Fig 1) The sall power handling of bea resonators that is ainly due to its sall ass cobined with the reduced nonlinearity threshold caused by sall gap size that fors the transducer negatively affects the phase-noise perforance of the oscillator In addition the need for autoatic level control circuits used to keep the oscillation aplitude fro reaching above the linear liit adds to the coplexity of the syste and further deteriorates the overall phase-noise perforance of the oscillator [10] Fig 1 Block diagra of 19MHz icroechanical oscillator [10] Iproveent to the design of the flexural bea resonators has resulted in significant increase in Q and power handling while preserving the large frequency tuning range of the resonator The tuning range can be used to electronically copensate the frequency drift with teperature In 004, researchers at Discera, Inc have reported a 70MHz 4

23 oscillator with siulated TCF below 0pp/ºC with output power exceeding 0dB and easured phase-noise ~-117dBc/Hz at 1kHz offset with floor reaching below - 130dBc/Hz [11] (Fig 13) The ain disadvantage of using flexural bea resonators at high frequency is their high otional resistance (in this case ~16kΩ at V p =7V) that requires electronics with large GBW that naturally include ore active eleents which exhibit ore theral and flicker noise This increased noise content directly shows up in the phase-noise perforance Fig 13 Diagra and phase-noise of the teperature-stable 70MHz oscillator [11] Another category of capacitive icroechanical oscillators use bulk acoustic wave resonators (BAW) These resonators excite an extensional bulk ode of the low-acousticloss aterial and exhibit larger echanical stiffness and as such, have larger power handling capability [1] In addition, they exhibit higher Q and lower loss, both critical for low-power low-phase noise oscillators The fundaental resonance frequency for the ajority of these BAW resonators is in the VHF range [8] but it has been shown that they can operate at uch higher frequencies well into the UHF range [13], [14], [15] potentially extending the oscillation frequency beyond 1GHz [1], [6] 5

24 Bulk extensional ode devices originated with disk resonators in early 000 s [16] [17] The early prototypes had high loss and therefore unsuitable for low-power oscillator applications However, the eventual iproveent in the perforance (both Q and loss) led to the developent of first capacitive icroechanical oscillator in VHF range at the University of Michigan [8] whose phase-noise perforance was coparable with coercial quartz crystal oscillators The resonator was a 60MHz wine glass disk resonator that was excited in its nd extensional ode and the sustaining aplifier was a siple fully-differential TIA fabricated in 035μ CMOS (Fig 14) More recent work has focused on using a icroachined silicon bar as a resonating aterial These resonators are ade of a relatively-thick single-crystal silicon bar that is separated fro electrodes by very narrow capacitive gaps [18] Called silicon bulk acoustic resonators (SiBAR), they offer siilar Q but significantly saller loss in upper VHF range [19] Due to very large echanical stiffness of BAW resonators, the electrostatic frequency tuning range is very liited [1] As such, designers have been forced to search for alternative ethods that enable sufficient tuning range for process/teperature copensation A proven ethod is icro-oven control in which the resonator body is heated up by passing a controlled DC current through the resonator, thus changing its teperature-dependent resonance frequency [6] While this ethod offers high accuracy (<±0pp) and does not have a ajor ipact on the phase-noise, its deand for high DC power (>50W) akes it unattractive for any low power applications A 103MHz 6

25 prototype teperature-copensated SiBAR oscillator is reported with phase-noise below -108dBc/Hz at 1kHz offset and total teperature drift of 39pp in 100ºC (Fig 15) [6] To address the liitation in tuning range without sacrificing high Q and low loss of BAW resonators another category of BAW resonators that use a cobination of bulk and flexural odes has been developed [0] The device benefits fro large flanges that are placed at the end of several extensional beas These flanges increase the capacitive transduction area and hence increase the tuning range Due to the specific geoetry, these devices are called I-shaped Bulk Acoustic Resonator (IBAR) Tuning range approaching 5000pp is reported for prototype in 5-0MHz [1] and is used for electrostatic teperature copensation (Fig 16) [] The ajor proble with these resonators is their inherent liitation for frequency of operation that is a direct outcoe of the echanical design of the resonator State-of-the-art coercial capacitive icroechanical reference oscillators have been designed and optiized with the intention of copeting with quartz crystal oscillators for variety of applications in consuer electronics, clock generation for coputers, and counication [3] As such, these reference oscillators are usually ade with wellcharacterized low-frequency (<30MHz) capacitive resonators Using single-chip prograable fractional-n frequency synthesizers, a wide range of frequencies have becoe available that greatly reduce the power consuption, size, cost, and coplexity of the syste [3] Moreover, added functionality in the for of frequency tuning and process/teperature copensation can be available as well More recent products take 7

26 advantage of four-terinal icroechanical resonators to deliver highly stable fullydifferential prograable reference oscillators with lower jitter (Fig 17) [3] Still, due to the low frequency of the resonator, the phase-noise perforance significantly deteriorates towards the higher-end of the frequency range (>300MHz) for large upconversion ratios of the synthesizer In addition, the need for vacuu packaging continues to be a ajor obstacle toward achieving very cheap icroechanical oscillators [4] Fig 14 Block diagra of 60MHz disk icroechanical oscillator [8] Fig 15 Block diagra of 103MHz teperature-copensated SiBAR oscillator [6] 8

27 Fig 16 General block diagra of teperature-copensated IBAR oscillator [] One of the biggest challenges in creating stable reference oscillators is to achieve frequency stability in presence of variations in process, teperature, and power supply Most quartz crystal oscillators take advantage of high absolute frequency accuracy (<10pp) and inherently-sall teperature drift of the quartz crystal resonator (<100pp in -40ºC to 85ºC) to deliver an accurate teperature- and process-insensitive clock [5] However, for ore accurate (<10pp in -40ºC to 85ºC) crystal oscillators such as teperaturecontrolled crystal oscillators (TCXO), teperature and process copensation is necessary The teperature copensation is usually achieved by accurately sensing the teperature variation and then adjusting the oscillation frequency [5] For ost applications, on-chip teperature sensors are sufficiently accurate These sensors use bandgap and proportional-to-absolute teperature (PTAT) references to accurately predict the teperature difference 9

28 Due to large teperature coefficient of frequency of ost coercially-available icroechanical oscillators ( TCF >5pp/ºC), prograable icroechanical oscillators rely on closed-loop teperature copensation ethods [6] Closed-loop ethods are usually built around the phase locked loop (PLL) that is readily available as part of the high-resolution fractional-n frequency synthesizers used in the prograable oscillators [3] Therefore, the PLL-based closed-loop ethod is capable of providing ultra-stable oscillation with teperature drift less than 01pp/ºC Fig 17 SiTie s Ultra-thin high perforance MEMS reference oscillator [3] Piezoelectric icroechanical resonators can be traced back uch further than capacitive resonators The first prototypes were introduced in 1960 s [7] This is partly due to the fact that the principle of operation is siilar to quartz crystals; they both take advantage of high electroechanical coupling in piezoelectric transduction There are two iportant categories for piezoelectric resonators: bulk acoustic wave (BAW) [8] and surface acoustic wave (SAW) [9] For a given area, the piezoelectric transduction is uch larger than capacitive transduction This larger force results in significantly lower 10

29 loss for piezoelectric resonators copared with their capacitive counterparts and akes the very attractive for low-power oscillator applications Piezoelectric icroechanical oscillators usually take advantage of resonators operating in a bulk ode for higher Q and hence, lower phase-noise [30] Bulk ode resonators are divided into two categories: lateral and thickness-ode devices Siilar to capacitive resonators, an extensional ode is excited in lateral piezoelectric resonators [30] Due to the liitation in the lithography, these resonators tend to operate at lower frequencies in the VHF range [31] More recent work has pushed the resonance frequency of these resonators above gigahertz [3] While high frequency piezoelectric SAW oscillators have been popular since the early 1980 s [33], research on piezoelectric BAW oscillators ade little progress until early 1990 s [34] Earlier versions priarily used think-fil bulk acoustic resonators (FBAR) ade of AlN that were designed for lower UHF range The fabrication process of these resonators allows for integration with standard IC fabrication processes (Fig 18) [34] FBAR resonators enjoy very low loss (otional resistance < 10Ω) while aintaining high Q (>1000) This is a direct ipact of high electroechanical coupling cobined with large transduction area of the FBAR The large area of FBAR gives rise to unwanted feedthrough coupling (usually in the for of capacitance) between the input and output terinals 11

30 Fig 18 Co-integration of thin-fil bulk resonator with Si Bipolar process [34] FBAR technology has ade great strides to a state that coercial prototypes in upper UHF range are easily accessible in the arket The design of FBARs have been perfected for iproved power handling that enables low phase-noise reference oscillators with high output power Soe researchers have shown that oscillators ade with these resonators significantly outperfor LC oscillators and can potentially eet the strict far-fro-carrier phase-noise specification of broadband OFDM-based wireless standards such as 8011n [35], [36] A quadrature VCO oscillator based on a coercial 1GHz FBAR has been deonstrated and copared with an LC oscillator with on-chip passives in [36] Incredibly-sall loss of the FBAR has enabled sub-w oscillator (~600μW) with phasenoise approaching -155dBc/Hz at 10MHz offset fro carrier (Fig 19) Considering the potential for post-cmos fabrication copatibility of FBAR that uses AlN as piezoelectric transducer, FBAR oscillators can potentially copete with LC oscillators in delivering a fully on-chip solution for wireless standards Still, one has to be indful of relatively-poor close-to-carrier phase-noise perforance in coparison with copetitors such as crystal or capacitive icroechanical oscillator even when the synthesizer upconversion is increased beyond 100 Due to very low loss of FBAR, electronic frequency tuning is easier The tuning, achieved by series tunable capacitors that introduce phase-shift in the loop, is usually 1

31 sufficient for teperature and process copensation [37] This tunable capacitor can be integrated with the resonator [38] or can be placed on the sustaining aplifier [36] In both cases, liited Q of these tunable capacitors significantly increases the Q loading in the oscillator and negatively affects the phase-noise perforance Material-based teperature copensation is also popular Insertion of SiO layer in the FBAR stack helps reduce the TCF but drastically reduces the Q for the thickness ode operation by as uch as 3 [39] Fig 19 1GHz FBAR VCO and its phase-noise copared to an LC VCO [36] The concept of lateral piezoelectric oscillators was first explored at very low frequency on cantilever beas These resonators offered high Q (>1,000) and low loss but due to their very low resonance frequency (<100kHz), early prototypes were very large and naturally unsuitable for integration with IC [40] Power handling was also a valid concern Most of these low frequency resonators were fabricated on a thin substrate with low-stiffness Therefore, the resonator threshold for nonlinear operation was low and the phase-noise perforance of the oscillator was poor In addition, soe resonators were ade of piezoelectric aterials such as ZnO that are inherently incopatible with standard IC processes (Fig 110) [40] 13

32 Fig 110 Block diagra of the lateral piezoelectric oscillator [40] The research continued on both low-frequency [41] and high-frequency laterally-excited piezoelectric resonators [4] As discussed before, low frequency resonators were designed to replace quartz crystals To this end, special effort was ade to increase the Q and power handling capability, and reduce the loss [43] Several categories of lateral piezoelectric resonators were explored [1], [44] While operating in the first fundaental resonance ode of the structure sees to be a natural choice for any low frequency applications, it turns out that higher frequency odes of the sae structure ay provide siilar fq at lower loss [1] Most lateral piezoelectric resonators required reference electrode in addition to input and output electrodes The reference electrode, coonly known as reference ground, was used to ensure all voltages on the resonator are properly referenced This research resulted in piezoelectric oscillators in lower VHF range [44] Several designs were studied to iprove the Q and power handling and at the sae tie, reduce the loss of the resonator Multi-finger topology was used to reduce the loss of the resonator by placing several 14

33 electrodes in parallel [30] Another approach is to take advantage of echanical coupling to increase the transduction area and reduce the loss without sacrificing the Q of the resonator As an exaple an 81MHz oscillator based on a 1-resonator coupled array piezoelectric resonator is deonstrated The resonator has unloaded Q of ~ 3,000 and otional resistance ~ 00Ω The sustaining aplifier is a W single-transistor NPN [44] The oscillator achieves phase-noise better than -7dBc/Hz and -137dBc/Hz at 1kHz and 10MHz offset, respectively (Fig 111) It is clearly shown that the power handling capability is iproved copared to a ulti-finger resonator [44] An iportant advantage of thin-fil piezoelectric-on-substrate (TPOS) resonators is that their fabrication process can be easily adapted to include a thin layer of SiO layer that can be used for aterialbased passive teperature copensation [1] Using a thin SiO layer, the TCF of the 81MHz lateral piezoelectric oscillator is lowered to -pp/ºc (Fig 11) [44] Fig 111 Scheatic and easured phase-noise of the 81MHz oscillator [44] Frequency (MHz) Teperature (degrees C) Fig 11 Measured TCF of the 81MHz lateral piezoelectric oscillator [44] 15

34 Aong lateral piezoelectric oscillators, contour ode AlN resonators have attracted a lot of attention [45] [46] These resonators are capable of offering high power handling and high Q when integrated with CMOS electronics [45] Researchers at Sandia National Laboratory have developed a single-chip ulti-frequency AlN contour ode oscillator that operates at 0, 80 and 100MHz [45] The phase-noise profile shows better than - 90dBc/Hz at 1kHz offset for 100MHz oscillation (Fig 113) More recent studies have focused on pushing the frequency above 100MHz The design of these resonators is very siilar to low-frequency resonators except that the resonator is operated at higher width-extensional ode of the sae structure [7], [46] A MHz oscillator with phase-noise better than -88dBc/Hz at 1kHz offset and phase-noise floor approaching -160dBc/Hz is reported in [46] The sustaining aplifier is a siple 10W pierce topology that is fabricated in 05μ CMOS process The lack of silicon substrate has reduced the power handling of the resonator below 0dB This reduced power handling, as expected, has a negative ipact on the phase-noise perforance of the oscillator (Fig 114) Fig 113 Chip view and phase-noise of the ulti-frequency ALN oscillator [45] 16

35 An iportant proble with lateral piezoelectric resonators is frequency tuning Apart fro liitation caused by the absence of polarization voltage in conventional piezoelectric transducers, lateral piezoelectric resonators usually suffer fro large shunt parasitic capacitors to the reference electrode that seriously ipede the realization of electronically-tuned piezoelectric icroechanical oscillators [47] This is a uchneeded first step toward fully teperature and process copensated lateral piezoelectric reference oscillator and a giant leap fro current aterial-based teperaturecopensated lateral piezoelectric reference oscillator [48] Fig 114 View of the MHz oscillator and its easured phase-noise [46] Although piezoelectric icroechanical oscillators present treendous opportunity for delivering low jitter and low power frequency synthesizer solution for wireless applications, they have been largely ignored by industry This could be due to the poor absolute frequency accuracy of the resonators at high frequency as well as their liited tuning range, esp for lateral piezoelectric oscillator which akes it hard to copensate for teperature and process variation The only exception is FBAR oscillators that are being considered as a possible alternative for low power single-chip ediu perforance oscillators for wireless applications However, the excessive Q loading 17

36 caused due to very sall otional resistance of FBAR device when interfaced with sustaining aplifier continues to be a challenge for achieving a phase-noise profile that is coparable to that of the up-converted quartz crystal oscillator 1 Reference Oscillator Requireents and Classifications There are several iportant characteristics for reference oscillators that are shared between icroechanical and other types of reference oscillators: 11 Short-Ter Stability Short-ter stability is probably the single ost iportant perforance criterion of the oscillator and is a easure of frequency stability of the oscillator in steady-state operation The short-ter stability is usually expressed with phase-noise or jitter The jitter is partitioned into two section rando jitter (RJ) and deterinistic jitter (DJ) and usually expressed in unit intervals (UI) Deterinistic jitter is dependent to the data pattern dependant jitter and is attributed to a unique source This type of jitter is usually not a source of concern in reference oscillators The rando jitter is due to the noise fro electronics and typically exhibits a Gaussian distribution There are several different types of rando jitter: absolute jitter, cycle-to-cycle jitter, periodic jitter, peak-to-peak jitter, edge-to-edge jitter, integrated jitter (frequency doain) The ost iportant jitter quantities are absolute and cycle-to-cycle jitters The absolute jitter is the instantaneous variation in oscillation frequency and for a periodic signal and its RMS value can be related to the phase-noise by [49]: ΔT + π abs, rs = SΦn( f ) T0 df, (1-1) 18

37 where T abs,rs is the RMS value of the absolute jitter, T 0 is the period of the oscillation, f is the frequency, and S Φn (f) is the power spectral density of the output signal at frequency f Exaination of this forula reveals that the jitter is calculated fro the equivalent area under the spectru of Φ n and then noralized to the period of oscillation In other words, integrating the area under the phase-noise curve and then noralizing the result to T 0, gives out RMS value of the integrated jitter Cycle-to-cycle jitter of a free running oscillator can be related to its phase-noise by: 4π ΔT cc S 3 Φ ω0 ( f ) df, (1-) where T cc is the cycle-to-cycle jitter, ω 0 is the frequency of the oscillation, and S Φ (f ) is the relative phase-noise power at an offset frequency of f The iportant property of the cycle-to-cycle jitter that akes it a ore accurate representation of oscillator shortter stability is the fact that it does not require a reference signal 1 Long-Ter Stability Long-ter stability is a easure of frequency stability over the factors influenced by the environent (such as teperature, huidity and acceleration) and tie The aging easureent is usually conducted by advanced tools that cycle the teperature according to a pre-specified test pattern This pattern eulates the effect of aging for the oscillator The response to huidity can be easured in a well-controlled huidity chaber The frequency drift with teperature is usually expressed in pp/ºc and is obtained with the help of a teperature chaber 13 Absolute Frequency Accuracy 19

38 This is a easure of accuracy of the oscillation frequency and after short-ter stability is the ost iportant perforance etric that is specified for reference oscillators This quantity is usually expressed in pp There are several standards that each iposes a certain liitation on the axiu inaccuracy of the oscillator frequency The ajority of standards for consuer arket put a cap on the total variation at 50pp; however, there are soe applications that can tolerate as uch as 1000pp More deanding applications ay require better than ±10pp accuracy As entioned earlier, due to inherently low accuracy of ost icroechanical oscillators, this level of accuracy usually calls for fractional-n frequency synthesizer solution 14 Frequency Tuning Frequency tuning is an essential property of every reference oscillator This is necessary to adjust the oscillation frequency and potentially copensate for teperature and process variation The tuning range is defined as the axiu range that the oscillation frequency can be systeatically varied while still reains under control Most icroechanical reference oscillators use a very stiff icroechanical resonator with liited tuning range below 1000pp 15 Wavefor Shape The oscillation wavefor is typically a sinusoidal or a square This shape is usually deterined by nonlinearity of the oscillator that is influenced by a variety of factors including the circuit nonlinearity and resonator power handling Most low phase-noise crystal or icroechanical reference oscillators deliver a near sinusoidal output wavefor Oscillation power is also iportant in deterining the phase-noise perforance of the oscillator 0

39 16 Power Consuption Power consuption of the oscillator is another key etric that has recently becoe an issue for integrated solutions in advanced IC processes where the reduction in supply voltage has pushed the overall power consuption down to a few illiwatt Low frequency reference oscillators with power dissipation in the range of few tens of icrowatt and gigahertz reference oscillators with power dissipation in the range of a few illiwatt are being explored for sensing and counication applications, respectively 17 Size The size requireent is ainly driven by the need for axiu integration The integration with IC coes at a significant increase in cost which directly affects the coercial viability of the single-chip solution All of these criteria play a role, to a degree, in deterining the perforance of a reference oscillator Fro a syste designer s point of view, the designers should focus their efforts to axiize the short-ter and long-ter stability, tuning range and absolute frequency accuracy and at the sae tie iniize the size and power consuption However, this task is proved to be ore challenging than anticipated There is a fundaental trade-off between stability and tuning range of the oscillator; a ore stable oscillator tends to resist any change in the oscillation frequency Moreover, the frequency accuracy is usually coproised for oscillators with very sall for-factor due to the inherent inaccuracy of fabrication processes when dealing with sall feature sizes Based on their perforance, reference oscillators fall into one of these three categories: 1

40 Low perforance: low perforance oscillators exhibit poor short-ter and long-ter stability as well as low frequency accuracy but they usually offer ore flexibility in ters of frequency tuning, size, and power consuption These reference oscillators are ainly intended as low-cost on-chip solutions with significant tuning range (usually ore than 10%) and are available in a wide frequency range fro a few khz to tens of GHz Faous exaples are CMOS ring oscillator for low frequency and LC oscillator for high frequency that can be used to generate clock for icroprocessors A control signal is usually available to tune the frequency For higher frequency, a control signal generation unit is used in a feedback loop to eet the required accuracy specification High perforance: high perforance solutions are usually built around a crystal oscillator in PLL loop High-Q icroechanical resonators (Q>50,000) have begun to replace quartz crystals as the preferred resonating tank in the reference oscillator for high-perforance solutions While these reference oscillators offer excellent stability (both short-ter and long-ter) and frequency accuracy, they are relatively large, especially in the case of quartz crystals that are off-chip, and very hard to tune In addition, significantly higher power dissipated in PLL circuits akes the unattractive for low power applications These solutions are ideal for wireless radio transceivers; for exaple, ost cellular transceivers whether G or newer OFDMbased 3G systes rely on high perforance quartz crystal oscillators to achieve ultralow jitter perforance [50] The phase-noise requireents for soe of the wellknown cellular and broadband wireless standards are suarized in Table 11 Fro

41 Table 11, it is clear that reference oscillators used to generate clock for high data-rate cellular standards such as HSDPA with 16QAM or 64QAM odulation require soe of the toughest close-to-carrier phase-noise specifications However, the phase-noise requireents of older cellular standards such as GSM continue to pose a challenge for iniaturized and fully on-chip icroechanical reference oscillator solution Table 11 Phase-Noise Requireent for Cellular and Broadband Wireless Standards Standard Carrier Freq Modulation Close-to-Carrier PN Far-fro-Carrier PN GSM 900MHz GMSK [51] [5] WCDMA 1GHz QPSK HSDPA 17GHz to 1GHz 16QAM -83dBc/Hz in-band [53] [53] 8011n 4GHz 64QAM -91dBc/Hz in-band WiMax 3GHz 64QAM -95dBc/Hz in-band Another application of high perforance frequency reference oscillators is the clock for data converters [54] The clock jitter liits the overall SNR of the data converter and sets an upper liit to the effective nuber of bits In advanced counication transceiver systes, designers usually partition the total jitter budget into several parts and allocate a jitter budget for the ADC Fig 115 illustrates the challenges posed by clock jitter in increasing the resolution and speed of data converters It is clear that high-speed ADC with conversion rate over 300MS/s can only tolerate a very sall clock jitter of less than 05ps to achieve 10 bit accuracy This stringent specification require a high perforance clock with excellent short-ter stability whose design is further coplicated for icroechanical resonators with significantly higher loss than quartz crystals Fro Fig 115, a 300MS/s 10bit 3

42 Nyquist converter requires a high frequency icroechanical reference oscillator with Q in the range of 0,000 For an ADC, the total SNR degradation of an ADC can be expressed as: SNR ADC SNR Jitter 0 0 SNR (deg radation) = 0log , (1-3) where SNR Jitter is the SNR of the ADC due to the clock jitter The theoretical liit on SNR Jitter is given by: SNRJitter, db 0 10 Δ Trs =, (1-4) πf osc where f osc is the clock frequency The relationship between the total phase jitter of the reference clock and the phasenoise can be expressed as: ΔT phase = ( πf ) osc + 0 L ( f ) sin ( πf ) df, (1-5) where L(f ) is the phase-noise at frequency f offset fro carrier and for an oscillator that uses a resonator with a nd order bandpass response can be approxiated by: L FkT 1 f f +, (1-6) ( ) osc α f = 1+ 1 Posc f Qloaded f where F, k, T, P osc, f α, Q loaded, and f are noise factor, Boltzan s constant, teperature (in Kelvin), power of the oscillation signal, a constant related to flicker noise corner, loaded Q of the resonator, and offset frequency 4

43 Mediu perforance: oscillators in this category stand in the iddle between low perforance and high perforance oscillators They offer extended tuning range and burn less power than the high perforance oscillators but have worse jitter profile and frequency accuracy Low frequency icroechanical reference oscillators that use lower Q (Q<10,000) but low loss (<100Ω) resonators fall in this category These oscillators offer an ideal solution for wireline broadband data transfer applications The jitter tolerance requireents for soe of the well-known broadband optical standards based on GR-53-CORE SONET are listed in Table 1 These relatively relaxed requireents even allow for LC oscillators with on-board high-q passives to be able to eet ost of the jitter specifications shown in Table 1 5

44 Fig 115 SNR vs clock jitter for ADCs [55] Table 1 Jitter Requireent for Broadband Optical Standards Standard Rate Close-To-Carrier Jitter (f 1 ) Far-Fro-Carrier Jitter (f ) OC-1 6M 01 UI p-p (10UI RMS 161UI p-p (161UI RMS OC-48 5G 01 UI p-p (10UI RMS 40UI p-p (40UI RMS OC-19 10G 03 UI p-p (30UI RMS 01UI p-p (10UI RMS OC G 6 UI p-p (60 UI RMS 015UI p-p (15UI RMS 6

45 13 Organization This dissertation is organized into seven chapters; Chapter 1 starts with brief introduction to icroechanical oscillators and their proble It then briefly touches on the history of icroechanical oscillators and provides exaples of the prior work At the end, it proposes appropriate solutions for different applications and fits the into three perforance categories Chapter discusses the fundaentals of icroechanical oscillators that include the sustaining aplifier, icroechanical resonator, and aplitude control unit In this chapter the capacitive and piezoelectric icroechanical resonators and their electrical odels are studied Chapter 3 discusses the sustaining aplifier that is usually designed as transipedance aplifier for series-resonant icroechanical oscillators The topics covered in this chapter include open-loop and closed-loop TIAs and their frequency and noise response, low-power high perforance techniques (both bandwidth and gain enhanceent), design trade-offs, design exaples and their easured perforance and finally the coparison of different techniques Tuning echaniss for icroechanical oscillators are discussed in Chapter 4 The discussion starts with general description of the tuning ethods for icroechanical oscillators that includes both resonator-based and electronic tuning Exaples of prior art are also provided as suppleent to this section The reainder of this chapter focuses on electronic tuning echaniss for icroechanical oscillators, esp those based on lateral icroechanical resonators The discussion starts with the fundaentals of series and parallel tuning and inherent liitations on tuning range that is faced when applying these techniques to high frequency lateral icroechanical oscillators The solutions to these shortcoings that significantly enhance the tuning range are then proposed Finally, the 7

46 easured data which that validates the feasibility of these tuning enhanceent techniques to increase the tuning range of high frequency icroechanical oscillators, is provided Chapter 5 covers the application of frequency tuning for icroechanical oscillators It starts by providing a brief explanation of the fundaentals of on-chip teperature copensation for icroechanical oscillators and provides exaples of prior work on teperature-copensated capacitive and piezoelectric icroechanical oscillators After that, it goes into ore details of each block such as teperature sensors, scalars, aplifiers, analog function generators and biasing circuits The application of this technique to deliver electronically teperature-copensated high-frequency icroechanical oscillators is deonstrated by providing the easureent data for several oscillators The last portion deals with the ajor sources of error and liitations in each block, and identifies approaches that help iprove the absolute accuracy of the teperature copensation block The phase-noise of both capacitive and piezoelectric icroechanical oscillators are covered in Chapter 6 This chapter starts by providing an overview of the linear tieinvariant (LTI) theory of phase-noise in oscillators with high-q tank Then, this theory is applied to a lateral icroechanical resonator The effect of electronic theral and 1/f noise on the phase-noise considered Unlike prior published work, the effect of nd order parasitics such as resonator and aplifier shunt parasitic ipedances on the phase-noise perforance, esp close-to-carrier is studied in detail to arrive at a closed-for expression for overall phase-noise perforance of the oscillator In addition, the effect of resonator nonlinearity and other environental parasitics such as teperature fluctuation and noise 8

47 fro teperature copensation circuitry are discussed Finally, easured phase-noise data fro different icroechanical oscillators is used to support the theory The phasenoise odel is fitted to the data and any discrepancies are explained Chapter 7 lists the contributions of this work and provides a glipse into the research work that is ahead for integrated high-frequency icroechanical oscillators to satisfy requireents for new deanding applications 9

48 CHAPTER : High Frequency Microechanical Oscillator Design 1 Introduction As entioned earlier, despite significant efforts toward integration of low-phase-noise reference oscillators on the sae chip with odern radio transceivers, ost systes continue to rely on large off-chip quartz crystal oscillators as the only viable solution for high-perforance frequency synthesizers However, the perforance degradation caused by interconnects parasitic (due to two-chip syste) and large up-conversion ratio (due to the inherent frequency liitation of the quartz-crystal reference oscillator), as well as the desire to reduce the cost and size of the final product have otivated the designers to search for an integrated alternative to off-chip quartz crystal oscillators Although iniaturized low phase-noise integrated icroechanical oscillators have been considered a potential candidate in crystal-less transceivers for several years, their low oscillation frequency has ade the inferior to quartz crystals [] Recent progress in icroachining technology has accelerated the eergence of high-q low-loss integrated icroechanical resonators as a feasible alternative to quartz crystals for counication transceiver applications [7] Coponents used in a icroechanical oscillator will be studied in this chapter These coponents include different types of resonators and electronic circuits that are used through this work For each type of resonator, the principle of operation is briefly discussed and the procedure for luped electrical odeling is explained The required electronic circuits for icroechanical reference oscillators including the sustaining aplifier, teperature copensation circuitry and autoatic level control, are identified 30

49 and briefly explained Finally, exaples of high frequency icroechanical oscillators are provided Microechanical Reference Oscillator Block Diagra A general block diagra of high frequency icroechanical reference oscillator is shown in Fig 1 The block diagra consists of a sustaining aplifier, frequency tuning network, teperature sensing and copensation unit, on-chip buffer, and high frequency icroechanical resonator Frequency tuning Teperature sensor and copensation Copensation Circuitry Tunable TIA Ap1 Ap On-chip Buffer Core Aplifier Voltage Aplifiers 50Ω Buffer Resonator Fig 1 General block diagra of high frequency icroechanical oscillator [1] The sustaining aplifier is coprised of a tunable TIA and additional gain/phase-shift stages The sustaining aplifier is ainly used to copensate for the loss of the icroechanical resonator and satisfy the Barkhausen s gain and phase criteria for oscillation [15]: A CL ( jω0 ) = 1, (1) A CL ( jω0 ) = 0, () 31

50 where A CL is the closed-loop gain and ω 0 is the oscillation frequency The frequency of oscillation in deterined by the resonance frequency of the icroechanical resonator: 1 ω 0 =, (3) L C where L and C are the equivalent inductance and capacitance in the resonator odel The frequency tuning network is used to vary the frequency of oscillation Teperature sensing and copensation unit provides a teperature dependent control signal that can be used to copensate for the frequency drift of the oscillator with teperature High frequency icroechanical resonator acts as the frequency selective tank in the oscillator and sets the oscillation frequency The on-chip buffer is used to drive the load that can be another block in the PLL or the input of easureent equipent 3 Series-Resonant Microechanical Resonator Series-resonant icroechanical resonators are iniaturized echanical resonant transducers that are actuated to resonate near their natural echanical resonance frequency This natural resonant frequency depends on the aterial and shape of the resonator Microechanical resonators usually consist of two parts: the transducer and echanical resonant body The transducer acts to convert the electrical energy to echanical energy and vice versa; for ost resonators the transducer interacts with sense and drive electrodes The sense drive is usually at the input terinal of the resonator; it senses the electrical signal that is then converted to the echanical doain At the output terinal, the signal is converted back to electrical doain; then, the output load is driven by this electrical signal 3

51 The frequency response of a icroechanical resonator operating close to its resonance frequency resebles that of a second-order linear tie-invariant (LTI) syste The coon electrical odel used to describe a series-resonant icroechanical resonator consists of a series RLC network (Fig ) [56] When both input and output terinals (electrodes) are in-phase and syetric, the transforers can be eliinated C f L C R C p C p Fig Luped RLC odel for a series-resonant icroechanical resonator For a single degree of freedo (SDOF) echanical syste such as icroechanical resonator, the resonance frequency is: ω = πf = K M, (4) 1 eff eff where M eff and K eff are effective ass and effective stiffness, respectively For a hoogeneous and continuous syste, M eff and K eff can be expressed as: M eff u ( x, y, z) dv V = ρ, (5) u c K eff = ω M eff, (6) where ρ is the density, u(x,y,z) is the ode shape and u c is the odal displaceent at the point (x c,y c,z c ) Then, the paraeters for the siplified series RLC electrical odel of the icroechanical resonator can be derived as: 33

52 Keff Keff R = η, L, C ωqη = η = K, (7) eff where η is the electroechanical coupling coefficient, and R, L, and C are referred to as the otional resistance, otional inductance, and otional capacitance of the icroechanical resonator, respectively At resonance, the effect of otional inductance and capacitance cancel out, leaving only the otional resistance that represents the iniu loss of the resonator across the frequency range Other paraeters in the odel are C p that is the shunt parasitic capacitance at the input/output terinal of the resonator, and C f that represents the feed-through path between the input and output node and is typically sall for lateral icroechanical resonators (<50fF) The shunt parasitic capacitance includes both the capacitance fro overlap between input/output electrodes and the reference electrode, and the capacitance fro parasitic pads The shunt parasitic capacitance could be as large as 4pF for soe lateral icroechanical resonators 31 Capacitive Microechanical Resonator The principle operation echanis for this type of icroechanical resonators is capacitive transduction Capacitive transduction creates an electrical force that will be used to excite a particular resonance ode of the icroechanical structure To increase this force, a very narrow gap is fored between the electrodes and the body of the resonator A polarization voltage is applied to the body of the resonator to avoid frequency doubling at the drive force and to create a sufficiently-large electric field for excitation The aterial used in the fabrication of capacitive icroechanical resonators 34

53 are chosen such that the acoustic energy loss is iniized For this reason, low-acoustic loss aterials such as single-crystal silicon or nanocrystalline diaond are coonly used in cobination with poly-silicon or poly-silicon geraniu (poly-diaond) The capacitive icroechanical resonators usually exhibit very large Q (>50,000) [1] that is coparable to that of quartz crystals [57] Although capacitive resonators exhibit very large Q, they suffer fro large otional resistance The otional resistance in these resonators is priarily liited by the polarization voltage that can be safely applied to the and the technology liit for the gap size The otional resistance is inversely proportional to the capacitive gap size to the fourth power [56] However, by optiizing the design and perfecting the fabrication procedure, low-loss high-frequency high-q capacitive icroechanical resonators are within reach Capacitive SiBARs are prie exaples of optiized design and are the priary choice of icroechanical resonators that are used in high frequency capacitive icroechanical oscillators throughout this work Fig 3 shows an exaple of 103MHz high-q (Q~9,000) capacitive SiBAR that is used in [6] For a capacitive SiBAR operating in its fundaental width-extensional ode, the displaceent of the resonator body toward the electrodes on its two sides is in phase [1]; as such, the direction of input and output currents is fro the electrodes toward the resonator body This shows that the input and output signals are 180º out-of-phase This 180º phase difference fro input to output can be odeled by an ideal inverting transforer (Fig 4) The resonator-specific odel paraeters such as R, L, and C 35

54 can be obtained by fitting the RLC odel to the easured frequency response for the resonator Feedthrough capacitance, C f, can be approxiated by considering the level of isolation between input and output of the resonator f ~ 103MHz Q ax ~ 9,000 R ~ 50kΩ (@ V P =5V) R ~ 36kΩ (@ V P =18V) Fig 3 The response and SEM of a capacitive icroechanical resonator [6] Fig 4 Luped RLC equivalent odel for capacitive SiBAR 36

55 3 Piezoelectric Microechanical Resonator Piezoelectric icroechanical resonators take advantage of electroechanical coupling caused by piezoelectric transduction in certain aterials to excite the resonance ode of the structure As entioned in previous chapter, ost piezoelectric resonators are either categorized as bulk acoustic wave (BAW) [8] or surface acoustic wave (SAW) [9] The electroechanical coupling of piezoelectric transduction is uch larger than capacitive transduction; hence, when operating at the sae frequency, the piezoelectriclytransduced icroechanical resonators exhibit significantly lower loss than their capacitive counterpart This is particularly iportant for high frequency icroechanical oscillators where the loss of the resonator directly affects the power consuption and phase-noise perforance Lateral piezoelectric resonators are typically constructed using a stack of ultiple layers of aterials that have different acoustic properties; in fact, soe (such as etals) exhibit relatively high acoustic loss Therefore, the reported Q fro piezoelectric resonators is typically lower than those reported fro capacitive resonators The loss of acoustic energy at the interface of aterials further reduces the Q of piezoelectric resonators Despite this shortcoing, piezoelectric resonators usually outperfor capacitive resonators in high frequency (>300MHz) oscillator applications due to their low otional resistance [7] This study focuses on the application of high-frequency TPOS resonators to enable high frequency icroechanical oscillators in UHF range Fig 5 shows an exaple of 496MHz high-q (Q~3,800) TPOS resonator that is used to deliver a low phase-noise icroechanical oscillator in [7] 37

56 Siilar to capacitive SiBAR, the displaceent of the body of a TPOS resonator operating in its fundaental width-extensional ode toward the electrodes on its two sides is in phase and hence, the direction of input and output currents is fro the electrodes toward the resonator body However, for operation in higher-order odes the displaceent on two sides is opposite, so is the direction of input and output currents originating fro electrodes As such, the input and output signals are in-phase This reduces the electrical odel of a syetric resonator to a siple RLC with parasitic (Fig 6) f ~ 496MHz Q (loaded with 50Ω) ~ 3,00 Q unloaded ~ 3,800 R ~ 600Ω Fig 5 Response and SEM of a 496MHz piezoelectric MEMS resonator [7] 38

57 Fig 6 Luped RLC equivalent odel for high-order TPOS resonator 4 Sustaining Aplifier for Microechanical Oscillators The sustaining aplifier is the ain circuit block that provides the required gain and phase-shift to sustain the oscillation There are usually two approaches to copensate for the loss of the icroechanical resonator in the oscillator loop: negative ipedance generation and positive feedback loop In the negative ipedance generation approach, the loss of the icroechanical resonator that is usually odeled by its otional resistance is cancelled through adding a negative resistance of equal size in parallel to the icroechanical resonator This is because at resonance, the otional inductance, L, and otional capacitance, C, cancel out, leaving the otional resistance, R, which can be canceled by a negative resistance equal to -R that is generated by the negative resistance circuit (Fig 7) 39

58 Fig 7 Block diagra of the negative-resistance based icroechanical oscillator There are quite a few topologies that can generate the required negative resistance and can be categorized into one-port and two-port negative resistance generators One-port negative resistance generators are fairly siple and in soe cases, can be built using a single transistor Prie exaples of this topology are Colpitts and Pierce oscillators The latter is very popular in crystal oscillators and icroechanical oscillators that use lowloss resonators Fig 8 deonstrates the concept of negative resistance for crystal oscillator applications [58] For ost cases, the generated negative resistance can be related to the g of the transistor 40

59 Fig 8 Negative resistance odel of a crystal oscillator [58] Two-port negative resistance generators are slightly ore coplicated but they offer an advantage over one-port negative resistance generators; they can be ade to operate differentially and therefore, are inherently ore syetric However, this syetry coes at a cost of ore noise and higher power consuption The cross-coupled topology is an exaple of pseudo-differential negative resistance generation topology that is widely used for high-frequency FBAR oscillators (Fig 9) Addition of coonode feedback to this topology can turn it into a fully-differential oscillator with outstanding phase-noise and haronic rejection perforance Although negative resistance-based oscillator topologies are inherently low power and hence, see ideal for high frequency applications, the negative resistance that is generated in high frequency oscillators is relatively sall This is ainly due to the fact that the value of negative capacitance for ajority of approaches is proportional to 1/g of the active devices As the frequency of operation increases, so does the required 41

60 transition frequency (f T ) of the transistors which in turn, forces the designer to increase the g of the transistor in the face of constant parasitic capacitance Larger g values translate to saller negative resistance values which liits the application of negative resistance-based oscillation topologies for icroechanical resonators with high loss For exaple, in frequencies above 1GHz, the value of negative resistance that is generated by cross-coupled topology is barely about -100Ω This is about an order of agnitude saller than the required negative resistance for gigahertz lateral icroechanical oscillators On the other hand, the positive feedback approach can accoodate both low loss and high loss icroechanical resonators Fig 9 Exaple of cross-coupled topology used in 1GHz FBAR oscillator [36] 4

61 In positive feedback approach, a sustaining aplifier is used with the resonator in a positive feedback loop to sustain the oscillation For series-resonant icroechanical resonators, the output of the resonator is an AC current, therefore, the sustaining aplifier needs to siultaneously boost the input current and convert it to voltage at the output This is done by a high-gain TIA An ideal TIA is a broadband aplifier with infinitely-sall input and output ipedances TIAs are categorized into two general groups: open-loop and closed-loop (feedback) TIAs Open-loop TIAs are based on a current aplifier in which the output current is passed through a resistance load to convert it to voltage Closed-loop systes are usually built around a voltage aplifier with shunt-shunt feedback The shunt-shunt feedback helps the output voltage track the input voltage by the ratio of the feedback resistance In addition, it iniizes the Q-loading in the oscillator [8] This resistance sets the transipedance gain of the TIA and can be ade tunable for greater flexibility In any cases, the power consuption and GBW requireents call for ulti-stage TIA design These TIA topologies usually take advantage of one or ore voltage gain stages that provide additional gain and phase-shift that is required to satisfy Barkhausen s criteria for oscillation (Fig 10) For high frequency applications, extree care in the design of additional stages are necessary as these stage will appear as loading to the first stage and ay liit the overall BW of the TIA 43

62 C f R C p C p R F A V Fig 10 Block diagra of the oscillator based on positive feedback loop with TIA An exaple of a low-power 018μ CMOS TIA that is designed for high frequency capacitive icroechanical oscillator applications in shown in Fig 11 The first stage is a coon-source aplifier with tunable shunt-shunt feedback This stage acts as the TIA The second stage is also a coon source with shunt-shunt resistive feedback This stage acts as a low-power broadband voltage aplifier that provides additional gain The shunt-shunt feedback in the second stage enhances the BW of the second stage in presence of large output load capacitance The TIA consues A fro 18V supply and achieves transipedance gain > 80dBΩ with BW greater than 150MHz when loaded with 15F input and output capacitance [19] (Fig 1) The gain can be tuned down ore than 0dB This TIA is interfaced with a 145MHz capacitive SiBAR that has a Q ax ~74,000 The resulting phase-noise is better than -111dBc/Hz at 1kHz offset and eets the GSM phase-noise requireent 44

63 V DD Bias Voltage Vout Iin VTune RF Fig 11 Scheatic of the two-stage 018μ CMOS TIA [19] Gain [db-oh] Min gain Noinal gain (BW>150MHz) Max gain (w/o overshoot) Frequency [Hz] 5 3 x 10 8 Fig 1 Measured transipedance gain of the two-stage 018μ CMOS TIA [19] 45

64 5 Autoatic Level Control Due to sall power handling capability of soe icroechanical resonators, an autoatic level control (ALC) ay be necessary to control the aplitude of the oscillation and prevent the icroechanical resonator to be derived into the nonlinear region Nonlinearity of icroechanical resonators is the result of any factors including the resonator geoetry, aterial, and transduction echanis The aplitude control is also essential in iproving the close-to-carrier phase-noise perforance of the oscillator This is especially iportant for high frequency capacitive icroechanical oscillators where the requireent for sall otional resistance calls for very narrow gaps that have a great ipact on the linearity perforance of the icroechanical resonator Fig 13 shows a general block diagra of an ALC circuit that is used for icroechanical oscillators based on feedback TIAs [] Aplitude control is achieved by detecting the aplitude of the output signal with a high-speed peak detector and coparing the aplitude to a pre-defined resonator-specific threshold value V REF The value of V REF is set by the nonlinearity liit of the icroechanical resonator The resulting error signal is applied to the TIA to adjust the transipedance gain with the help of a tunable MOS resistor Varying the gain of the TIA affects the large-signal response of the oscillator which in turn, liits its output swing that is closely related to the aplitude of oscillation For better accuracy, the ALC can be digitally prograed with the help of a high resolution digital to analog converter (DAC) Main liiting factors in this topology are offset of the coparator, speed of the coparator, and the accuracy of peak detector 46

65 Fig 13 General block diagra of ALC circuit [] Recent developent in the design and technology of icroechanical resonators has increased their power handling capability that deterines the threshold of nonlinearity This is ore pronounced in high frequency piezoelectric icroechanical resonators where the transduction area and resonating ass can be increased independently fro the resonance frequency This iproved nonlinearity of the icroechanical resonator cobined with constantly-shrinking supply voltage in advanced IC processes that severely liits the output swing has shifted the focus to sustaining aplifier as the ain block that sets the aplitude of oscillation Moreover, the ALC has negative effect on the phase-noise, especially close-to-carrier perforance, of the icroechanical oscillator As such, ost high frequency (>300MHz) piezoelectric icroechanical oscillators do not use an ALC 6 Teperature Copensation Circuit Teperature copensation circuitry is an essential part of a icroechanical reference oscillator Teperature copensation circuit consists of two blocks: teperature sensing and control unit, and analog function generator The teperature sensing unit usually uses a teperature-insensitive block such as a bandgap reference, and a block whose 47

66 output varies linearly with teperature such as a proportional-to-absolute-teperature (PTAT) reference The output of bandgap and PTAT references will be copared and scaled appropriately before being applied to an analog function generator The analog function generator is designed to iprove the perforance of the teperature copensation block by trying to odel the frequency vs teperature behavior of the oscillator ore accurately as this relationship is often ties, nonlinear (Fig 14) Fig 14 General block diagra of the teperature copensation circuit 7 Microechanical Oscillator Exaples Although both capacitive SiBAR and TPOS resonators are being used throughout this work, the ajor portion of this research study is dedicated to TPOS resonators as capacitive SiBARs have not yet been optiized (both in ters of loss and Q) to offer copetitive solution for coercial frequency reference oscillators in UHF range Still, efforts have been ade throughout this study to increase the resonance frequency of the capacitive SiBAR with inial effect on its Q and loss In this section, exaples of capacitive SiBAR and high frequency TPOS icroechanical oscillators are provided 71 Capacitive SiBAR Oscillator As entioned earlier, High-Q capacitive icroechanical oscillators are viable tiing solutions for odern counication systes as they offer superior close-to-carrier 48

67 phase-noise in a sall for factor, and potential for integration with integrated circuits [6], [8] This is achieved at the expense of higher power consuption and worse phasenoise floor, both of which are the result of high otional resistance of the capacitive transducer Teperature-copensated capacitive SiBAR oscillators have been successfully deonstrated in the past however, increasing the oscillation frequency has continued to be a challenge The otional resistance of the capacitive icroechanical resonator increases rapidly as the frequency scales to the upper VHF [1], hence, aking the resonator unsuitable for high frequency low power tiing applications The otional ipedance can be iniized by increasing the transduction area or reducing the capacitive gap, both of which have practical liitations [1] Siulation of the frequency response of a SiBAR in ANSYS reveals that there is an optiu thickness for which the otional ipedance can be iniized The otional ipedance is proportional to the fourth power of the gap, and inversely proportional to the square of V p, and the transduction area A [18]: R 4 g, (8) QV A p Lowering the otional ipedance of a device with given diensions requires that either the gap size is reduced or V p is increased Both of these ethods are unattractive due to the fabrication issues and inherent incopatibility of ost IC technologies with high voltages Therefore, increasing the transduction area (ainly through increasing the thickness of the resonator or by arraying resonators) or using a aterial with high 49

68 dielectric constant in the gap [15] appears to be the path toward lower otional ipedance resonators The latter, however, ay negatively affect the Q and significantly increases the static capacitance of the resonator; thereby, aking it unsuitable for lowpower low phase-noise oscillators The value of the silicon thickness that iniizes the insertion loss (while keeping the thickness less than 30µ for ease of anufacturing) was deterined fro ANSYS siulations of a odel of the coplete device, including electroechanical transduction in the capacitive gaps Different types of eleent odels available in ANSYS were used for the various coponents of the resonator A nuber of resistors and capacitors were also added to odel the test setup used for resonator testing (Fig 15) This odel akes it possible to siulate the frequency response of a SiBARs of arbitrary diensions R S C d C s SiBAR + v in C pd C ps v out R L Fig 15 Circuit equivalent of the ANSYS odel of the SiBAR Each siulation consists of a static analysis, which is needed to account for the effect of the DC polarization voltage, followed by a haronic analysis over a specified frequency range This particular set of analyses, cobined with the inclusion of the electrostatic gap in odel, provides ore coprehensive and ore accurate inforation about the behavior of the coplete device than is obtainable fro a siple odal analysis In particular, the siulation results include the values of all node voltages, which akes it 50

69 possible to generate plots of the voltage gain A v = v out /v in over the specified range of frequencies Several paraeters indicative of the resonator perforance can then be obtained fro those plots, including the agnitude of the resonant peak, which is related to the insertion loss of the device Siulations of a set of SiBARs of fixed length (70μ) and width (7μ) were used to generate the plot in Fig 16, which shows the values of A v at resonance as a function of device thickness The optial range of thickness values that iniizes the insertion loss in the device is clearly identifiable in the plot (15-0µ) A v (db) L = 70 μ W = 7 μ 33 gap = 80 n Vp = 14 V thickness (μ) Fig 16 Value of A v at resonance vs device thickness To validate the optiu thickness obtained fro ANSYS siulation, a high-q 70μ 7μ SiBAR was fabricated using the HARPSS process flow [1] on a p-type 51

70 SOI ultra-low resistivity silicon (0005 Ωc) with 15μ thick device layer, as predicted by ANSYS siulation The easured frequency response of the fabricated SiBAR shows axiu Q ~ 74,000 at 145MHz with V p =V (Fig 17) The resulting fq product, ~ , is coparable to that of quartz resonators (~ ) After increasing V p to 14V the otional ipedance is reduced to 4kΩ (Fig 18), which akes the device suitable for low-power oscillators The drop in Q at higher V p is attributed to a parasitic resistance, R load, that appears in series with R in the equivalent electrical odel: Q res R + R + R Q R easured load s, (9) where Q res is the intrinsic echanical Q of the resonator, R s is the resistance of silicon bar, R load is the parasitic series resistance that loads the Q, and R is the otional resistance of the resonator that becoes saller with larger V p For this resonator, R load is extracted to be ~107kΩ The sustaining aplifier is a two-stage feedback TIA (Fig 11) Due to the large otional ipedance and input/output parasitic capacitance of the resonator, unlike the TIAs used for low loss high frequency piezoelectric resonators, the TIA gain and 3dB bandwidth have to increase siultaneously To increase the gain of the TIA beyond the required 80dBΩ without significant increase in power consuption, the signal is passed through additional voltage aplifier with fixed gain Local shunt-shunt feedback is also used in this stage to iprove the 3dB-bandwidth and linearity of the aplifier The result is a two-stage aplifier in which the first stage uses coon-source topology with tunable shunt-shunt feedback and acts as the TIA The second stage provides additional voltage gain The gain tuning is realized through an externally-controlled NMOS resistor 5

71 f = 145MHz V p = V Q ax = 74,000 R =79kΩ Fig 17 Measured frequency response of the 145MHz SiBAR (highest Q) f = 145MHz V p = 14V Q op = 51,000 R =4kΩ R load =107kΩ Fig 18 Measured frequency response of the 145MHz SiBAR at V p =14V The sustaining circuitry is fabricated in a 018µ 1P6M CMOS process and easures 600µ 300µ, of which only 70µ 40µ is occupied by the sustaining aplifier (Fig 19) An off-chip 50Ω buffer is used to interface with easureent equipents The 53

72 TIA provides ore than 80dBΩ at 150MHz with 15pF input and output capacitance (equivalent parasitic capacitance of a SiBAR) while consuing A fro 18V supply The gain can be tuned by ore than 0dB fro 75dBΩ to 95dBΩ (Fig 1) before the appearance of peaking in the frequency response At highest gain configuration (95 dbω), the BW is just under 100MHz with the sae loading The resonator and IC are interfaced through wirebond 70µ 40µ Fig 19 Micrograph of CMOS TIA Magnified view shows the active area The oscillator phase-noise is easured in vacuu using an Agilent E5500 phase-noise analyzer syste The easured phase-noise is -111dBc/Hz at 1kHz offset fro the carrier and extends below -133dBc/Hz at far-fro-carrier (Fig 0) The oscillation power is -9dB This is within the resonator linear operating range Close-to-carrier phase-noise perforance of this oscillator eets the GSM phase-noise specification To the authors knowledge, this is the highest frequency icroechanical oscillator reported to-date using a capacitive resonator 54

73 -111dBc/Hz Fig 0 Measured spectru and phase-noise of the 145MHz oscillator 7 High Frequency TPOS Oscillator As discussed earlier, currently, ost reference oscillators are based on quartz crystals Although quartz oscillators exhibit superior stability and phase-noise perforance, their frequency liitation (<00MHz) reduces the perforance of ulti-ode RF transceivers because of the increase in the up-conversion ratio for the synthesizers Prior work on high frequency low phase-noise silicon icroechanical reference oscillators are based on capacitive MEMS resonators with native frequencies in the VHF range [6], [8] The otional ipedance associated with high-frequency (>100MHz) capacitive resonators is usually large (>10kΩ) In addition, capacitive resonator need to 55

74 be operated in vacuu and require a DC polarization voltage that is typically beyond what is available in standard IC processes (>5V) This coplicates the realization of lowpower low-phase-noise UHF oscillators Laterally-excited TPoS icroechanical resonators, on the other hand, offer an alternative solution as they exhibit significantly lower otional ipedances (<1kΩ) at UHF range [0] In addition, unlike thicknessode piezoelectric technology (ie, FBAR), ultiple frequency resonators can be integrated on the sae substrate In this section, a 496MHz reference oscillator based on an AlN-on-Si TPoS resonator is deonstrated [7] By including silicon in the resonant structure, ost of the acoustic energy is stored in a low-acoustic-loss aterial (single crystal silicon) This boosts the quality factor of the resonator, a key perforance paraeter for oscillator applications, when copared to a fully piezoelectric resonator (eg, FBAR) As shown in Fig 1, the resonator structure resebles a block designed to operate in high order width-extensional resonance ode The easured otional ipedance of the device is ~600Ω and the unloaded Q is ~3800 easured in air The fabrication process flow of this type of TPoS resonators is low-teperature and post-cmos-copatible, adding ore value to this approach The block diagra of the reference oscillator is shown in Fig 1 The frequency of oscillation is deterined by either a 496MHz or a 08MHz high-q TPOS resonator The sustaining aplifier consists of two parts: TIA with tunable gain and two subsequent 56

75 voltage aplifiers The gain tuning is achieved by a NMOS resistor The third stage helps relax gain constrains on the previous gain stage; thereby, reducing the power consuption and iproving linearity Due to large power-handling of these resonators (>10dB), autoatic level control (ALC) is not necessary Fig 1 Block diagra of the high frequency TPOS oscillator [7] The resonators used in this oscillator are 9 th -order TPoS lateral bulk acoustic resonator (LBAR) that are fabricated on a SOI substrate with 10μ thick device layer The finger pitch size is 10µ for 496MHz device and 0 µ for 08MHz device The frequency is reduced ore than 0/10 ratio due to the increase in finger width The frequency response of the device is easured in air using an Agilent E8364B VNA with GSG probes (Fig ) Since the terination load of the network analyzer (50Ω) is coparable with the otional ipedance of both device (~80Ω and 600Ω) the Q values 57

76 easured (~,50 and ~3,180) are evidently lower than the unloaded Q of the resonator (~7,400 and ~3,800) f ~ 4966MHz Q L (Loaded with 50Ω) ~3180 Q UL ~3800 R ~ 600Ω f ~ 08MHz Q L (Loaded with 50Ω) ~530 Q UL ~7300 R ~ 80Ω Fig SEM and response of 496MHz and 08MHz AlN-on-Si resonators [7] The sustaining aplifier is a three-stage 018μ CMOS TIA with variable gain at the first stage (Fig 3) The TIA was intended to be a universal design, capable of sustaining oscillation with a broad range of high frequency TPOS resonators having characteristics of: 100MHz < f < 1GHz and 50Ω < R < 1kΩ and shunt parasitic capacitance between 15pF to 3pF To achieve high gain while aintaining the wideband characteristic of the TIA, a lowgain transipedance stage is followed by two wideband voltage gain stages Shunt-shunt feedback is introduced in each voltage gain stage to reduce the ipedance at inter-stage nodes This technique increases the frequency of the poles resulting fro the inter-stage nodes to uch higher than those of the input/output; thus providing wideband characteristic without increasing the power consuption Another advantage of this technique is to eliinate on-chip inductors typically used in high-gain gigabit CMOS TIA circuits to enhance the bandwidth The result is significant reduction in area 58

77 Fig 3 Scheatic of the three-stage CMOS TIA (biasing is not shown) [7] The designed TIA achieves the -3dB bandwidth of ore than 880MHz at axiu gain (7dBΩ) when loaded with pf capacitance load at the input and output node The ain reason to choose coon source over higher gain topologies such as cascode is to increase the voltage swing and enable the circuit to operate fro lower supply (in this case 15V) that further reduces the power consuption The higher output swing results in lower phase-noise floor as the dynaic range of the TIA will be iproved To boost the gain at higher frequencies, capacitive coupling is used in the third stage The high pass response of the third stage significantly attenuates the low frequency noise of 59

78 the aplifier, which is higher in CMOS circuits due to large flicker noise Therefore, the contribution of TIA noise to the overall close-to-carrier phase-noise is reduced The choice of capacitor C F deterines the attenuation For the case of pf, the phase-noise at 1kHz offset is db lower than the oscillator constructed with the sae resonator but using the TIA without capacitive coupling The TIA and biasing circuitry is fabricated in a 018u 1P6M CMOS process Another TIA that does not incorporate capacitive coupling was also fabricated on the sae die for the purpose of perforance coparison An off-chip 50Ω buffer is used to interface with the easureent equipents The TIA was easured to have axiu transipedance gain of ore than 718dBΩ and axiu -3dB bandwidth in excess of 960MHz when loaded with pf at both input and output nodes The TIA -3dB bandwidth when interfaced with standard photodiodes with equivalent capacitance ~500fF will be enhanced to 15GHz The TIA gain could be varied by 8dB (Fig 4) The aplifier and biasing circuitry consued 6A fro 15V supply The die size is 1 of which 450µ 330µ is occupied by the sustaining aplifier (Fig 5) The easured phase-noise of the oscillator in air is 9dBc/Hz at 1kHz offset and below 147dBc/Hz at far-fro-carrier (Fig 6) The easureent was carried out by an Agilent EE5500 phase-noise analyzer The oscillation power was 19dB, well within the resonator linear range The slight degradation in phase-noise perforance around 100kHz offset is due to the internal phase-noise liit (~ 136dBc/Hz) of the Agilent 60

79 E857C Analog Signal Generator that is used in the phase-noise easureent setup The spurs below 1kHz are caused by 60Hz signal and its haronics To deonstrate the effect of Q loading on the phase-noise of the oscillator, a 08MHz AlN-on-Si resonator that exhibits Q UL ~ 7400 and R ~80 Ω was interfaced with the sae TIA The oscillation power was 5dB The easured phase-noise at 1kHz offset was 95dBc/Hz and phase-noise floor 15dBc/Hz While ore than 5dB iproveent to the phase-noise floor can be explained by the lower otional ipedance of the resonator, the less than expected iproveent in close-to-carrier phase-noise can be explained by the fact that in both cases, Q L is roughly the sae Considering R in ~ 100Ω and R out ~ 10Ω, Q L is 300 for this device whereas for the case of 496MHz resonator, Q L is ore than 500 The 3dB difference in phase-noise is due to the fact that the oscillation power for 08MHz is ~3dB higher 61

80 Fig 4 Frequency response of the tunable CMOS TIA [7] 6

81 Test circuits TIA w/o capacitive coupling TIA with capacitive coupling Fig 5 Micrograph of the fabricated die [7] 1/f 3 region f o ~4966 MHz P out ~db 1/f region 1/f region Noise floor Fig 6 Phase-noise and output spectru of 08MHz and 496MHz oscillators [7] 63

82 The phase-noise perforance of the 496MHz AlN-on-Si oscillator, which at the tie of publication was the highest frequency lateral icroechanical oscillator, is scaled and copared to state-of-the-art capacitive icroechanical oscillators in Table 1 Table 1: Perforance coparison of icroechanical oscillators Oscillator Disk [8] SiBAR [6] This Work 61MHz 103MHz 496MHz 1kHz (dbc/hz) kHz (dbc/hz) PN floor (dbc/hz) f (MHz) Resonator Q 48,000 80,000 3,800 Vacuu Yes Yes No DC Voltage Yes Yes No IC Process 035u 018u 018u 8 Conclusion The design of high frequency icroechanical oscillators is explained The icroechanical oscillator consists of sustaining aplifier and icroechanical resonator The high frequency lateral resonators that are used in this work are either capacitive SiBAR or lateral TPOS, both of which can be odeled by a series-rlc luped circuit that incorporates additional shunt and feedthrough capacitance to odel non-idealities of the resonator The sustaining aplifier is usually a tunable TIA that includes a teperature copensation circuit whose output can be applied to the 64

83 frequency tuning network for teperature and process copensation For capacitive resonators with sall power handling capability, an ALC can be used to control the oscillation aplitude for best phase-noise perforance Finally exaples of high frequency capacitive SiBAR and TPOS oscillators that are realized as part of this work are provided 65

84 CHAPTER 3: Transipedance Aplifier Design 31 Introduction Due to the high loss of the icroechanical resonator, high frequency MEMS reference oscillators require sustaining aplifiers with large gain bandwidth (GBW) Seriesresonant icroechanical resonators call for current to voltage conversion that can be perfored in a TIA Series-resonant icroechanical resonators typically exhibit large shunt parasitic capacitance at both terinals that directly appear at the input and output of the TIA This large input/output capacitance load, which is typically a few ties bigger than parasitic capacitance of a typical photo-diode (~00-500fF), severely liits the ability of the designer to eet the BW requireents with a reasonable power budget The design is further coplicated by the requireent for high gain and low power consuption As such, unconventional design ethodology ay be necessary to deliver a low-power highgain TIA that is suitable for series-resonant icroechanical oscillators operating in ulti-gigahertz frequency range This chapter describes the TIA design and trade-offs for high-frequency icroechanical oscillators At the beginning of this chapter, TIA topologies are introduced and their gain, frequency response and noise perforance are copared After that, the TIA design etrics are explained and trade-offs are briefly explained The next section focuses on high perforance techniques, naely gain and bandwidth enhanceent which are critical to iproving the TIA perforance Output buffers with large driving capability are 66

85 discussed as well The high perforance techniques are then utilized to push the liits of the technology for 018μ low-power CMOS TIAs that accopany this chapter as design exaples Finally, different TIA topologies are copared for best perforance 3 TIA Configurations Transipedance aplifier (TIA) is an active circuit eleent whose input and output are AC current and voltage, respectively The transipedance gain is defined as the ratio of output voltage to input current and is usually expressed in dbω For an ideal TIA, both the input and output ipedances are infinitely sall and the 3dB bandwidth (BW) is infinitely large However, in reality, the input and output ipedances are finite and tend to ove away fro pure resistive as the frequency increases For frequencies well below f T, the TIA equivalent luped odel can be approxiated (Fig 31) Fig 31 The equivalent luped odel of the TIA 67

86 There are two general aplifier configurations that are widely used to realize a currentto-voltage converter aplifier (coonly known as TIA) with large GBW These topologies are called open-loop and closed-loop (feedback) configurations 31 Open-Loop TIA Configuration The principle of operation in open-loop TIAs is based on a current aplifier with output resistive load The input current is first aplified by passing through the current aplifier; then, the resulting output current is given to a resistive load to generate an output voltage Fig 3 shows the concept of open-loop TIA configuration R L I out ~A I I in Vout ~A I I in R L I in A I Fig 3 Open-loop TIA concept The ost coon aplifier topologies that are used in open-loop TIA configurations are coon-gate (CG) and coon-base (CB) The inherently-low input resistance of these topologies (~1/g ), akes the ideal for broadband TIA applications In ost cases, the input ipedance of the open-loop TIA can be further reduced and consequently the BW can be iproved by using boosted-g topologies such as regulated-cascade that offers lower input resistance with negligible effect on the gain [59] Open-loop TIAs are generally lower power but higher noise solutions than feedback TIAs [49] 68

87 The high frequency behavior of the open-loop TIA is of extree iportance Assuing that doinant parasitic capacitance loads are at the input and output of the TIA (this is a reasonable assuption due to the large input and output shunt parasitic capacitance of the icroechanical resonator) and neglecting the channel-length odulation effect (λ 0 or r ds ), the frequency response of a CG TIA (Fig 33) can be approxiated by: V DD R L V out M 1 V b1 C out I in C in M V b Fig 33 Siplified scheatic of a CG TIA V I out in ( g + g ) Cin s g 1 + g R ( g 1 + gb 1) RD ( g + g + C s)( R C s + 1) 1 b1 b1 in D out b1 D 1 C s out, (31) where g 1 is the transconductance of M 1 transistor g b1 is transconductance of M 1 due to the body effect that in short-channel regie, could be as high as 04g 1 for iniu channel length devices Equation 31 clearly shows that the transfer function of the TIA 69

88 has two poles The agnitude of each pole is dependent on the transconductances of M 1 transistor, R D, and parasitic input and output load capacitances Considering the fact that the ipedance looking into the source of the M 1 transistor is approxiately 1/(g 1 +g b1 ), the input ipedance of the CG TIA is: R 1 1 in Cin s g 1 + g (3) b1 Neglecting the channel-length odulation effect on M 1, forces the output current to flow through the parallel equivalent of R D and C out ; therefore, the output ipedance of the CG TIA can be approxiated by: R out 1 Cout s R D (33) To realize a low phase-noise icroechanical reference oscillator, it is critical to study the noise behavior of the TIA that is used as sustaining aplifier Three devices contribute to the output noise of the TIA, two NMOS devices, M 1 and M, and the resistors, R D Neglecting the gate-induced noise current of MOS devices, the high frequency noise power is ainly due to the theral noise associated with these three active eleents The equivalent circuit to calculate the input-referred noise current of the TIA is shown in Fig 34 It is worth entioning that due to the very sall BW of icroechanical resonators, spot noise at a particular frequency is a ore relevant perforance etric than the average noise; as such, coputing the total integrated noise in the BW and finding the average noise and noise BW is not necessary At the first step, it is clear fro the equivalent circuit of Fig 34 that the noise of the drain noise current of M directly shows up at the input 70

89 Solving the network for I n,in, the equivalent input-referred current noise power can be derived as: I n, in = I n, M + C ω ( g + g ) 1 in b1 I n, M Cin ω + + ( g 1 + gb 1) ( g + g ) 1 b1 n, R 1 D I, (34) where ω is the angular frequency and I n,m1, I n,m, and I n,rd are the equivalent theral noise current of M 1, M, and R D, respectively The aforeentioned noise analysis states that in addition to the theral noise of the M transistor that directly shows up at the input, the noise of R D is aplified and referred to the input too Therefore, CG TIAs are considered an unsuitable solution for low phase-noise icroechanical oscillators Fig 34 Siplified equivalent circuit for noise calculation in a CG TIA 3 Feedback TIA Configuration The feedback TIA configuration is the ost coon TIA topology used in sustaining aplifiers of lateral icroechanical oscillators due to their low noise and gain vs BW trade-off flexibility [8], [7] This configuration is based on a voltage aplifier with shuntshunt negative feedback between input and output (Fig 35) The role of shunt-shunt feedback is to saple the output voltage and return a proportional current to the input of the TIA; effectively acting as the current-to-voltage converter An iportant property of 71

90 shunt-shunt negative feedback that akes it ore attractive for TIA applications is lowering the input and output resistances of the aplifier by loop-gain and naturally, boosting the BW of the TIA In addition, it helps reduce the equivalent input-referred voltage noise power of the aplifier by the square of the shunt-shunt feedback resistance value The reduction in noise akes this TIA ore attractive for low phase-noise icroechanical oscillators R F I in V out ~I in R F A I Fig 35 Closed-loop TIA concept The ost coon aplifier topologies that are used in feedback TIA configurations are coon-source (CS) and coon-eitter (CE) Many feedback TIAs are constructed with a single-stage CS aplifier with active load, however, due to the need for larger drive capability and lower output resistance, a source-follower coon-drain (CD) stage can be added to the output [49] Another approach is to use ultiple stages each with a shunt-shunt feedback to increase the BW [7] The frequency response of the feedback TIA shows ore flexibility than its open-loop counterpart It allows for easier trade-off between gain and BW, thereby aking the task 7

91 of designing a TIA with gain tuning that can be used in icroechanical oscillator applications significantly easier For a first-order feedback TIA, ie the core aplifier is a first-order inverting ideal aplifier with very large input ipedance and infinitelysall output ipedance, with input and output shunt capacitance (Fig 36), the frequency response can be expressed as: R F C in C out -A V I in Fig 36 Diagra of the feedback TIA with input and output capacitance load v i out in Av RF =, (35) A RFC v + 1 in 1+ s A + 1 v where A v is the open-circuit voltage gain of the core aplifier The BW of the TIA is liited by the input capacitance and can be traded of by id-band transipedance gain, R F ; due to the ideal nature of the voltage aplifier, ie the output ipedance of the TIA is near zero, the current passing through R F alost copletely flows into the aplifier, leaving only a negligible portion to flow through C out ; as such, the output capacitance will 73

92 not have a tangible effect on the frequency response of the TIA and hence, can be safely ignored in the AC analysis Applying the Miller theore, the input ipedance of the TIA can be approxiated by: R in 1 Cin s RF 1+ A v (36) To study the noise behavior of the first-order feedback TIA, it is iperative to use twoport noise theory to find the equivalent input-referred current and voltages noise sources of the aplifier Due to the infinitely-large input ipedance of an ideal aplifier, the effect of the equivalent input-referred current noise on the noise perforance of the TIA is negligible and hence, it can be ignored in the analysis Fig 37 shows the scheatic of the TIA with noise of the core aplifier and feedback resistor For very aplifiers with very large open-loop voltage gain, ie A v >>1, the equivalent input-referred current noise spectru of the TIA can be approxiated by: V n, R F R F C in C out V n,av -A V I n,in Fig 37 Scheatic of the feedback TIA showing the resistor and aplifier noise 74

93 I n, in V = ( R C ω 1 ) n, R + F F in + RF V n, Av, (37) where V n,av is the equivalent input-referred noise voltage of the core aplifier and V n,rf is the equivalent noise voltage of the shunt-shunt feedback resistor, R F The noise expression indicates that at sufficiently-low frequencies, the equivalent input-referred voltage noise of the core aplifier is reduced by a factor equal to R F before showing up at the input of the TIA This iportant property of feedback TIAs akes the potentially suitable for low phase-noise icroechanical oscillators where high loss of the high frequency resonator requires a large shunt-shunt feedback resistor which, in turn, helps further reduce the noise of the TIA The practical ipleentation of a feedback TIA in standard IC processes could be a challenge Although the large ipedance looking into the gate of a MOS transistor is considered a reasonably-good eulation of infinitely-large input ipedance of an ideal aplifier ipleented in CMOS technology, the finite output ipedance of a CMOS aplifier cobined with the output capacitances liits the BW of the TIA The resulting TIA can no longer be considered a 1 st order syste (Fig 38) Fig 38 Siplified scheatic of the feedback TIA with finite output ipedance 75

94 The frequency response of the TIA can be obtained by solving the equivalent circuit of Fig 38 for v out : v i out in RF ( Rout Av RF ) ( R R C s + R + R )( R C s + 1) ( R A R ) =, (38) F out out F out F in out v F where A v is the open-loop low-frequency voltage gain and R out is the output ipedance of the core aplifier The equation (38) clearly shows that the feedback TIA is now a second order syste The location of the poles is heavily dependent on the feedback resistance, R F, as well as the input and output capacitance The typical ipleentation of a single-stage CMOS feedback TIA is an inverter with shunt-shunt feedback (Fig 39) A tunable MOS resistor is used to introduce the gain tuning capability in the TIA Fig 39 Scheatic of single-stage inverter-based tunable feedback TIA 76

95 33 TIA Perforance Metrics for Microechanical Oscillator Applications High frequency TIAs used for icroechanical oscillator applications differ fro their conventional counterparts that are used in optoelectronics applications by their gain, noise, and BW requireents Other factors including the power consuption and linearity of the TIA ay also have significant ipact on the perforance of the icroechanical oscillator This section briefly introduces different TIA perforance etrics that are iportant for icroechanical oscillator applications 331 Transipedance Gain One of the ain obstacles in aking high frequency icroechanical oscillators is the high loss of the lateral resonator [1] This calls for high gain TIA and akes its iniu required transipedance gain, one of the ain criteria for the design of high frequency icroechanical oscillators High gain coes at a steep price for power consuption and in any cases forces unattractive trade-off with BW [49] Therefore, gain enhanceent techniques ay be explored to boost the gain with inial increase on the power consuption of the TIA 33 3-dB Bandwidth (BW) Perhaps the single ost iportant criterion for the design of TIAs is their iniu BW requireent To eet the phase requireent for oscillation, the TIA BW should extend well beyond the resonance frequency of the icroechanical resonator Large shunt parasitic capacitance appearing in ost lateral icroechanical oscillators renders any of the conventional bandwidth enhanceent techniques inefficient The stringent power budget allocated to the TIA akes this task enorously-difficult for gigahertz lateral 77

96 icroechanical oscillators, as such, special BW and/or cobination of several BW enhanceent techniques ay be considered 333 Noise Low phase-noise icroechanical reference oscillator requires a low noise TIA Miniizing the noise of the TIA that can be categorized into flicker and theral noise sources with a given fixed power consuption requires detailed noise analysis and optiization with CAD tools Optiizing the close-to-carrier phase-noise perforance which is a directly affected by the up-conversion of flicker noise, calls for a CMOS TIA with very-low flicker noise This is arkedly different fro the conventional TIA design approaches where the only noise source to worry about is the theral noise 334 Linearity The linearity of the TIA has an ipact on the integrated jitter of the icroechanical oscillator This effect is ore pronounced on the far-fro-carrier perforance of the oscillator as the oscillation aplitude is ainly liited by the axiu swing of the TIA which is directly related to its dynaic range In addition, the total haronic distortion (THD) of the TIA deterines the power of spurious haronics and sets the overall Spurious-Free Dynaic Range (SFDR) The ever-decreasing supply voltage in advanced CMOS processes puts further strain on the linearity of the TIA and naturally the phase-noise perforance of the icroechanical oscillator This reduced voltage headroo is not particularly troublesoe for optoelectronic applications where the output signals are rail-to-rail square wave, however, it should be copensated for low phasenoise icroechanical reference oscillators through linearity enhanceent techniques This could be in the for of adding transistors that operate in triode region, in parallel 78

97 with the input device to absorb part of the input power when passing a certain threshold The devices that operate in triode region are inherently ore linear 335 Power Consuption The power consuption is another key factor in the design of the TIA The overall power budget of the icroechanical reference oscillator iposes a liit on the axiu power consuption of the sustaining aplifier Stringent gain, BW and linearity requireents of the sustaining aplifier usually do not leave uch roo for flexibility 336 Stability The stability of an aplifier is an iportant factor in deterining its gain, BW and load driving capability [60] Although TIAs are inherently designed for stable operation in gigahertz range, soe of the gain and BW enhanceent techniques negatively affect the stability While feedback TIAs are relatively iune to instability due to the use of negative shunt-shunt feedback, the excessive GBW that is ade available through enhanceent techniques, especially pole-cancellation where addition of zero significantly reduces the phase-argin of the aplifier ay cause instability This ay show as ringing in the transient response or overshoot in the frequency response [49] This instability in the oscillation loop ay cause the oscillation to build up at another frequency that is totally undesirable Therefore, stability of the TIA should be onitored across up to the frequency where the transipedance gain is larger than unity, ie unity gain-bandwidth (UGBW) One approach to reduce the instability caused by excessive gain or large capacitance load is to use a feedthrough capacitance between the input and output of the TIA This feedthrough capacitance controls the overshoot by introducing a zero in the transfer function of the TIA at the expense of saller BW 79

98 34 High Perforance Techniques The need for a high gain TIA that is capable of tolerating large parasitic capacitance is explained in previous section The focus of this section is on ways to iprove the TIA perforance with inial ipact on its noise perforance and power consuption The ain perforance criteria that need iediate attention are gain and BW of the TIA 341 Gain Enhanceent There are several low-power gain enhanceent techniques that can be used in conjunction with other high perforance techniques to deliver a low-power high-gain broadband CMOS TIA suitable for high frequency icroechanical oscillators Most of these techniques are prograable and can be used with both open-loop and feedback TIAs in lateral icroechanical oscillators Auxiliary load: To circuvent the constraint iposed by liited supply voltage in advanced CMOS processes, it is possible to add a PMOS (or NMOS) load in parallel with the drain resistance, R D, of the CS or CG aplifiers (Fig 310) [49] This MOS device is biased such that a portion of the drain current is supplied by this transistor Since the output ipedance of a current source ade of a MOS transistor is significantly higher than the drain resistance used for high frequency TIAs, it is possible to increase the overall transipedance gain Careful balance between the current of the MOS current source and the drain resistance ensures appropriate gain with inial ipact on the BW of the aplifier The ain disadvantages of this gain enhanceent ethod are the increase in the total noise and reduced linearity 80

99 V DD V b3 M 3 R L ki D (1-k)I D V out I D M 1 V b1 C out I in C in M V b Fig 310 Scheatic of CG TIA with auxiliary PMOS load Cascode: A popular approach to increase the gain of an aplifier is cascoding The gain boosting is achieved through increase in the output resistance of the aplifier The cascode device will appear as CG for the input signal, effectively providing additional aplification before the signal is arrived at the output Assuing that the MOS devices are identical and exhibit sufficiently-large drain-source resistance, the gain iproveent can be approxiated by: A v _ boosted A v r ds, (39) where r ds is the drain-source resistance of the MOS device While for open-loop TIAs, the aount gain iproveent is roughly equal to that of a siple voltage aplifier, the gain of the feedback TIA does not iprove uch as it is priarily deterined by the value of the feedback resistor 81

100 With high deand for high frequency low phase-noise reference oscillator based on capacitive icroechanical resonators, the gain iproveent due to the use of a cascode topology ay not be sufficient Increasing the nuber of cascode devices to two, ie triple-cascode topologies is considered an option; but it coes at the expense of further reduction in voltage headroo that can only be tolerated in higher voltage older generation CMOS processes (>3V) A ore practical approach is based on boosted or regulated cascode (RGC) topology where the output resistance can be increased substantially by the gain of the feedback aplifier [60] (Fig 311) The feedback aplifier can be a siple CS with active load Fig 311 Siplified scheatic of aplifier with boosted cascode load Cascade of aplifiers: The ost effective approach to reliably increase the gain of an aplifier in advanced CMOS processes is through the cascade of two or ore lower gain aplifiers The total 8

101 gain will be the product of the gain of aplifiers (Fig 31) For practical reasons, this technique is usually applied to several single-stage aplifiers with low gain and large BW For TIA applications, the first stage is norally a transipedance stage; subsequent stages are voltage aplifiers that boost the signal level in voltage doain Cascaded aplifiers will have the potential for lower instability threshold This is usually due to the extra poles in the transfer function of the aplifier that significantly reduce the phaseargin Since any copensation technique will shrink the BW of the aplifier, the designers usually opt for lower gain stages with feedback that can push the poles to higher frequency and hence, reduce their ipact on the phase of response of the cascaded aplifier Faous approaches include cherry-hooper aplifiers that can offer large GBW with acceptable stability [49] I in A z A v V out Fig 31 Block diagra of the cascaded TIA Current aplification: Since the input to the TIA is current, it ay be worth to consider boosting the signal in the current doain and then pass it to the transipedance stage for current-to-voltage conversion This approach is conceivable only if the current aplifier is sufficiently low power and its BW is coparable (and preferably beyond) with the required BW of the TIA (Fig 313) A siple broadband current aplifier is MOS current irror with 1:N ratio (N>1) This ratio should be carefully chosen to avoid unreasonable increase in the power consuption of the TIA 83

102 I in NI in V out A i A z Fig 313 Block diagra of the TIA w/ current pre-aplification for gain boosting 34 BW Enhanceent To address the BW reduction caused by large parasitic capacitance of high frequency lateral icroechanical resonators, novel low-power BW enhanceent techniques are necessary These techniques fit into one of these two sub-groups: Pushing the transfer function poles to higher frequency: In this category, the BW extension is realized by reducing the ipedance to ground at critical nodes This reduction helps push the poles to higher frequency and naturally, increase the BW of the TIA Prie exaple of this approach is to use shunt-shunt feedback in the TIA Feedback: Study of feedback theory reveals that shunt-shunt feedback have a positively effect the BW of the TIA through reducing the input and output ipedance of the closed-loop feedback syste by a factor close to the loop gain of the syste [60] Considering the large shunt parasitic capacitance of the lateral icroechanical resonator, the feedback pushes the poles to uch higher frequency and hence, greatly iproves the BW of the TIA In any cases, however, the BW liitation due to inter-stage poles is a bigger proble that weights over the design ethodology Here, the first stage acts as the current-to-voltage conversion stage while local shunt-shunt feedback resistor incorporated into other stages lower the equivalent ipedance seen at each critical inter- 84

103 stage node (Fig 314) Of course, adding additional feedback resistors in each stage hapers the goal of aking a high-gain low-power TIA A Cherry-Hooper topology that iniizes the use of feedback resistors can be considered as a coproise [49] For any given two-stage aplifier that uses local shunt-shunt feedback in each stage, the feedback in the first stage can be eliinated in favor of higher gain In this case, the shunt-shunt feedback in each stage lowers the equivalent resistance at both terinals by loop-gain, therefore, in N-stage aplifiers (N>=3), the shunt-shunt feedback in the even stages (, 4, etc) will be redundant (Fig 315) The ain disadvantage of cherry-hooper aplifiers when used in icroechanical oscillator applications is their reduced stability and inial control over the large signal behavior of the aplifier For very-high gain applications (>80dBΩ), it is recoended to keep in the shunt-shunt feedback in each stage for iproved level control and iunity to process and teperature variation Inter-stages nodes Fig 314 Diagra of a ultiple-stage aplifier with local shut-shunt feedback 85

104 Fig 315 Diagra of a ultiple-stage aplifier that shows Cherry-Hooper concept Low-ipedance input and output stages Even after addressing the proble with inter-stage poles, large parasitic capacitance of lateral icroechanical resonators continue to pose serious challenges at the input and output of the TIA While peranent solution to this proble usually lies in the design of resonators with saller shunt parasitic capacitance, using low-ipedance input and output stages can reduce the intensity of the proble Most low-ipedance input stages take advantage of 1/g concept; ie the input ipedance is proportional to the inherently-sall 1/g of the input transistor CG topology is the ost faous exaple in this class Another exaple is a diode-connected current-irror aplifier that is cobined with current-to-voltage conversion stage In soe cases, excessively-large shunt parasitic capacitance requires further reduction in 86

105 input ipedance A known ethod is to use boosted-g that is coonly known as regulated cascode topology (RGC) (Fig 316) V DD R Vbp M3 Vout1 In M1 M R1 Fig 316 Scheatic of an RGC TIA For RGC TIA shown in Fig 316, the input ipedance can be expressed by: R in = 1 g (1 + R g ), (310) 1 1 where g 1, g, and R 1 are transconductance of M 1, M, and load resistance in g - boosting aplifier, respectively As entioned in the previous section, any type of CGbased topology suffers fro high input-referred noise and hence, is not suitable for ultralow phase-noise icroechanical oscillator applications For icroechanical oscillator applications, lowering the output ipedance of the TIA is equally iportant A well-known low-ipedance output stage is coon-drain (CD) stage that is otherwise known as source follower The output ipedance of this stage is 87

106 proportional to 1/g of the transistor Further reduction in output ipedance can be achieved by introducing a feedback in source-follower stage The feedback helps reduce the output ipedance by a factor close to the loop-gain of the closed-loop syste This topology is soeties called super source-follower [61] Poor linearity and liited dynaic range are aong the well-known probles of source-follower topology Introduce zeros in the transfer function to cancel the effect of poles: This approach relies on the pole-zero cancellation concept for BW enhanceent; one or ore zeros are introduced in the transfer function of the TIA The locations of these zeros are precisely deterined to cancel the effect of poles (especially the doinant pole) The faous exaples of this approach are series and shunt inductive peaking Pole cancellation (inductive peaking and capacitive degeneration) The BW iproveent in this ethod can be explained by introducing one or ore lefthand plane zeros in the transfer function whose frequency can be varied accurately to atch those of one or ore poles in the transfer function The concept relies on the added positive phase-shift fro the zero to copensate for the negative phase-shift that is caused by the pole The left-hand zeros do not cause the syste to becoe unstable Although pole cancellation is a very popular approach to increase the BW for very-high frequency TIAs (BW>10GHz), it has been neglected to soe extent for lower frequency TIAs with cut-off frequency in upper UHF range (1GHz<BW<3GHz) This is ainly due to the large size of on-chip onolithic inductors (>10nH) that are required to realize lefthand plane zeros for TIA operating in this range A solution to this proble is to replace passive inductors with active inductors [49], [6] Not only active inductors are saller, 88

107 they are tunable and can be designed to have higher Q The ain drawbacks of active inductors are high noise associated with active coponents and poor linearity There are two ajor approaches to introduce zeros in the transfer function: series peaking and shunt peaking The concept of series peaking is based on putting a circuit eleent in series with the input or output of the TIA to create a zero in the transfer function In rare cases, it is possible to place this eleent between two stages [63] Shunt peaking follows a siilar approach with the exception that this eleent is placed in parallel with the input and/or output of the TIA In ajority of the cases, this extra eleent is an inductor (passive or active) For series-peaking, the inductor is usually placed at the input to resonate out the input pole while for the shunt-peaking, the inductor is intended to resonate out the output pole and hence appear in shunt with the output of the TIA Fig 317 shows the concept of peaking for aplifiers There are other ethods to create a zero in the transfer function of the TIA Placing a feedthrough inductor between the input and output of the TIA is a well-practiced approach for BW enhanceent through creating an additional zero, however, due to practical reasons, this approach is only suitable for wideband aplifiers (BW>10GHz) 89

108 Z L G Series peaking Z I Z O Z I G Z O Z L Shunt peaking Fig 317 Block diagra of TIA showing both series- and shunt-peaking concept Capacitive coupling is another pole-cancellation BW enhanceent ethod that can benefit TIAs interfaced with icroechanical resonators This approach is attractive for high gain lower BW (f<1ghz) icroechanical oscillator applications where the value of inductors that can be potentially used for inductive peaking is significantly larger than what can be practically realized on chip (Fig 318) The output pole resulting fro the equivalent output resistance and the capacitance load can be resonated out by the zero that is generated by source degeneration resistor and the extra capacitance to the reference ground This results in boosting G off the aplifier at higher frequencies 90

109 Fig 318 Scheatic of an aplifier with capacitive coupling for BW enhanceent Other techniques: There are several less popular techniques that can be used to increase the BW of a TIA with liited effectiveness for icroechanical oscillator applications For exaple, f T - doubler topologies [64] are designed to reduce the effective parasitic capacitance of the input transistor (usually C GS ) by 50% This could theoretically increase f T by and potentially increase the BW But this approach is only applicable to TIAs whose BW is liited by parasitic capacitance of the transistor itself However, this approach is clearly not applicable for lateral icroechanical oscillators where the shunt parasitic capacitance of the resonator sets the doinant pole In addition f T -doubler adds to noise 35 Output Buffer Buffers are needed to drive large loads that appear the output of icroechanical oscillators These loads are either in the for of a large equivalent capacitance of 91

110 subsequent blocks in the frequency synthesizer, or for stand-alone oscillators, is in the for of a sall resistance (usually 50Ω input ipedance of the line) cobined with the parasitic inductance and capacitance of package and interconnects This section identifies several CMOS output buffer topologies that are suitable for icroechanical oscillator applications and briefly lays out the design procedure for each topology 351 Inverter Topology One of the faous buffer topologies that are used to drive large capacitance load is the inverter topology The inverter buffer is a relatively low-power topology offers large driving capability with rail-to-rail output in copact size Its very-high output ipedance obviates the need for an ipedance atching network for high-speed signals However, this high-ipedance approach is only acceptable where the parasitic fro interconnects between the inverter and the capacitance load is very sall (Fig 319) This is usually the case when the inverter is used as an output buffer for on-chip icroechanical reference oscillator used in a frequency synthesizer In this case, the frequency synthesizer blocks are laid out very close to each other and therefore, the interconnect parasitics are negligible For off-chip capacitors, this approach has a potential drawback; the reflection caused by isatch between characteristic ipedance of the line and the high output ipedance of the inverter gives rise to severe distortion in the aplitude and phase of the signal which directly shows up in the phase-noise perforance In this case, a siple atched line can do the job 9

111 V DD M Vout Vbuffer CL M1 Fig 319 Scheatic of inverter buffer with capacitive load The axiu speed of the inverter can be approxiated by finding the rise tie and fall tie Then, the iniu acceptable period for a signal can be found by averaging the rise and fall ties This is called the propagation delay of the inverter: t t p p HL LH L DD =, (311) K n p C V ( V V ) DD T,n C V =, (31) K L DD ( V V ) DD T, p t p, avg t p LH + t p HL =, (313) where C L is the load capacitance, V T,n and V T,p are the threshold voltages for N-type and P-type MOS device, and K n and K p are K factors for N-type and P-type devices, respectively 93

112 35 Doubly-Terinated (50Ω-Matched) Topology The best approach to deliver a large signal to output load with iniu loss is to use a load-atched buffer The load ipedance is usually near-50ω with negligible reactive coponent A prie exaple is the 50Ω input ipedance of RF easureent equipents In an unlikely case that the load ipedance and the line characteristic ipedance are different, the buffer output should be atched to line Alternatively, a transission line ipedance transforer can be used to perfor proper atching The siplest CMOS topology for 50Ω buffer is a CS with near 50Ω resistive load The load resistance has to be carefully adjusted to account for the equivalent output resistance if the MOS transistor, which for high-speed high-power buffers, could be coparable to the ipedance of the load For very high frequency applications where parasitic capacitance of the MOS device is not negligible, an on-chip inductor is placed in series with the load resistor to resonate out the unwanted pole (siilar to shunt peaking) This inductor is usually chosen as a passive onolithic inductor for best linearity and noise perforance Fig 30 shows a siplified scheatic of a 50Ω-atched buffer with inductive shunt peaking 94

113 V DD LD RD Vbuffer 50 Vout M1 CL Fig 30 Siplified scheatic of a 50Ω-atched output buffer 353 Open-Drain Topology Open-drain output topology is the ost popular output topology for high-speed optoelectronics syste as it can produce large output swing for far-end when the load is atched to the characteristic ipedance of the line This output buffer topology is ostly used in differential configuration to iniize noise coupling fro nearby high-speed lines and supply lines all of which appear as coonode to the differential buffer and hence, are substantially attenuated Stability of the buffer is iproved as well; however, it still reains an issue especially instability due to feedthrough parasitic ipedances The only outstanding proble with differential operation is the increased power consuption that ay be a concern for on-chip systes 95

114 For near-end applications such as on-chip buffering, the buffer exhibits high output ipedance and akes it unattractive for ost icroechanical oscillator applications As such, the design ethodology for the open-drain buffer is not explained here 36 Design Exaples The knowledge acquired during the previous sections is utilized to design and characterize several low-power high-gain CMOS tunable TIAs This section details the design procedure, easured perforance, and interface data with icroechanical resonators for each of these TIA 361 Regulated Cascode TIA This CMOS TIA is intended for low-power applications, therefore, an open-loop configuration is chosen In this approach, a non-inverting RGC current-to-voltage conversion stage is cascaded with a tunable inverting voltage aplification stage in which the input and output signals are out-of-phase (Fig 31) Outputs fro both inverting and on-inverting stages are taken out to enable operation with both in-phase and out-of-phase icroechanical resonators [65] When operating in non-inverting ode, the second stage is bypassed and the output is taken fro the first stage In inverting ode, the second stage provides additional 180º of phase-shift To drive a resonator with large parasitic shunt capacitance (C P ~pf) into oscillation, both input and output resistance of the sustaining aplifier have to be reduced such that the resulting poles are pushed to frequencies uch higher than the oscillation frequency To achieve this, a g-boosted coon-gate topology, coonly-known as regulated cascade (RGC) is used for the first stage [59] The input resistance of the TIA further 96

115 reduced by the loop gain of the feedback syste; therefore, increasing the g of both transistors helps reduce the input resistance: R in = 1 g (1 + R g ), (314) 1 1 where g 1, g, and R 1 are transconductance of M 1, M, and load resistance in g - boosting aplifier, respectively Fig 31 Scheatic of the two-stage RGC TIA The transipedance gain is ainly set by the gain of the RGC stage The gain of this stage is traded-off with lower output ipedance to avoid creating a high-ipedance node, and consequently a low-frequency pole, that ay liit the BW of the TIA when driving the large shunt parasitic capacitance of the resonator in non-inverting ode 97

116 The second stage is an inverter with tunable shunt-shunt resistive feedback The choice of inverter over CS is ade due to the availability of higher voltage gain with the sae power consuption The overall transipedance gain when both NMOS and PMOS transistors are operating in saturation is: ( R Rtune ) A R, (315) CL, RGC v where R tune and A v are the shunt-shunt feedback resistor and voltage gain of the second stage, respectively The shunt-shunt feedback is used to reduce the output ipedance, hence, aking the second stage capable of driving large shunt-parasitic capacitance without the need for additional buffering The shunt-shunt feedback resistance, R tune, is realized by a NMOS device, M 5, which operates in linear region The voltage gain of the second stage can be approxiated by: ( g + g )( r r R ) Av 1 o1 o, (316) where g 1 and g are transconductance, and r o1 and r o are output resistance of M 1, M, respectively tune Although other high-gain topologies such as cascode can be used in the second stage, their significantly higher output ipedance, severely liits the overall BW of the aplifier Reducing the output ipedance to eet the required BW while aintaining the gain, results in significantly higher power consuption in this stage On the other hand, an inverter benefits fro large equivalent transconductance that is effectively equivalent to the suation of those of the NMOS and PMOS transistors This larger transconductance allows for higher gain with the sae output ipedance; therefore, larger BW can be achieved 98

117 The presence of large capacitance at input node increases the noise of the TIA at higher frequency Neglecting the noise contribution fro nd stage and assuing that the doinant pole fro the RGC stage is at the input, a valid assuption for uch larger input capacitance in coparison with inter-stage parasitic capacitance, the input-referred noise of the TIA is: ( g + g ) 1 1 4kTγ d 0, d 0,3 1 i + + n, in kt + ω C R1 R Rtune g R1 4 in, (317) where C in, is the total capacitance at input terinal of the TIA, g d0 is the drain-source conductance at zero V DS, and γ is the noise coefficient (~/3 in long channel regie) Neglecting the noise contribution fro the nd stage ensures that the input-referred noise does not see the effect of output pole that is due to the large parasitic capacitance of icroechanical resonator For non-inverting operation where the output is directly taken out fro RGC stage, the effect of output pole should be considered too The sustaining circuitry was fabricated in a P3M 05µ CMOS process The IC included four TIAs; two RGC TIAs and two inverter TIAs that will be explained in the next section Each two-stage TIAs has been accopanied by a siilar TIA with sae design paraeters but without the switching network Switching network is used for dual-ode operation The switchless TIAs are used to deterine the effect of switching network on the phase-noise perforance of the oscillator The die area is (Fig 3) Gain and frequency response easureent of the TIAs are perfored by an Agilent E5071C Vector Network Analyzer (VNA) and are followed by oscillation spectru and phase-noise easureent taken when the IC is wirebonded to icroechanical resonators Agilent E4407 spectru analyzer and E5500 phase-noise 99

118 easureent systes are used to onitor the oscillation spectru and easure the phase-noise An off-chip 50Ω buffer is used to drive the 50Ω input of the easureent equipent RGC TIA Inverter TIA RGC TIA w/o switch Inverter TIA w/o switch Fig 3 Micrograph of the fabricated IC The frequency response of the TIA for both odes of operation is easured individually The parasitic shunt capacitance of the resonator is represented by shunt capacitance to ground, C p, at both input and output terinals of the TIA Since creating a precise AC current source is difficult, a novel ethod is used to deterine the transipedance gain and BW of the TIA The signal fro VNA is first passed through a series RC network and then given to the input of the TIA The capacitor is used to DC-decouple the input of the TIA and the VNA (Fig 33) and is chosen large enough for the frequency of interest The transipedance gain of the TIA, Z TIA, can be found as: v v =, (318) ( R Z ) out out Z TIA = s + iin vs in 100

119 where v s is the source voltage fro the vector network analyzer (VNA), v out is the output voltage of the TIA and Z in is the input ipedance of the TIA As evident fro (318), choosing R s >> Z in, the low-frequency transipedance gain is siply found: v v Z out out 0 = ZTIA = R w 0 s, (319) > iin vs where v out /v s is the voltage gain easured by the VNA To easure the frequency response (esp the BW) of the aplifier, R s is reduced to the original 50Ω input ipedance of the VNA source Using the low-frequency gain of the TIA found in (319) and assuing that the input ipedance of the TIA can be approxiated as a parallel R in C in tank, the location of poles and zeros can be found as: Z 1 = z Z ω TIA ω 0 v = v 1 out s R in 50 + Rin Cin s 1 + 1, ω = p ( Rin 50) Cin RinCin ω 0 v v out s ( 50 + R ) in, (30) It is clear fro (30) that ω z < ω p, therefore the BW of the easured response fro the VNA is reasonably close to the 3-dB BW of the TIA In this work, the axiu designed BW of the aplifier with pf capacitive load is less than 300MHz with doinant pole at input, therefore R in >>50Ω Fig 33 Siplified scheatic of the easureent setup 101

120 Using this ethod, the frequency response of the tunable two-stage RGC TIA is easured When operating in non-inverting ode (the second stage is turned off), the TIA consues 084A fro 3V supply and aintains transipedance gain of 7dBΩ up to 40MHz (Fig 34) In inverting ode when both stages are on, the power consuption is increased by an additional 38W In this case, the BW of the TIA is extended beyond 170MHz with gain ore than 66dBΩ The gain tuning in second stage of the TIA allows for 10dB increase in the gain (without experiencing overshoot) at the expense of saller BW~89MHz (Fig 34) Gain [db-oh] dB BW~40MHz 3-dB BW~170MHz 3-dB BW~89MHz 50 Max gain (both stages are on) 45 Min gain (both stages are on) Gain (nd stage is off) Frequency [MHz] Fig 34 Measured frequency response of the RGC TIA 10

121 The RGC TIA is interfaced with a 35MHz TPOS resonator (Q~10,100) and output spectru is onitored with the spectru analyzer The oscillation is sustained when the supply voltage is increased to 14V and DC current is increased to 400µA The oscillation starts at lower supply voltage of 19V in vacuu and the power consuption is reduced to 580µW (Fig 35) This is ainly due to the lower loss of the resonator when operating under vacuu The phase-noise of the oscillator in air and under vacuu is easured at V DD =5V (P DC =16W) and are copared with each other (Fig 35) The easured phase-noise of the oscillator at 1kHz offset is -103dBc/Hz in air and - 111dBc/Hz under vacuu The phase-noise floor, which is doinated by the TIA and off-chip buffer noise, reaches -140dBc/Hz Close-to-carrier phase-noise perforance between offset frequencies of 10Hz and 1kHz, is iproved by ~ 10dB f 0 ~ 354MHz P 0 ~86dB Span=10kHz Fig 35 Spectru and phase-noise of the 35MHz oscillator ade with RGC TIA 103

122 36 Inverter TIA An inverter TIA is designed and included on the sae chip that the RGC TIA is fabricated on The TIA benefits fro two high-gain stages; an inverter with tunable shunt-shunt feedback resistor that acts as the current-to-voltage conversion stage is followed by a CS voltage aplifier with resistive load (Fig 36) This TIA is designed for larger GBW and naturally, consues ore power When operating in non-inverting ode, both inverting stages are in the loop to ensure in-phase operation; in inverting ode, the second stage is bypassed, leaving an inverter with adjustable gain and 180º phase-shift Fig 36 Scheatic of the Inverter TIA 104

123 For high-frequency operation, both input and output resistances of the sustaining aplifier have to be iniized In addition, all inter-stage nodes have to be provided with a low- ipedance path to ground to avoid a low frequency pole Due to the high gain of the inverter, the transipedance gain is ainly deterined by the tunable shunt-shunt resistor, R tune The equivalent input resistance of the closed-loop syste is: R in Rtune + ( ro 1 ro ) ( g + g )( r r ), (31) 1 o1 o where g 1 and g are transconductance, and r o1 and r o aredrain source resistance of M 1 and M transistors, respectively The second stage of the TIA is a CS with resistive load Careful trade-off of gain with BW obviates the need for additional high-power output stage The transipedance gain of the TIA is: R g 3 R R, (3) CL, Inverter Rtune Av tune out where A V is gain of the nd stage and g 3 is the transconductance of M 3 Neglecting the noise contribution fro nd stage and assuing that the doinant pole is at the input, the input-referred noise of the TIA is: i n, in = ( g + g ) γ d 0,1 d 0, 1 kt ω Cin +, (33) Rtune ( g + g ) R 1 tune 4 Using the ethod specified in section A, the frequency response of the tunable two-stage Inverter TIA is easured When operating in inverting ode (nd stage off) the TIA consues 16A fro 3V supply and provides ore 74dBΩ up to 7MHz The BW can be extended beyond 17MHz at the expense of 13dB lower gain (Fig 37) 105

124 Gain [db-oh] dB BW~60MHz 3-dB BW~7MHz 3-dB BW~81MHz 55 Min gain (nd stage turned off) 3-dB BW~17MHz Max gain (nd stage turned off) 50 Min gain (both stages are on) Max gain (both stages are on) Frequency [MHz] Fig 37 Measured frequency response of the Inverter TIA (V DD =3V) In non-inverting ode (both stages on), the power consuption is increased by 34W The BW of the TIA is ~ 60MHz with gain ore than 83dBΩ The gain tuning in the first stage allows for 1MHz iproveent in BW at the expense of saller gain~68dbω (Fig 36) Increasing the supply to 5V enables BW > 0MHz (Fig 38) The Inverter TIA is interfaced with the sae 35MHz TPOS resonator that is used in previous section, and the output spectru is onitored with a spectru analyzer The oscillation is sustained when the supply voltage is increased to 175V and DC current is increased to 80µA The oscillation starts at lower supply voltage of 16V under 106

125 vacuu and the power consuption is reduced to 60µW (Fig 39) This is ainly due to the lower loss of the resonator under vacuu The phase-noise of the oscillator in air and under vacuu is easured at V DD =5V (P DC =38W) and are copared with each other (Fig 39) The easured phase-noise of the oscillator at 1kHz offset is -105dBc/Hz in air and below -114dBc/Hz under vacuu The phase-noise floor, which is doinated by the TIA and off-chip buffer noise, reaches -14dBc/Hz When coparing the phase-noise perforance of this oscillator with the one that is ade with the RGC TIA, substantial iproveent in the close-tocarrier perforance is clearly visible Gain [db-oh] dB BW~100MHz 3-dB BW~88MHz 3-dB BW~150MHz 3-dB BW~7MHz 60 Max gain (both stages turned on) 55 Min gain (both stages turned on) Min gain (nd stage turned off) Max gain (nd stage turned off) Frequency [MHz] Fig 38 Measured frequency response of the Inverter TIA (V DD =5V) 107

126 f 0 ~ 354MHz P 0 ~96dB Span=10kHz Fig 39 Spectru and phase-noise of the 35MHz oscillator ade w/ Inverter TIA 363 Multiple-Stage Feedback TIA To realize an oscillator in the UHF range using a lossy icroechanical resonator with large input/output parasitic capacitance (~pf), it is crucial to use high-gain broadband TIA To this end, a three-stage feedback TIA with variable gain at the first stage is designed (Fig 330) [7] The TIA was intended to be a universal design, capable of sustaining oscillation with a broad range of resonators having characteristics of: 100MHz < f < 1GHz and 50Ω < R < 1kΩ To achieve high gain while aintaining the wideband characteristic of the TIA, a lowgain transipedance stage is followed by two wideband voltage gain stages Shunt-shunt 108

127 feedback is introduced in each voltage gain stage to reduce the ipedance at the interstage nodes This technique increases the frequencies of the poles resulting fro the inter-stage nodes to uch higher than those of the input/output; thus providing wideband characteristic without increasing the power consuption Another advantage of this technique is to eliinate on-chip inductors typically used in high-gain gigabit CMOS TIA circuits to enhance the bandwidth The result is significant reduction in area Fig 330 Scheatic of the three-stage tunable feedback TIA (biasing not shown) The designed TIA achieves BW > 880MHz at axiu gain (7dBΩ) when loaded with pf capacitance load at the input and output node The ain reason to choose coon source over higher gain topologies such as cascode is to increase the voltage swing and enable the circuit to operate fro lower supply (in this case 15V) that further reduces the 109

128 power consuption The higher output swing results in lower phase-noise floor as the dynaic range of the TIA will be iproved To boost the gain at higher frequencies, capacitive coupling is used in the third stage The high pass response of the third stage significantly attenuates the low frequency noise of the aplifier, which is higher in CMOS circuits due to large flicker noise Therefore, the contribution of TIA noise to the overall close-to-carrier phase-noise is reduced The choice of capacitor C F deterines the attenuation For the case of pf, the phase-noise at 1kHz offset is db lower than the oscillator constructed with the sae resonator but using the TIA without capacitive coupling The TIA and biasing circuitry is fabricated in a 018u 1P6M CMOS process Another TIA that does not incorporate capacitive coupling was also fabricated on the sae die for the purpose of perforance coparison An off-chip 50Ω buffer is used to interface with the easureent equipents The TIA was easured to have axiu transipedance gain of ore than 718dBΩ and axiu BW in excess of 960MHz when loaded with pf at both input and output nodes The TIA BW when interfaced with standard photodiodes with equivalent capacitance ~500fF will be enhanced to 15GHz The TIA gain could be varied by 8dB (Fig 331) The aplifier and biasing circuitry consued 6A fro 15V supply The die size is 1 of which 450µ 330µ is occupied by the sustaining aplifier (Fig 33) 110

129 This three-stage feedback TIA is interfaced with a 496MHz AlN-on-Si (Q unloaded ~3,800) TPOS resonator The output power of the 496MHz oscillator is ~db The easured phase-noise of the oscillator in air is 9dBc/Hz at 1kHz offset and below 147dBc/Hz at far-fro-carrier (Fig 333) The easureent was carried out by an Agilent EE5500 phase-noise analyzer The oscillation power was 19dB, well within the resonator linear range The slight degradation in phase-noise perforance around 100kHz offset is due to the internal phase-noise liit (~ 136dBc/Hz) of the Agilent E857C Analog Signal Generator that is used in the phase-noise easureent setup The spurs below 1kHz are caused by 60Hz signal and its haronics Fig 331 Measured gain of the three-stage feedback TIA 111

130 Test circuits TIA w/o capacitive coupling TIA with capacitive coupling Fig 33 Micrograph of the fabricated die 1/f 3 region f o ~4966 MHz P out ~db 1/f region 1/f region Noise floor Fig 333 Phase-noise of the 08MHz and 496MHz oscillators 11

131 363 TIA with Inductive Shunt Peaking The BW enhanceent techniques that were introduced so far take a high toll either on the power consuption or the noise perforance of the TIA The open-loop architectures are known for higher input-referred noise The feedback approach forces trade-off of gain and BW, leaving no choice but to increase the power consuption when both high gain and BW are desired A logical conclusion would be to cobine feedback approach and pole cancellation to siultaneously increase the BW while eeting the required transipedance gain specification In this section, a two-stage high-gain broadband differential CMOS TIA that uses inductive shunt peaking is presented (Fig 334) V DD R load VBP VBP M 10 M 4 M 5 M 11 R load Voutp VCT VCT Voutn L shunt L shunt Vresn M 6 M 7 Vresp M 13 M 8 M 1 M M 9 M 1 In Ip VBN M 3 Fig 334 Scheatic of the two-stage differential TIA with inductive shunt peaking The TIA uses feedback in the first stage to provide large BW and good noise atching when used in icroechanical oscillator applications The gain tuning is incorporated in this stage by varying the equivalent resistance of the MOS resistor The gain is further increased b cascading an additional CS stage to the first stage The nd stage uses inductive shunt peaking to cancel the effect of output pole that is resulted fro large shunt parasitic capacitance of the icroechanical resonator A diode-connected NMOS 113

132 transistor is placed in series with the inductor to increase the resistive load of this stage and increase the gain The value of this resistance is carefully chosen to eet the required gain specification for the overall TIA Finally, a 50Ω-atched CS output buffer stage is added to interface the output of the TIA with the 50Ω input ipedance of easureent equipents The advantage of differential signaling is the coon-ode rejection that helps suppress the noise injected fro supply and other bias circuits Moreover, it helps iprove the stability by iniizing the effect of parasitic inductances that appear at critical nodes such as the reference ground The two-port nature of ost high-frequency lateral icroechanical resonators akes the fully-differential operation challenging Therefore, the coon-ode feedback (CMFB) circuitry is not included in this pseudodifferential TIA The TIA is designed and fabricated in 013μ process Due to the lack of proper equipent for fully-differential gain and noise easureent, only the siulated data is presented here The TIA is capable of providing ~64dBΩ (Fig 335) and BW>17GHz with pf input/output capacitive load while consuing 98W (including the on-chip buffer) The differential gain can be tuned up to 7dBΩ at the expense of reduction in BW (~1GHz) The TIA noise is siulated with pf input and output capacitive load Due to pole cancellation at the output, the doinant pole is at the input of the TIA The siulated input-referred current noise is 53pA/ (Fig 336) Although this data could be very valuable to understand the noise echanis and help with optiization process, it is of little practical value due to the absence of proper gateinduced noise odel in the BSIM31 transistor odels that are used in this work 114

133 Gain 17GHz Fig 335 Differential transipedance gain of the TIA with inductive shunt peaking I n ~53pA / 10GHz Fig 336 Input-referred current noise of the TIA 115

134 To benchark the TIA perforance for icroechanical oscillator applications, the TIA is interfaced with a 06MHz AlN-on-Si resonator with relatively low-q (~1,00) and high otional ipedance (~600Ω) The oscillator achieves phase-noise better than - 78dBc/Hz at 1kHz offset but the far-fro-carrier perforance is not ipressive (Fig 337) This is due to the liited dynaic range of the nd stage that uses a diodeconnected NMOS in the load This poor phase-noise perforance cobined with large inductors used for shunt peaking (75nH each), akes the TIA unattractive for low phasenoise icroechanical oscillators f osc ~061MHz P osc ~-10dB Span=50kHz Fig 337 Spectru and phase-noise of the 06MHz AlN-on-Si oscillator 365 TIA with Current Pre-Aplifier High Q lateral-ode silicon icroechanical resonators are suitable for ulti-frequency references but exhibit high otional resistance copared to FBAR The otional 116

135 resistance can be reduced at the expense of larger transduction area and hence larger parasitic capacitance This high otional resistance cobined with large parasitic capacitance of the resonator akes the realization of low-power oscillator coplicated As such, the developent of low-power high-gain transipedance aplifiers (TIA) becoes necessary The ost popular TIA topology used in icroechanical oscillators is the shunt-shunt feedback TIA as it iproves the BW and reduces the input-referred noise [6], [7] The BW iproveent forces a trade-off with the gain Further increase in the gain requires higher power consuption that is undesirable Using a broadband current aplifier increases the gain while aintaining the BW with little or no extra power consuption In this section, an inductor-less 018µ CMOS tunable TIA that uses a broadband current pre-aplifier for gain boosting is presented [66] The easured gain is varied fro 64dBΩ to 76dBΩ in a BW of 17GHz to 1GHz with pf input/output load The TIA consues 48A fro 15V supply Fig 338 shows the TIA scheatic and consists of 3 sections: current pre-aplifier that is cobined with the current-to-voltage conversion stage, voltage aplifiers and 50Ω buffer The first stage uses a broadband current aplifier to achieve gain with inial effect on BW The current gain is set by the W/L ratio of M 3 to M 1 transistor (N) The aplifier is a odification of inherently-low input resistance current-irror (~1/g 1 ) 117

136 topology that is suitable for reducing the power consuption The feedback further reduces the input resistance by a factor ~ g r ds Neglecting the effect of M 5 : R in = 1 1 g (1 + g r ) + g + g g g r, (34) 1 ds ds1 ds4 1 ds where g 1, g are transconductances of M 1 and M, and g ds1, g ds, g ds4 are drain-source conductance of M 1, M, and M 4, respectively Current-to-voltage conversion is also perfored in this stage; the current flowing through drain of M 1 is irrored into M 3 and passed through a resistive load to produce a voltage Using sall resistors ensures inial effect on BW The transipedance gain in the first stage can be written as: z ( R r ) R N, (35) 1 ds3 where N is the gain of the current irror, R 1 is the load resistance, and r ds3 is the drainsource ipedance of M 3 The power consuption of the first stage is ~3W The voltage aplifier is a odified cherry-hooper that consists of two coon source (CS) stages with gain tuning in second stage Shunt-shunt feedback reduces the input and output ipedance of the last stage, which in turn, help increase the BW by pushing the poles to higher frequency Using a tunable PMOS resistor in the feedback network iproves the linearity, lowers the noise contribution, and akes the TIA capable of interfacing with variety of icroechanical resonators with different loss The resistive feedback is replaced with an RC network to create a zero whose frequency can be tuned to cancel the effect of the output pole To obtain the frequency response, two sets of S-paraeters, one for axiu and the other for iniu gain were easured and interfaced in ADS with an ideal AC current 118

137 source with pf load Gain > 76dBΩ with BW~17GHz is achieved The gain can be tuned to 64dBΩ with BW > 1GHz (Fig 339) Replacing the pf load with a photodiode (C p ~500fF), the BW is extended to 5GHz with gain > 76dBΩ V B1 C Z ω z R tune + R R R C tune z z z R tune R z M 50 I in A v1 A v +1 Current ap w/ feedback I-to-V converter R Z V DD V B I in M 4 M V B1 R 1 V B M 7 V TUNE V B M M M 1 3 M 5 M 6 M 8 R Z M 9 M 11 C Z Current ap and current-tovoltage conversion stage Voltage aplifiers with BW enhanceent 50 buffer Fig 338 Scheatic of the TIA with current aplification stage To easure the input-referred noise of the TIA, the input is connected to ground through a pf capacitor to eulate the loading of the resonator The gain is set to axiu and the output signal is recorded fro 10MHz to 5GHz Due to the very sall BW of the resonators, spot noise at a particular frequency is a ore relevant perforance etric 119

138 than the average noise (Fig 340) Optiization of input transistor paraeters has yielded an input-referred noise current of less than 7pA/ Hz in the MHz range dB BW ~ 17GHz Gain [dbω] dB BW ~ 1GHz Maxiu gain (w/ pf) Miniu gain (w/ pf) Frequency [GHz] Fig 339 TIA gain when the S-paraeters are interfaced with ideal current source Due to the large power handling of AlN-on-Si resonators [7], the oscillation power is set by nonlinearity of the TIA As such, the dynaic range and gain copression of the TIA have direct ipact on the perforance of the oscillator The use of relatively wide-swing CS output stage with feedback has pushed axiu output swing, which directly influences the overload current, beyond 06V p-p Considering the input-referred noise of 7pA/ Hz in the MHz, the TIA achieves a rearkably high dynaic range of 138dB in this range To obtain the 1-dB copression point (P 1dB ), the S-paraeters of the TIA in axiu gain setting is easured when the input power is varied fro -0dB 10

139 to -10dB The input-referred P 1dB (after 10dB adjustent due to the reflection) is - db The BW is only reduced by 8% to 16GHz (Fig 341) The linearity is iproved due to the use of low-gain output stage with tunable shunt-shunt feedback in the aplifier section The TIA perforance is copared with the state-of the-art 018 µ CMOS TIAs [67]-[70] (Table 31) When interfaced with a photo-diode (C p ~500fF), the TIA achieves a figure of erit of 190 GHzΩ/W (GBW per DC power) 1000 Input-Referred Current Noise [pa/ Hz] Frequency [GHz] Fig 340 Measured input-referred noise of the TIA with pf input load To deonstrate its high perforance, the TIA is interfaced with two high order lateralode icroechanical resonators: a high-loss 74MHz (Q unloaded ~000, R ~ 750Ω, C p ~15pF) and a high-parasitic 1006GHz (Q unloaded ~7100, R ~ 150Ω, C p ~3pF) AlNon-Si resonators The Q of 1006GHz resonator is iproved by optiizing the resonator 11

140 geoetry and the anchors to iniize the acoustic loss by confining the energy in a single resonant ode of the structure The oscillation at 74MHz and 1006GHz starts with ~16W and ~19W, and grows to -8dB and -3dB, respectively Gain [db-oh] dB BW [GHz] Input power [db] Fig 341 Large-signal gain and BW behavior of the TIA (loading = pf) Table 31 Perforance coparison of the state-of-the-art CMOS TIAs Spec [67] [68] [69] [70] This work Gain (dbω) (siulated) BW (GHz) C in (pf) Dynaic range (db) 14 N/A 66 N/A 138 Input-referred noise 19 (siulated) 4 N/A (pa/ 8 GBW/P DC (GHzΩ/W) P DC (W) Chip area ( ) Process 018μ 018μ 018μ 018μ BiCMOS * 018μ CMOS CMOS CMOS CMOS <7 (01-09GHz) 1

141 The phase-noise easureent is easured at V DD =15V Owing to its higher Q, the phase-noise of 1006GHz oscillator reaches 94dBc/Hz at 1kHz offset and outperfors the 74MHz oscillator by 8-1dB (Fig 34) Higher TIA noise at 1006GHz partially offsets its higher output power, resulting in ~db iproveent in phase-noise floor, - 154dBc/Hz In coparison with previously reported state-of-the-art AlN-on-Si oscillators [7], iproveent in phase-noise floor is due to the lower noise TIA Fig 343 shows the icrograph of the die fabricated in 018µ 1P6M CMOS process when interfaced with the 74MHz AlN-on-Si resonator The resonator diensions are less than 300µ 100µ The absence of on-chip inductors has reduced the IC area to 650µ 500µ 1006GHz Fig 34 Measured output spectru and phase-noise of 1006GHz oscillator 13

142 Fig 343 Micrograph of the IC when interfaced with the 74MHz resonator 14

143 366 Coparison of Different Enhanceent Techniques Coparing the enhanceent techniques presented in previous sections reveals that the best approach to reduce the input-referred noise and provide good noise atching is to use shunt-shunt feedback at the input of the TIA The shunt-shunt feedback also helps increase the BW The gain enhanceent at low power consuption is best achieved when a current pre-aplifier is used in addition to the current-to-voltage conversion stage Pole cancellation is the key to iprove the BW without sacrificing the gain and having to resort to the unpleasant choice of increasing the power consuption Another valid concern is the linearity of the TIA that is best achieved with feedback TIA configuration Table 3 suarizes the coparison of different TIA techniques Table 3 Coparison of different high perforance techniques Topology Gain BW Noise Linearity Power Multi-stage feedback Inverter TIA 4 3 Regulated Cascode Feedback with inductive peaking Current-based w/ feedback Conclusion Stringent gain, noise, BW, and power consuption requireents for the TIAs that are used as sustaining aplifier of icroechanical oscillators call for a odified for the high frequency low-power TIA design In this chapter, a systeatic approach to the design of open-loop and feedback TIAs for lateral icroechanical oscillators along with perforance iproveent techniques are presented 15

144 CHAPTER 4: Electronic Tuning for Lateral MEMS Oscillators Frequency tuning is an integral part of any icroechanical reference oscillator as it provides a echanis to copensate for process and teperature variation in the reference oscillator [] In addition, for sufficiently large tuning range, it increases the functionality of radio transceivers by covering several channels that fall into the frequency tuning range This chapter explores electronic frequency tuning for lateral icroechanical oscillators The discussion starts with introduction into different frequency tuning ethods for icroechanical oscillators and continues on electronic tuning techniques for seriesresonant icroechanical oscillators Then, the effect of resonator parasitic is investigated to deterine the practical liits for the frequency tuning range in lateral series-resonant icroechanical resonators Next section presents tuning enhanceent ethods based on parasitic cancellation and offers exaples fro tunable high frequency lateral icroechanical oscillators to support and benchark the perforance of oscillators for each ethod 41 Introduction The ability to tune the frequency of oscillation is a key requireent to achieve accurate and teperature/process-copensated reference oscillator The frequency tuning in icroechanical oscillators is either achieved by varying the resonance frequency of icroechanical resonator or by introducing additional phase-shift in the oscillation loop (ainly on the sustaining aplifier side) Several techniques have been used to tune the 16

145 frequency of icroechanical resonators These techniques can be categorized into two groups: resonator-based techniques and electronic-based techniques Resonator-based techniques rely on the acoustic properties of the resonator structure to induce a shift in the resonance frequency Since the echanical resonance frequency is proportional to K electrical /K echanical, the echanical resonance frequency of a fixed geoetry can be changed either through electrostatic tuning or echanical/aterial tuning ethods Electrostatic tuning involves the use of an electrical signal to vary K electrical in a predictable anner Flexural bea resonators or IBAR take advantage of this ethod to deliver significant tuning range in excess of 1000pp Mechanical/aterial tuning is ore coplicated Peranent shift in the resonance frequency can coe through ass loading [71] or excessive doping [7] Teporary shift in the resonance frequency can be achieved by exploiting the dependency of Young s Modulus to paraeters such as teperature [6] Both of electrostatic and echanical/aterial tuning techniques require large DC voltages and increase the power consuption of the syste Moreover, the absence of polarization voltage akes these ethods ipractical for piezoelectric resonators Electronic frequency tuning techniques for icroechanical resonators priarily rely on creating a phase-shift in the oscillation loop This phase-shift is usually achieved by using a tunable capacitor or a varactor whose capacitance can be independently controlled by an electrical signal Depending on the type of the resonator and the required tuning range, 17

146 the tunable capacitor can be placed either in series or in parallel with the icroechanical resonator Parallel tuning has been used extensively for teperature copensation in quartz crystal oscillators to deliver voltage-controlled crystal oscillators (VCXO) Series tuning is a natural choice for series-resonant icroechanical oscillators; however, it is yet to be fully explored as a viable alternative that can provide large tuning range that is sufficient to tackle the coplicated process and teperature copensations of these reference oscillators The goal of this study is to identify the liitations of series tuning technique and find ways to address these shortcoings 4 Electronic Tuning for Series-Resonant Microechanical Oscillators Series-resonant icroechanical resonators can benefit fro both parallel and series tuning Series-resonant icroechanical resonators can be categorized into two groups: thickness-ode and lateral-ode icroechanical resonators Although both types of series-resonant icroechanical resonators can benefit fro parallel and series tuning, the focus of this work is on lateral-ode icroechanical resonators with large shunt parasitic capacitance 41 Parallel Tuning Parallel tuning can be accoplished either by adding a feedthrough tunable capacitor between the input and output terinals or by adding a shunt tunable capacitor between the input/output terinal and reference ground Changing the feedthrough capacitance shifts the anti-resonance frequency of the resonator which in turn, pulls the resonator away fro the natural resonance frequency The aount of tuning is dependent on the resonator feedthrough capacitance, initial value of the tunable capacitor, and its tuning range This approach is ore effective for thickness-ode series-resonant 18

147 icroechanical resonators where the feedthrough capacitance is large and has a easureable ipact on the resonance frequency Changing the effective feedthrough capacitance of FBAR that has negligible shunt parasitic capacitance has the potential to deliver large tuning range in excess of 10000pp On the other hand, for lateral-ode series-resonant icroechanical resonators with very sall feedthrough capacitance (<100fF), large shunt parasitic capacitance (>pf) and high loss (>100Ω), this approach is not very effective For these icroechanical resonators, the recoended approach is to shift the resonance frequency by varying the shunt parasitic capacitance of the resonator This approach has been widely used in VCXOs for frequency pulling in the order of few hundred pp For higher-loss icroechanical resonators, the tuning is even saller Several oscillator topologies are suitable for parallel tuning A universal topology that is widely used for both quartz crystal and icroechanical oscillators is the Pierce topology (Fig 41) In Pierce oscillator, the oscillation criteria is satisfied slightly offresonance which is due to the influence of shunt capacitors at the input and output of the sustaining aplifier At oscillation, the resonator exhibits inductive behavior and exhibits near 90º phase shift Additional phase-shift coes fro the inverting aplifier (180º) and shunt capacitors (90º) The oscillation frequency can be deterined by equation (41) The ajor proble with Pierce oscillator topology is the close-to-carrier phase-noise perforance; the effective Q of the resonator when operates off-resonance is significantly lower This gives rise to higher phase-noise which is undesirable Another iportant 19

148 130 proble is the liited tuning range (<500pp) for high-frequency lateral icroechanical resonators with high Q and sall otional capacitance ( ) ( ) ( ) ,, p p p p eq p eq p o n o f loop p p loop b loop p p eq p p eq C C C C X C X X X R X r r R R C C R g g A C C L C C L + = = + + ω ω ω (41) Fig 41 Block diagra of a pierce oscillator Another parallel tuning ethod that can be used for lateral icroechanical oscillators with large shunt parasitic capacitance is creating extra phase-shift in the loop by shifting

149 the frequency of one or ore poles/zeros of the closed-loop syste (Fig 4) Exploiting the effect of large shunt parasitic capacitance on the frequency of oscillation, the extra phase-shift created in this ethod cobined with the large gain of the TIA satisfies the oscillation condition at a frequency that is slightly different fro the resonance frequency of the icroechanical resonator The ain concern in this tuning ethod is that the TIA needs to have large excessive gain beyond what is needed to satisfy the oscillation gain criterion Siilar to the Pierce oscillator, this ethod results in lower effective Q when the oscillation is sustained This lower Q results in inferior phase-noise perforance that is undesirable for low phase-noise icroechanical oscillators Moreover, it has a negative ipact on the absolute frequency accuracy of the oscillator Fig 4 Block diagra of the oscillator that uses parallel tuning To deonstrate the frequency tuning range achieved with this ethod, a 497MHz lateral icroechanical resonator (R ~50Ω, Q unloaded ~1,500, C p ~5pF) is interfaced with a 131

150 three-stage 018μ tunable CMOS TIA that uses cascaded feedback topology explained in 445 (Fig 43) The TIA achieves axiu transipedance gain of 7dBΩ up to 900MHz across PVT with pf input/output capacitive load and burns less than 4W Using the gain tuning that is incorporated into the first stage of the TIA the frequency of the oscillation can be varied by over 600pp fro 49731MHz to 49761MHz (Fig 44) VBP V DD VBP VBP VBP VBP Vres-p VCT VCT Vres-n In Ip VBN Fig 43 Scheatic of the three-stage CMOS tunable TIA f=49731mhz f=49761mhz Fig 44 Output spectru of the 497MHz tunable oscillator Although this tuning range is relatively large, the phase-noise degradation (over 10dB across the tuning range) due to Q poses a considerable challenge to successful realization 13

151 of low phase-noise tunable lateral icroechanical oscillators The tuning range is deterined by the aount of phase-shift in the loop that is in-turn proportional to the ratio of the resonator otional capacitance, C, to its shunt parasitic capacitance, C p As such, at lower frequencies, the tuning range ay be coparable (>4000pp at 7MHz) 4 Series Tuning Series tuning is the ost natural choice for series-resonant icroechanical oscillators and is usually accoplished by placing a tunable capacitor in series with the resonator in the oscillation loop that changes the effective otional capacitance of the resonator The tunable capacitor can be placed either on the IC side, for ease of electronics design and control, or integrated with the resonator for best tuning perforance (Fig 45) For oscillators that are built with series-resonant icroechanical oscillators, the series cobination of varactor and otional capacitance of the resonator, C, exhibits lower overall capacitance, which in-turn causes an upward shift in the oscillation frequency The aount of frequency shift can be accurately deterined by designing a precision control circuitry to supply the varactor tune signal In oscillators that are built based on series-resonant resonators with inial shunt parasitic such as quartz crystal or FBAR, series tuning provides large tuning range with a potential to offer a fully-electronic teperature- and process-copensated solution However, the designers still have to watch for the effect of large feedthrough parasitic of high frequency thickness ode resonators such as FBAR on the tuning range and phasenoise perforance of the oscillator 133

152 43 Series Tuning in Lateral Microechanical Oscillators Series tuning for lateral icroechanical oscillators warrants a ore detailed study as these resonators suffer fro large parasitics (especially large shunt parasitic capacitance) that have a ajor negative ipact on the tuning range of the oscillator In this section, the effect of parasitics on the tuning range of the oscillator is investigated 431 Lateral Microechanical Oscillator with Ideal Resonator A lateral icroechanical oscillator based on an ideal series-resonant icroechanical resonator with no shunt and feedthrough parasitic capacitance, the oscillation frequency is given by: f tune0 = π 1 CC L C + C tune,0 tune,0, (4) where C tune,0 is the iniu varactor capacitance and C is the otional capacitance of the icroechanical resonator The axiu tuning range of the icroechanical oscillator can be expressed by: f f tune,1 tune,0 f ( 1+ k)( C + C ) tune0 tune,0 = = = 1+, (43) f + Δf tune,0 C + kc ( 1+ k ) Ctune,0 C + ( 1+ k) Ctune, 0 where k is the varactor tuning ratio According to (43), there is no theoretical upper liit to the tuning range for infinitely-large tuning ratio or infinitely-sall tunable capacitor In practice, however, the tuning range is severely liited due to the resonator parasitic, especially the large shunt parasitic capacitance appearing at the input and output of ost lateral icroechanical resonators 134

153 TIA with Tunable Gain Voltage Aplifier R TUNE C TUNE TIA Ap L C R C p C p Fig 45 Diagra of the tunable icroechanical oscillator that uses series tuning 43 Lateral Microechanical Oscillator with Practical Resonator Practically, lateral icroechanical resonators exhibit parasitic effects both in the for of feedthrough capacitance and shunt parasitic capacitance at both the input and output terinals The feedthrough capacitance is very sall (<50fF) and therefore, has a negligible effect on the tuning range of the icroechanical oscillator Here, we focus ore on the effect of shunt parasitic capacitance on the tuning range of the lateral icroechanical oscillator For an oscillator based on a series-resonant icroechanical resonator with input/output shunt parasitic capacitance and no feedthrough parasitic, the oscillation frequency is given by: 135

154 f ( C p + Ctune,0 ) ( C + C ) 1 C = 1+, (44) π L C C p p tune,0 where C p is the shunt parasitic capacitance of the lateral icroechanical resonator Using equation (44), the axiu tuning range can be expressed by: f f tune,1 tune,0 ( C p + Ctune,0 ){ C p[ C p + ( 1+ k) Ctune,0] + C[ C p + ( 1+ k) Ctune,0 ]} [ C + ( 1+ k) C ][ C ( C + C ) + C ( C + C )] =, (45) p tune,0 p p tune,0 p tune,0 Equation (45) clearly deonstrates the liitation to the axiu frequency tuning range in the presence of resonator shunt parasitic capacitance; the axiu tuning range is inversely proportional to the ratio of C p over C For an infinitely-sall varactor (C tune,0 <<C <<C p ), the axiu tuning range can be approxiated by: f f tune,1 tune,0 C 1+ (46) [ C + ( 1+ k) C ] p tune,0 Often ties, in practical applications with on-chip electronic tuning, the choice of process technology deterine the iniu available size of the on-chip varactor To have an idea about what would be the axiu tuning range in this case, a 500MHz icroechanical resonator with Q unloaded =,000, R =00Ω, and C p =pf is considered Equation (46) gives around 3000pp for axiu tuning range However, unless using a deep sub-μ process with nanoeter range feature size, the iniu value of the varactor, C tune,0, is at least an order of agnitude higher than C of the icroechanical resonator In this case, the axiu tuning range can be approxiated by: f f tune,1 tune,0 p + (47) C p C + C C C + C p In this case, the axiu tuning range of the sae 500MHz icroechanical oscillator drops below 500pp which is siply not sufficient for ost process and teperature 136

155 copensation applications In order to better understand the challenges posed to the oscillator tuning by the shut parasitic capacitance of the resonator, the frequency tuning of the sae 500MHz oscillator is plotted vs the shunt parasitic capacitance, C p for different Q and R values (Fig 46) Each plot has a faily of curves for different resonator Q with a fixed R The study of these curves shows that the frequency tuning range severely deteriorates when the shunt capacitance is increased beyond 1pF In fact, even for very sall shunt parasitic capacitances in the range of 500fF, the tuning range iproveent for resonators with R > 00Ω is relatively odest and in no way ipressive (<1000pp) What akes the atter worse is that R is inversely proportional with the Q; ie the tuning range is further shrunk for a lower phase-noise oscillator that is using a higher Q resonator Fro these results it becoes clear that efforts need to be ade to eliinate or at least significantly reduce the effect of shunt parasitic capacitance on the tuning range of the oscillator 137

156 Maxiu Tuning Range vs C p 1400 Maxiu Tuning Range vs C p Frequency Tuning [pp] Q=k Q=3k Q=5k Frequency Tuning [pp] Q=k Q=3k Q=5k Shunt Capacitance [F] x Maxiu Tuning Range vs C p Shunt Capacitance [pf] x Maxiu Tuning Range vs C p Frequency Tuning [pp] Q=k Q=3k Q=5k Frequency Tuning [pp] Q=k Q=3k Q=5k Shunt Capacitance [pf] x Shunt Capacitance [pf] x 10-1 Fig 46 Series tuning liitation for 500MHz lateral icroechanical oscillator 433 nd -Order Parasitic Effects on Tuning Range Apart fro the shunt parasitic capacitance, other parasitics of the icroechanical resonators have an ipact on the tuning range Although the scope and extent of this ipact is heavily dependent on the TIA topology and resonator characteristic (resonance frequency, shunt parasitic capacitance, loss, and Q), the ipact fro nd -order resonator parasitics is relatively insignificant when copared to non-idealities of the sustaining aplifier and electronic tuning network Nevertheless the nd -order parasitic both fro IC and icroechanical resonator continue to pose a challenge The nd -order parasitic effects in the resonators ostly include the feedthrough capacitance The effect of 138

157 feedthrough capacitance on the resonator is usually negligible as the varactor capacitance, C tune,0, is significantly larger than the feedthrough capacitance nd -order effects fro the electronics are centered on the nonlinearity of the varactor These nonlinearities include Q liitation, self-resonance, noise, and the dynaic range Low-Q varactors cause degradation in phase-noise perforance by adding to the overall noise of the sustaining aplifier In addition, they negatively affect the tuning range by adding a series parasitic resistance This extra resistance liits the effective capacitance change across the tuning range which results in saller tuning range Liited self-resonance frequency for the varactor can be odeled by a series inductor Siilar to the Q liitation this effect results in saller change in varactor capacitance across the tuning range with negative consequence for the tuning range Noise of the varactor is a critical issue in the perforance of the oscillator Although it ay not have a direct ipact on the tuning range of the icroechanical oscillator, its effect on the phase-noise degradation can not be ignored The ain noise sources for MOS and junction varactor are flicker and theral These noise sources contribute to the phase-noise of the oscillator with the forer having a ajor ipact on the close-tocarrier phase-noise perforance The specified phase-noise requireent for the icroechanical reference oscillator ay indirectly liit the useful tuning range 139

158 Dynaic range liitation is a significant challenge for any electronic circuit operating in large-signal regie Oscillators that benefit fro high-gain TIAs are no exception The dynaic range of the varactor further constrains the perforance of the oscillator by reducing the spurious-free dynaic range (SFDR) that results in severe degradation in phase-noise perforance (especially far-fro-carrier) This could be in the for of higher power haronics, ie larger total haronic distortion (THD) content with ipact on the far-fro-carrier phase-noise, and/or the appearance of unwanted spurs in the phase-noise of the oscillator Siilar to varactor noise, the outcoe ay indirectly affect the usable tuning range of the icroechanical reference oscillator 44 Tuning Range Enhanceent through Shunt Capacitance Cancellation Fro the discussion in section 43, it is now obvious that the tuning range in high frequency lateral icroechanical oscillators are significantly liited by the presence of shunt parasitic capacitance to a level that is not sufficient for the ajority of applications Naturally, the tuning enhanceent techniques have to focus on this issue by trying to reduce (and hopefully copletely cancel) the effect of shunt parasitic capacitance of the resonator on the oscillator tuning range Therefore capacitance cancellation techniques becoe necessary This section focuses on different approaches for cancelling the shunt parasitic capacitance of the resonator 441 Active Inductance Cancellation A well-known approach to cancel the effect of an electrical circuit eleent is to use its dual counterpart to cancel its effect In this case, the shunt parasitic capacitance can be resonated out at or near the frequency of oscillation with an appropriately-sized inductor (Fig 47) Due to the low frequency of oscillation in ajority of cases (<1GHz), the 140

159 inductance value is relatively large (>0nH) Monolithic on-chip inductors are very low- Q and consue large on-chip area In addition, they can not be tuned to accoodate for the possible variation in the effective shunt parasitic capacitance that is usually present in practical applications (eg bondwire and IC parasitic) Therefore, they are not a good choice for shunt parasitic cancellation On the other hand, active inductors are relatively sall, tunable and potentially exhibit higher Q [49], [6] C TUNE L C R L p C p C p L p 1 (4π f 0 ) C p Fig 47 Concept of tuning enhanceent based on active inductor cancellation The ain disadvantage of active inductors when copared to their passive counterparts is the excessive noise associated with the active eleents used in the active inductor The higher noise calls for iniizing the nuber of active eleents A single-transistor oneport active inductor that is a derived fro coon drain (CD) topology can potentially result in inial extra noise at the expense of saller tuning range [49] Fig 48 shows the scheatic of the single-transistor one-port active inductor with its equivalent luped electrical circuit odel 141

160 Fig 48 Scheatic and equivalent odel of the single-transistor active inductor The input ipedance of the circuit can be expressed by: Z Z Z in R g in s in s G C gs + C R s + 1 G gs s 1, (48) 0 g where g and C gs are the transconductance and gate-source capacitance of the MOS transistor The input resistance approaches a purely resistive value at very low and very high frequencies that are different, effectively paving the way for eulating an inductive response at a pre-defined frequency range The equivalent inductance, L in can be approxiated by: 14

161 L R R in p s = C = R gs G 1 = g R R s p 1 g (49) Using the inforation provided in equation for (49) for R s and R p, the Q of the inductor when R G >>1/g, can be approxiated by: Rp g Q in = L ω C in gs, (410) where ω is the angular frequency Since g /C gs is proportional to the transition frequency (f T ) of the process, Q ind is liited by the choice of process technology (transistor size) and the power consuption (transconductance) Therefore, in a given technology, a higher Q active inductor is only achieved at the expense of higher power consuption In this work, we priarily use 018μ CMOS process that offers f T 55GHz As such, the Q ind >50 ay be achieved for 300MHz < ω < 1GHz This Q is sufficient for cancelling the C p to within 10% of its noinal value 44 Negative Capacitance Cancellation Another approach to cancel the shunt parasitic capacitance of the icroechanical resonator is to place a negative capacitor of equal value in parallel with the shunt parasitic capacitance at the input/output of the resonator (Fig 49) For coplete cancellation and best phase-noise perforance, this single-port negative capacitor should be tunable, low-noise, and high Q Meeting all of these requireents with low power consuption is challenging 143

162 C = in C P Fig 49 Concept of tuning enhanceent based on negative capacitance cancellation There are several ethods to create a negative capacitance Most of these ethods rely on the concept of negative ipedance converter (NIC) NIC usually involves an aplification stage configured in such a way to introduce a phase-shift of -180 between the voltage and current of the input signal An NIC circuit can be used to transfor any arbitrary ipedance into its algebraic negative (Fig 410) NIC s can be realized either as a two-port topology (with differential operation capability) such as cross-coupled pair [73] or single-port proposed by Linvill [74] Soe topologies allow for inclusion of floating nodes that ake the design robust for both single- and two-port applications [74] In this work, we use a siple two-transistor NIC that has the potential to operate both as a single-port or two-port network [74] The original circuit is proposed by Linvill in 1953 but uses bipolar transistors The circuit is odified for CMOS by providing current source to feed the current and a resistive network to bias the gate of the transistors This extra resistive biasing network provides flexibility in the design as the transistor biasing is not dependent on the ultiplication ratio that is required for negative capacitance 144

163 generation (Fig 411) A oderate level of tuning ay be required on the load capacitance, C L, for coplete cancellation Z L Z IN =-kz L NIC C IN =-kc L NIC C L Fig 410 Concept of negative ipedance converter (NIC) Fig 411 Scheatic of the single-port negative ipedance generator Fig 41 shows the siplified equivalent electrical circuit for the single-port negative capacitance generator R in the electrical odel is the equivalent shunt resistance fro R and R 3 shown in the circuit The M n1 and M n devices are replaced with M 1 and M in the electrical odel, respectively 145

164 146 Fig 41 Electrical odel of the single-port negative capacitance generator Solving for C in, we have: where g 1 and g are the transconductance of M 1 and M devices, respectively This analysis shows that for g 1 g g, the input resistance, Z in, can be siplified to: ( ) L in g s R g C g R Z =, (411) () ( ) () ( ) () ( )? = = = = = = = = = x x in gs g s s x gs d g gs s gs x gs g i v Z v v v v v v g C s v v R v g v v g i v g R v ()() ( ) ( ) ()( ) ( ) () ( ) ( ) ( ) ( ) () () ( ) ( ) ( ) ( ) , , , series in in gs x gs gs x gs gs g R C g R R g C R g C s g R g C s g R Z v R g C s i v g R g C s v g R v v g R g C s v = + = = + = + + = + =

165 When g R 1 is sufficiently large, ie g R 1 >>1, the input ipedance can be further siplified to: Z in R 1 = + (41) R1 CL s g The real part of the input ipedance, 1/g, is considered the equivalent input resistance, R in, of the network Using equation (41), the equivalent negative capacitive can be derived as: ( ) R 1 C in = 1+ R 1g C ( L R R 3 )g R R 3 ( ) C L (41) It is clear fro equation (41) that the equivalent negative capacitance can be independently adjusted without changing the biasing condition of transistors 45 Case Studies Three tunable oscillators are designed and fabricated in 018μ CMOS process to deonstrate and copare the effect of tuning enhanceent techniques on the tuning range and phase-noise perforance of the lateral icroechanical oscillator All three TIA s use the sae core aplifier and biasing condition with the sae size varactors in series with the input to achieve the tuning The first TIA does not use any tuning enhanceent technique The second TIA uses use active inductor cancellation while the third TIA uses negative capacitance cancellation techniques to iprove the tuning range To have a fair coparison, all three TIA s are interfaced with a 47MHz AlN-on-Silicon icroechanical oscillator (R ~180Ω, Q unloaded ~1400, C p ~7pF) and the tuning range, output spectru and phase-noise perforance are onitored The resonator frequency response is shown in Fig

166 f 0 ~473MHz Qunloaded~1400 R~180Ω Fig 413 Response and SEM view of the 47MHZ AlN-on-Si resonator 451 TIA without Tuning Enhanceent A three-stage feedback tunable TIA is designed and fabricated in 018μ CMOS process The first stage is an inverter with shunt-shunt feedback and acts as the transipedance aplification stage The choice of inverter over CS topologies is due to the availability of larger gain The shunt-shunt feedback is realized with an NMOS transistor biased in triode region to provide gain tuning capability The nd and 3 rd stages are voltage aplifiers that boost the gain To lessen the effect of inter-stage critical nodes on the BW of the TIA, the last stage incorporates a local shunt-shunt feedback network to lower the input and output ipedance of this stage Together with the nd stage, the last two stages of the aplifier for a odified Cherry-Hooper The RC shunt-shunt feedback incorporated in the last stage is in the for a T network that can realize a left-hand 148

167 plane zero for pole cancellation The tuning network is coprised of two back-to-back MOS varactors that are placed in series with the input of the TIA This approach obviates the need for two independent tune signals and at the sae tie potentially lowers the iniu available tuning capacitance value (Fig 414) The TIA easures 45μ 45μ (Fig 415) and consues around 10W and is capable of providing iniu gain above 6dBΩ up to 1GHz with pf input/output capacitive load The gain can be tuned by ~1dB at the expense of saller BW The ipact of the tuning network on the transipedance gain can not be ignored Due to the lack of shunt-parasitic cancellation, the high-pass response due to the use of sall series varactors significantly lowers the gain This effect becoes ore pronounced as the varactor is tuned to the iniu capacitance in which case, the gain drops fro 78dBΩ to 6dBΩ (Fig 416) V DD M VBP M 4 VBP M 6 Iin V TUNE VCT R Z1 R Z Vout 50Ω Vbuffer C TUNE C TUNE M 8 M1 M 3 C Z M 5 M 7 Fig 414 Scheatic of the tunable TIA w/o shunt parasitic cancellation 149

168 Fig 415 Chip Micrograph of the TIA without shunt capacitive cancellation Fig 416 AC gain and phase of the tunable TIA w/o shunt parasitic cancellation 150

169 The TIA is interfaced with the 47MHz AlN-on-Si lateral icroechanical resonator specified earlier in this section The easured tuning range of the 47MHz icroechanical oscillator is around 64pp (Fig 417) This tuning range is in no way sufficient for teperature or process copensation Frequency [MHz] Vtune [V] Fig 417 Frequency vs voltage for the 47MHz oscillator w/o tuning enhanceent 45 TIA with Active Inductance Cancellation A three-stage feedback tunable TIA that uses active inductor for shunt parasitc cancellation is designed and fabricated in 018μ CMOS process The core aplifier is the sae as the one used for oscillator without tuning enhanceent Siilarly, two series back-to-back varactors that are placed at the input of the TIA play the role of tuning network The aforeentioned single-port single-transistor active inductor is added to the 151

170 input of the TIA for shunt parasitic cancellation The bias current of the active inductor is sourced by an NMOS transistor, M n, which is connected between the ground and the input of the TIA (Fig 418) Fig 418 Scheatic of the tunable TIA with active inductance cancellation The TIA easures 45μ 45μ (Fig 419), consues around 11W, and is capable of providing iniu gain above 66dBΩ up to 1GHz with pf input/output capacitive load The gain can be tuned by ~10dB at the expense of saller BW Although the ipact of the tuning network on the transipedance gain is reduced due to partial shunt parasitic cancellation, it is still considerable (>10dB) and cannot be ignored In this case, the transipedance gain drops fro 80dBΩ to around 66dBΩ when the tuning capacitance is varied fro its axiu to the iniu (Fig 40) The TIA is interfaced with the sae 47MHz AlN-on-Si lateral icroechanical resonator The easured tuning range of the 47MHz icroechanical oscillator is around 350pp (Fig 41) The tuning range, although ~55 larger than the oscillator 15

171 without shunt parasitic cancellation, but it is still not enough for ost teperature or process copensation applications Fig 419 Chip Micrograph of the TIA with active inductance cancellation Fig 40 AC gain and phase of the tunable TIA with active inductance cancellation 153

172 Frequency [MHz] VTUNE [V] Fig 41 Frequency vs voltage for the 47MHz oscillator with active inductor 453 TIA with Negative Capacitance Cancellation A three-stage feedback tunable TIA that uses negative capacitance for shunt parasitc cancellation is designed and fabricated in 018μ CMOS process The core aplifier is the sae as the one used for oscillator without tuning enhanceent Siilarly, two series back-to-back varactors that are placed at the input of the TIA play the role of tuning network The aforeentioned single-port negative capacitance generation block is added to the input of the TIA for shunt parasitic cancellation The load capacitance, C L, is ade tunable to allow for adjusting the negative capacitance value for best shunt parasitic cancellation result (Fig 4) 154

173 V DD VBP M M 4 VBP M 6 Iin R 3 V BP M n1 M n3 C TUNE V TUNE C TUNE VCT M 8 M 1 M 3 R Z1 C Z R Z Vout M 5 50Ω M 7 Vbuffer V BN M n4 R M n C L Negative Capacitor R 1 Core tunable TIA with varactors (tunable TIA w/o copensation) Fig 4 Scheatic of the tunable TIA with negative capacitor The TIA (with teperature copensation) easures 1300μ 45μ (Fig 43), consues around 114W, and is capable of providing gain > 7dBΩ up to 1GHz with pf input/output load The gain can be tuned by ~1dB at the expense of saller BW Although, the ipact of the tuning network on the transipedance gain is reduced due to partial shunt parasitic cancellation but it is still considerable (>14dB) and can not be ignored In this case, the transipedance gain drops fro 85dBΩ to around 7dBΩ when the tuning capacitance is varied fro its axiu to the iniu (Fig 44) The TIA is interfaced with the sae 47MHz AlN-on-Si lateral icroechanical resonator The easured tuning range of the 47MHz icroechanical oscillator is beyond 810pp (Fig 45) The tuning range is ~3 larger than the oscillator with active inductance cancellation and ore than 1 larger than the oscillator without shunt parasitic cancellation This tuning range is now beginning to approach 1000pp threshold that is necessary for fully-electronic teperature and/or process copensation in silicon icroechanical oscillators 155

174 Fig 43 Chip view of the TIA (and tep copensation) with negative capacitor Fig 44 AC gain and phase of the tunable TIA with negative capacitor The easured phase-noise of the 47MHz oscillator across the tuning range is shown in Fig 46 The phase-noise perforance is better than -8dBc/Hz at 1kHz offset and floor reaches below -147dBc/Hz for the best case The worse case phase-noise perforance across the tuning range is also shown in Fig 46 The tuning range is reduced when the 156

175 close-to-carrier (<10kHz) phase-noise degradation across the tuning range is kept within the 5dB ark of the best easured phase-noise profile The phase-noise is slightly worse than the oscillators with active inductance cancellation and without tuning enhanceent due to the higher noise associated with the negative capacitance generation circuitry With proper sizing of critical transistors, it is possible to reduce the flicker noise contribution of this block that has a direct ipact on the close-to-carrier phase-noise perforance of the oscillator Frequency [MHz] VTUNE [V] Fig 45 Frequency vs voltage for the 47MHz oscillator with negative capacitor 157

176 f 0 ~4739MHz P 0 ~db Span=100kHz Worst case Best case Fig 46 Phase-noise of the 47MHz oscillator with negative capacitor 454 Coparison of Tuning Enhanceent Techniques Coparison of these techniques based on the axiu tuning range achieved with 47MHz oscillator is fairly straightforward; the TIA with negative capacitance achieves axiu tuning range beyond 810pp that is 3 of that of the TIA with active inductor (~350pp) and ore than 1 of the 64pp tuning achieved in a TIA without tuning enhanceent (Fig 47) However, the phase-noise perforance gets affected when a shunt parasitic cancellation network is added The close-to-carrier phase-noise degradation is below 4dB for the worst case, ie oscillator with negative capacitance cancellation As such, the negative capacitance cancellation can be considered a viable technique to iprove the tuning range with inial phase-noise degradation 158

177 Frequency [MHz] Oscillator w/ negative capacitor 471 Oscillator w/ active inductor Oscillator w/o copensation VTUNE [V] Fig 47 Frequency vs the tune voltage for 47MHz oscillators 46 Conclusion In this chapter, different frequency tuning ethods for icroechanical oscillators are studied The chapter covered both the resonator-based and the electronic tuning techniques with ephasis on electronic tuning for lateral icroechanical oscillators Two popular ethods for frequency tuning, ie parallel and series tuning are discussed and their perforance in lateral icroechanical oscillators are copared The shortcoing of series tuning for lateral icroechanical oscillators with large shunt parasitic capacitance are identified and supported with detailed theoretical analysis of series tuning in such oscillators Finally, tuning enhanceent ethods based on shunt 159

178 parasitic capacitance cancellations are introduced and supported with easured data fro case studies to deonstrate the viability of each approach for high-frequency lateral icroechanical oscillators 160

179 CHAPTER 5: Teperature Copensation for MEMS Oscillators Frequency reference oscillators require very-high short-ter and long-ter accuracy to eet the requireent for odern radio transceivers While the short-ter accuracy can be addressed by reducing the phase-noise/jitter and suppressing the unwanted haronics, the long-ter accuracy calls for a coprehensive teperature copensation solution [1] There are two ajor approaches for teperature copensation in icroechanical oscillators aterial-based [30], [44], [75] and electronic [], [6] teperature copensation This chapter explores aterial and electronic teperature copensation techniques for lateral icroechanical oscillators The chapter starts with introduction of aterial and electronic teperature copensation; the two ost widely used approaches for teperature copensation Then, it builds up on this foundation by introducing the openloop electronic teperature copensation approach that can be adapted to a cobination of these approaches After that, it first goes into the syste-level and then circuit-level ipleentation of open-loop electronic teperature copensation The last portion of this chapter is dedicated to exaples of icroechanical oscillators that benefit fro aterial and electronic teperature copensation 51 Introduction Teperature copensation is the key to iprove the long-ter stability of reference oscillators Material and electronic copensation are the two ain candidates for lateral icroechanical oscillators Material copensation involves the use of a aterial in the resonator design with opposite behavior with teperature This approach is inherently 161

180 low power but it coes at the expense of Q reduction that is certainly not welcoe for ost low phase-noise applications Electronic copensation, does not affect the resonator perforance but it requires extra power beyond the sustaining aplifier and require accurate teperature sensors In fact, the accuracy of the teperature copensation circuit is no better than that of the teperature sensors used in the copensation block Another coplicating factor is the large drift ( TCF >5pp/ºC for silicon) of the high-q icroechanical oscillators This large TCF ay prevent the icroechanical oscillator fro achieving the stated total drift over a wide teperature range using only one of these copensation ethods As such, cobination of aterial and electronic copensation ay becoe necessary The goal of this study is first to explore the liitation of both aterial and electronic copensation schees to contain the total drift to less than ±50pp across the industrial teperature range of -40ºC to 85ºC, and then propose alternative to deliver such accuracy 5 Teperature Copensation Methods for Microechanical Oscillators Material and electronic teperature copensation ethods are widely used in lateral icroechanical oscillators The accuracy and ipact of each ethod should be independently studied to deterine its viability for high frequency icroechanical oscillator applications 51 Material Copensation In this approach, the frequency drift is copensated for by including a aterial in the icroechanical resonator structure that exhibit an opposite frequency vs teperature behavior than the rest of the aterials used in the resonator stack Usually, the resonator 16

181 is ade of aterials with large negative TCF such as silicon and AlN Hence, the copensation aterial should exhibit positive TCF A faous candidate is silicon dioxide (SiO ) with TCF around 3 larger (~80pp/ºC) [30] than that of the silicon A Carefully engineered silicon oxide to silicon ratio ensures near-zero TCF across a wide teperature range The silicon oxide layer is ebedded in the resonator stack (Fig 51) Silicon Oxide Layer Fig 51 Resonator structure with ebedded silicon oxide layer for TCF reduction The ain disadvantage of this teperature copensation ethod is that ost aterials with large positive TCF exhibit significantly higher acoustic loss properties than the single-crystal silicon This extra loss results in lower Q that is undesirable for low phasenoise reference oscillator applications [30] One solution is to use another low acoustic loss aterial with inherently lower TCF such as Nanocrystalline Diaond (NCD) in the resonator structure to reduce the thickness of silicon oxide fil [48] Another iportant advantage of NCD fil is the Q iproveent due to inherently higher fq product [76] 5 Electronic Copensation There are two ajor ethods for electronic teperature copensation: closed-loop and open-loop ethods In closed-loop ethod, the designers rely on the output of the PLL to 163

182 copensate for frequency drift with teperature This can be done either by an analog charge-pup PLL that uses a very accurate teperature sensing unit and a phasefrequency detector with known (and inially varying) characteristic across the teperature range or through a fractional-n frequency synthesizer whose output frequency is deterined with the help of a look-up table The closed-loop approach is ore accurate but at the sae tie, consues ore power In an open-loop syste, the copensation is achieved through accurate sensing of the teperature variation and using this inforation to generate a signal that is applied to the teperature copensation circuitry Although a closed-loop syste is potentially ore accurate, it is coplicated, requires large IC area and consues large power On the other hand, using an open-loop syste with a very accurate teperature sensing unit and a custo analog function generator that can be used to accurately odel the frequency drift of the oscillator with variation in teperature can provide up to 100 iproveent over uncopensated across -40ºC to 85ºC teperature range [6] The accuracy can be further iproved to ±5pp (that is coparable to TCXO s) with a ore accurate electronic and/or cobination of electronic and aterial copensation techniques Open-loop electronic teperature copensation takes advantage of electronic [47] and/or resonator-based [6] frequency tuning to accurately adjust the oscillation frequency in the presence of large variation in the environent teperature The electronic teperature copensation block is coprised of three sub-units with tight accuracy specs: teperature sensing unit, control signal generation unit, and frequency tuning unit The last block is usually ebedded in the sustaining aplifier and is extensively covered in 164

183 chapter 4 of this dissertation The teperature sensors are usually in the for of bandgap and proportional-to-absolute-teperature (PTAT) circuits The design of control signal generation unit is dependent on the frequency vs teperature behavior of the oscillator as well as the frequency tuning profile and can be ore coplicated [6] Fig 5 shows an exaple of electronic teperature copensation block used for 103MHz SiBAR oscillator [6] Fig 5 Block diagra of teperature-copensated SiBAR oscillator [6] The ain disadvantages of the open-loop electronic copensation technique are the tight accuracy requireents for each of these three sub-blocks and the power consuption While the power consuption can be lowered with a careful design [77], the only reliable 165

184 ethod to itigate the accuracy concern is to use a closed-loop PLL-based electronic teperature copensation approach [78] 53 Ipleentation of Open-Loop Electronic Teperature Copensation To better perfor the design and optiization required for accurate open-loop electronic teperature copensation blocks, it is vital to have a syste-level understanding of the block before oving to the detailed circuit-level ipleentation of each sub-block 531 Syste-Level Ipleentation A general block diagra for the open-loop teperature copensation bock is shown in Fig 53 The frequency tuning unit is ebedded with the TIA and is not shown here Fig 53 Block diagra of the open-loop electronic teperature copensation The teperature sensing unit includes the bandgap and PTAT teperature sensors The teperature-insensitive output voltage of the bandgap reference is copared against the output of the PTAT circuit that linearly changes with teperature The PTAT is used to generate an output signal (voltage or current) whose agnitude changes linearly with variation in absolute teperature The coparison and scaling are done with a low-offset difference aplifier with appropriate resistive feedback network The design of control signal generation unit is dependent on the frequency vs teperature drift of the oscillator Usually the frequency vs teperature behavior for 166

185 icroechanical oscillators can be approxiated with a linear function, however, the frequency variation vs tuning voltage for ost tunable icroechanical oscillators is nonlinear The resonator-based tuning techniques such as the electrostatic tuning rely on the change in the polarization voltage, V p, of the resonator to induce frequency shift Since the resonance frequency is proportional with V p, the frequency vs tuning voltage is nonlinear For electronic tuning, the variation in the effective capacitance of the varactor with the tune voltage is a function of (V tune ) -n This property cobined with the nonlinear relationship between the oscillation frequency and varactor capacitance, ie 1/ C tune, akes the linear approxiation obsolete To have a proper approxiation of these two curves, it is necessary to express these function in Taylor series For applications with oderate accuracy (<±50pp), considering the first two ters (first and second-order ters) is sufficient For this reason, an analog parabolic function generator is considered To convert the signal back to linear doain, the inverse of this function, ie square root generator [79] ust be included in the control signal generation unit Since the input to the square root generator is current and the output of the teperature sensing unit is a voltage, linear V-to-I conversion for DC signals is necessary [47] This can be done either by a transconductance aplifier [] or by a linear V-to-I converter A linear trannsconductance aplifier whose output is proportional to the g of the transistors will be prone to gain error due to the variation in process and teperature This error cobined with the inherent offset of the aplifier ay liit the perforance of the teperature copensation block A novel linear V-to-I converter such as the one shown 167

186 in [47], on the other hand, functions ore soothly, has larger dynaic range and exhibits less non-idealities The output of the control signal generation unit is then scaled and fed to the tuning network to adjust the oscillation frequency The frequency control unit is either part of the sustaining aplifier (for electronic tuning) or provides a signal to the resonator for frequency tuning 53 Circuit-Level Ipleentation The teperature sensing unit consists of three sub-blocks: bandgap, PTAT, and difference aplifier The bandgap reference is based on a V BE - V BE architecture with extra cascade devices and error aplifier to reduce the bandgap curvature [] (Fig 54) Siilar topology with different resistance ratio is used to realize the PTAT reference (Fig 54) Both circuits are optiized for the best perforance fro -40ºC to 85ºC The siulated and easured outputs of the bandgap and PTAT references are in good agreeent (Fig 55 and 56) The PTAT slope is around 17V/ºC The teperature coefficient of the bandgap cell is around 7pp/ºC The difference aplifier is a siple two-stage differential-input single-ended output operational transconductance aplifier (OTA) with iller copensation The overdrive voltages on input MOS transistors are axiized to reduce the input offset due to the isatch in the transistors (Fig 57) 168

187 Fig 54 Scheatic of the bandgap and PTAT reference generators Siulated Measured 114 Voltage [V] Teperature [C] Fig 55 Siulated and easured output of the bandgap reference 169

188 Siulated Measured 07 Voltage [V] Teperature [C] Fig 56 Siulated and easured output of the PTAT reference V DD CZ Vout Vn Vp VBN VBN Fig 57 Scheatic of the two-stage OTA with iller copensation 170

189 The square-root generator uses an aplifier in shunt feedback configuration whose input is connected to the source of a diode-connected device that passed the reference current The output voltage of the circuit is proportional to the square-root of the reference current reference current that passes through M 1 (Fig 58) The detailed design of square-root generator is given in [79] and won t be repeated here Fig 58 Block diagra of the square-root generator [] The design of linear V-to-I converter is critical since its perforance is directly related to the accuracy of the square-root generator The scheatic of the linear I-to-V converter is shown in Fig 59 Neglecting the channel-length odulation effect in M 1 transistor, the current that passes through M 1 and M is proportional to square of V in This current forces a certain V GS across the M device which is proportional to the square root of this current and consequently, linearly dependent to the input voltage Therefore, the output current, I out, generated by dropping this voltage across the resistor is linearly proportional to the input voltage, V in The input to output relationship can be approxiated by: 171

190 W Kn 1 L M 1 I ( ) out VTH, M 1 + Vin VTH, M, (51) R W K p L M where V TH,M1 and V TH,M are the threshold voltages of M 1 and M devices, respectively The output of the linear V-to-I converter is shown in Fig 510 The deviation fro linear line is very sall deonstrating the high accuracy of this block The ain source of error in this block is the channel-length odulation effect This error can be reduced by proper sizing of M 1 and M transistors Finally, the output of the square-root generator when connected to the linear V-to-I converter is shown in Fig 511 The sources of error in this block include the nonlinearity due to the body effect of M 1 transistor and gain error in the aplifier both of which can be suppressed by design optiization DD R 1 M M 3 in M 1 Fig 59 Scheatic of the linear V-to-I converter 17

191 Output Current [ua] Linear V-to-I Output Linear Fit Input Voltage [V] Fig 510 Output current of the linear V-to-I converter Output Voltage [V] Input Voltage [V] Fig 511 Output of the square root generator and linear V-to-I converter 173

192 533 Sources of Error There are four ajor sources of error: Bandgap and PTAT non-idealities: Usually appear as bandgap and PTAT curvature Aplifier offset: Inaccuracy of difference and scaling operations Square-root generator error: Error in approxiating a parabolic response Linear V-to-I converter error: Indirectly affect the parabolic response approxiation Aong these four error sources, the last two are ore iportant and should be iniized by careful optiization for high perforance applications The bandgap and PTAT errors can be easily reduced by using low-curvature circuits 54 Case Studies In this section, two teperature-copensated high-frequency lateral icroechanical oscillators are presented: the first oscillator uses a 441MHz AlN-on-Si resonator whose TCF brought near-zero by a thin silicon oxide fil (aterial copensation); the second oscillator is based on a low-tcf 47MHz resonator with electronic teperature copensation 541 Teperature-Copensated 441MHz AlN-on-Si Oscillator A 018μ three-stage feedback tunable TIA siilar to the one reported in [7] is interfaced with a 441MHz teperature-copensated AlN-on-Si icroechanical resonator The resonator is fabricated on a ~15μ-thick CMOS-grade silicon substrate and uses a thin (~07μ) silicon oxide layer to reduce the TCF of the resonator to ~1pp/ºC in -40ºC to 85ºC Due to the use of lossy silicon oxide layer, the unloaded Q (Q unloaded ) of the resonator is degraded to ~1,100 with otional resistance close to 500Ω 174

193 (Fig 51) In addition, the frequency is substantially shifted down due to the lower acoustic velocity in silicon oxide f MHz R 530Ω Q unloaded 1,100 Fig 51 Response of the teperature-copensated 441MHz AlN-on-Si resonator The 441MHz AlN-on-Si icroechanical resonator is interfaced with the three-stage tunable TIA to sustain the oscillation Then, the frequency drift of the oscillator across the -40ºC to 85ºC teperature range is easured under the vacuu The operation under the vacuu eliinates the potential inaccuracies in the easureent due to the environents such as huidity The results shows less than 140pp total drift in -40ºC to 85ºC teperature range that is only ore than uncopensated quartz crystal oscillators (Fig 513) 175

194 Frequency (MHz) Total drift<140pp Teperature (C) Series1 Poly (Series1) y = -1E-05x x Fig 513 Frequency drift of the 441MHz icroechanical oscillator The easured phase-noise perforance of the 441MHz AlN-on-Si icroechanical oscillator resonator is shown in Fig 514 The close-to-carrier phase-noise is around - 79dBc/Hz at 1kHz offset The phase-noise floor reaches -15dBc/Hz The close-to-carrier perforance is affected by low Q of the resonator that is partly due to the use of silicon oxide in the resonator stack The close-to-carrier phase-noise degradation is the inherent proble for icroechanical reference oscillators that use aterial teperature copensation and reains the ain obstacle toward their successful coercialization This proble can be addressed by using aterials with lower acoustic loss for copensation or placing the lossy silicon oxide layer as far away fro the electrodes as possible One way to realize such as resonator is to use the relatively-thin (<μ) buried silicon oxide layer (BOX) available in ost silicon-on-insulator (SOI) starting substrates [44] Another proble is large spurs in far-fro-carrier perforance that is due to poor power handling of the 176

195 icroechanical resonator This phenoenon can be partly explained by the low stiffness of the silicon oxide layer Fig 514 Measured phase-noise of the 441MHz icroechanical oscillator 54 Electronically Teperature-Copensated 47MHz AlN-on-Si Oscillator The 47MHz AlN-on-Si icroechanical resonator uses a very thin silicon oxide layer to lower the native TCF of the resonator to -10pp/ºC Then an open-loop teperature copensation circuit is used in cobination with a tunable oscillator to deliver a subpp/ºc 47MHz icroechanical reference oscillator [47] The design approach and characterization data of the sustaining aplifier, electronic frequency tuning network and negative capacitance cancellation circuit for tuning enhanceent are readily provided in chapter 4 of this dissertation 177

196 Fig 515 shows the block diagra of the teperature-copensated oscillator The fully on-chip W teperature copensation circuit burns W and includes bandgap and PTAT references for teperature sensing, low-offset aplifiers for difference and scaling, and square-root generation circuitry [79] A linear DC voltage-to-current converter is also added for better accuracy The frequency tuning and phase-noise results are reported in chapter 4 Moreover, the design and characterization data for the building blocks of the teperature copensation block are provided earlier in this chapter V TUNE Ap Square Root Generator Linear V-I Converter Ap PTAT Bandgap Teperature Copensation Circuitry TIA with Tunable Gain Voltage Aplifier 50Ω Buffer R F C TUNE C TUNE TIA Ap 50Ω Buffer L C R C L NIC C p Resonator Model C p Shunt Capacitance Cancellation Fig 515 Diagra of the electronically teperature-copensated oscillator 178

197 Using the open-loop electronic copensation technique, the teperature drift of the 47MHz oscillator is reduced fro 780pp to 70pp in -10ºC to 70ºC range (Fig 516) Reoving the square-root generator and linear DC V-to-I converter increases the drift to ore than 340pp that shows the iportance of this nonlinear copensation technique This result shows over 34 iproveent fro the uncopensated oscillator and is coparable with a typical uncopensated quartz crystal oscillator Frequency [MHz] Uncopensated 475 Linear Copensation Parabolic Copensation Teperature [C] Fig 516 Variation in oscillation frequency vs teperature in -10ºC to 70ºC range 55 Conclusion Teperature copensation is an integral part of any icroechanical reference oscillator This section introduced, explained the design ethodology, and provided 179

198 exaples of, two ajor teperature copensation techniques for icroechanical oscillators: aterial and electronic teperature copensation Material copensation is a low-power approach but it negatively affects the Q and power handling of the resonator, both of which detriental for low phase-noise icroechanical oscillators Electronic copensation, on the other hand, inially affects the oscillator perforance but it requires coplicated electronics with potentially high power consuption 180

199 CHAPTER 6: Phase-Noise in Series-RLC Lateral MEMS Oscillators Lateral icroechanical oscillators are gaining currency as the frequency references for odern radio transceivers due to their higher frequency of operation, larger tuning, saller fro-factor and potential integration with IC [6], [47], [66] However, the shortter stability of these oscillators, which is the single ost iportant perforance criterion in reference oscillators, reains inferior to conventional quartz crystal oscillators, even though theoretical studies [13], [80] suggest otherwise Therefore, accurate prediction of short-ter stability is necessary The short-ter stability of a reference oscillator is typically expressed in the for of jitter or phase-noise [7] Work pertaining to odeling the phase-noise of icroechanical oscillators has largely focused on fitting the classical linear odels such as Leeson s [81] to the observed phase noise characteristic [8], [83] While the classical phase noise theories [81], [84], which focus on an LTI approach, provide reasonable phase-noise estiates for crystal type oscillators, their track record in accurately predicting the phasenoise perforance of series-resonant lateral icroechanical oscillators is not proising Of particular iportance are the so-called epirical paraeters in the classical theory whose values significantly differ for oscillators that are share the sae sustaining aplifier but use siilar resonators (Q and loss) with different parasitic This requires careful consideration of the resonator parasitic ipedances on the phase-noise of the icroechanical oscillator 181

200 This chapter deals with the study of phase-noise in series-resonant lateral icroechanical oscillators focusing on both capacitive and piezoelectric oscillators First, several well-known phase-noise odels are introduced and their advantages are discussed Then, before diving into the details of analytical odeling, several sources of phase-noise in icroechanical oscillators are briefly entioned After that, the discussion continues with the application of classical Leeson s theory to icroechanical oscillators The contribution of first- and second-order parasitics on the phase-noise perforance of lateral icroechanical oscillators is studied This leads to an analytical expression for phase-noise of high frequency lateral icroechanical oscillators in presence of the finite otional resistance, shunt parasitic, and aplifier loading Finally, exaples of high frequency capacitive and piezoelectric icroechanical oscillators are provided to validate the derived analytical odel 61 Introduction Non-idealities in the oscillator whether fro the frequency selective tank such as finite Q and loss or fro aplifier such as electronic noise cause widening in the oscillation spectru The degree to which the oscillation power is speared across the frequency spectru is deterined by the phase-noise of the oscillator The relative phase-noise is defined as the average power carried in 1 Hz of the oscillation spectru when noralized to the carrier power, P C (Fig 61): L( df ) P 10log P 1Hz df =, (61) C where the L(df) is the relative phase-noise and P 1Hz is the average power carried in 1Hz of the oscillation spectru at the frequency df offset fro the oscillation frequency 18

201 P C 1Hz f 0 f 0 +df f Fig 61 Concept of phase-noise in oscillators The phase-noise of an oscillator is another way of expressing its frequency fluctuations [84] Stability easureents using frequency coparators give the spectral density of frequency fluctuations: f ( f ) = Δf SΔ, (6) where S f (f ) is spectral density of the frequency fluctuations, f rs The phase-noise of the oscillator at the frequency f offset fro the carrier frequency f 0 is expressed by: L ( f ) rs ( f ) S = (63) Δf f The phase-noise is usually easured and expressed in decibels rather than absolute value: Δf ( ) 10log rs L f = 10 (64) f 183

202 In a feedback oscillator, the echanical and electronic noise (both theral and flicker) are aliased around the oscillator frequency and are filtered by the frequency selective tank This phenoenon creates an oscillator phase-noise profile with different regions Fig 6 shows the typical phase-noise spectru of a feedback oscillator with coon electronic (and possibly echanical) noise sources [84] There are 5 different regions with potentially different behavior Soe of these regions ay be asked by others for oscillators with high-q resonating tank Fig 6 Phase-noise spectru of a typical feedback oscillator The first region is the 1/f 4 (f -4 ) region which is referred to as rando walk frequency odulation (FM) This region appears very close to the carrier and is typically due to the rando variation in the frequency of the tank For icroechanical oscillators, this phenoenon can be partly explained by the excessive low-frequency noise originating fro the vibrating echanical structure Other contributing factors are resonator 184

203 nonlinearity (including the nonlinearity of the transducer and liited power handling capability), particle adsorption and desorption, and the Brownian noise [6], [83] The 1/f 3 (f -3 ) region, called flicker FM, appears in close-to-carrier region and is the result of up-conversion of flicker noise (1/f noise) of the aplifier after it is aliased into the oscillation spectru For CMOS aplifiers with large flicker noise corner, the 1/f 3 region extends well into several tens of kilohertz The 1/f (f - ) region, called white FM or rando walk phase, is due to the up-conversion of theral noise (ostly fro the aplifier) whose power spectral density (PSD) reains constant with frequency For aplifiers with sall flicker noise corner (such as bipolar aplifiers) or oscillators with low-q tank (such as LC oscillators) this region is extended to fro both ends into the close-to-carrier and far-fro-carrier regions The 1/f (f -1 ) region, called flicker phase, is transition region between the theral noise and the noise floor of the oscillator For oscillators that use high-q tanks, the 1/f region is doinant and bridges the 1/f 3 and noise floor regions The noise floor, f 0 region, is liited by the noise of the electronics (including the buffer and other control circuits) that are used in the oscillator 6 Analytical Models for Phase-Noise Several odels have been used by IC designers to predict the phase-noise perforance of oscillators These analytical odels can be categorized into two general categories: linear and nonlinear odels This section briefly introduces these well-known odels 185

204 61 Classical Linear Tie-Invariant (LTI) Model (Leeson s Model) In the LTI approach, the noise generated fro the aplifier (and possibly the resonator) is passed through the feedback loop This noise (the aplitude and phase) is odulated to the carrier frequency Assuing an aplifier with noise factor F and flicker noise corner f c, the PSD of the noise at frequency f offset fro the carrier frequency is: f S 1 +, (65) n ( ) = c f ktf f where k is the Boltzan s constant, T is the teperature in Kelvin Assuing that half of this noise spectru contributes to the phase noise and the other half to the aplitude, the phase-noise in db can be expressed as: ktf f L , (66) ( ) = c f log Ps f where P s is the power of the carrier signal For closed-loop systes with feedback factor other than unity, the phase-noise expression is ore coplicated Feedback oscillators such as the one shown in Fig 63 not only odulate the noise of each block but also filter the noise by passing it through the frequency selective tank with a very narrowband frequency response The PSD of the output noise can be expressed by:, out ( f) Sθ, in( f) Gnoise( f) Sθ =, (67) where S θ,in (f ), S θ,out (f ) are the PSD spectra of input and output phase-noise, respectively G noise (f ) is the closed-loop transfer function of the feedback syste which depends on the frequency response of the resonating tank Since the PSD of the input phase-noise is readily available fro (66), the proble is reduced to finding the closedloop transfer function of the feedback oscillator 186

205 Θ noise,in PM Aplifier Θ noise,out P s P s Resonator Fig 63 Linear odel for the phase-noise analysis of feedback oscillator 6 Linear Tie-Variant (LTV) Model (Hajiiri s Model) Since the oscillators are essentially tie-varying, the tie-variant approach sees to be a ore appropriate approach in odeling the phase-noise With this in ind, Hajiiri proposed a novel LTV phase-noise odel for feedback oscillators [85] The linear assuption for noise despite the obvious nonlinear large-signal behavior of the feedback syste is justified when the noise power is uch saller than the carrier power The heart of this theory is based on the ipulse sensitivity function (ISF) Tie-varying perturbation results in tie-varying phase fluctuations The unit ipulse response for excess phase of an oscillator can be expressed [85] as: h φ ( t τ ) ( πf 0t) u ( τ ) Γ, = t, (68) q where q ax is the axiu charge displaceent on the node, u(t) is the unit step function, and Γ(x) is the ipulse sensitivity function The ISF is a diensionless, frequency- and aplitude-independent periodic function with period equal to π This function describes how uch phase shift results fro applying a unit ipulse at tie t=τ and is a function of the oscillation wavefor Skipping the details of the Fourier series analysis, one can show that the excess phase generated fro ISF can be expressed by: ax 187

206 φ () t ( Δωt) In cn sin, (69) q Δω ax where I n and c n are the current aplitude and coefficient for the n-th ter in the Fourier series To better understand the ipact of excess phase on the oscillation spectru, it is beneficial to understand the phase to voltage transforation echanis in the oscillator Fig 64 shows a general block diagra of the LTV phase-noise odel showing the phase-to-voltage converter Note that the nonlinearities of the oscillator (both aplifier and icroechanical resonator) affect the ISF wavefor and the oscillation wavefor Fig 64 General block diagra of the LTV phase-noise odel By coputing the PSD of the oscillation wavefor, the phase-noise can be obtained The excess phase generated by an injected current at nω 0 + ω results in double sideband power relative to carrier The single sideband PSD is given by: P 4 out Incn = (610) Ps qaxδω Finally, when considering the contribution fro theral noise, a closed-for solution for the oscillator phase-noise in db can be found: 188

207 L ( Δω) = 10log 10 in 4q n= ax cn 0 (611) 3 Δω Using Parseval s theore, the expression for the phase-noise is siplified to: ( ) Γrs in L Δω = 10log 10, (61) 3 qax qax Δω where Γ rs is the RMS value of the ISF If the contributions fro flicker noise sources are considered, the overall close-to-carrier phase-noise perforance can be approxiated: ( ) Γrs in + c0 in ωc L Δω = 10log 10, (613) 3 3 qax qax Δω qax 4 Δω Δω where ω c is the flicker noise corner frequency 63 Nonlinear Tie-Invariant (NLTI) Model (Saori s Model) This odel is based on a ore practical nonlinear approach in odeling oscillators [87] After all, the large-signal operation of an aplifier is synonyous to nonlinearity The study of the NLTI odel starts with finding the haronic transfer function of oscillator with a pre-defined frequency selective tank Then the single side-band PSD of the output noise voltage can be calculated to arrive at the final expression for the phase-noise of the oscillator The phase-noise of the oscillator in 1/f region can be approxiated by: kt ω0 1 L ( Δω ) = ( 1+ F ), (614) V C Q Δ 0 ω where V 0 is the oscillation aplitude, Q is the quality factor of the resonating tank, and F is the nonlinear noise factor Continuing with the nonlinear analysis of the output signal, 189

208 V(t), it is possible to have a ore accurate expression for F based on other known paraeters in the circuit 63 Sources of Phase-Noise in Microechanical Oscillators The noise sources for icroechanical oscillators are categorized into two groups: electronic and echanical noise sources Electronic noise sources are well-known They include theral and flicker noise of the active and passive devices used in the oscillation block This includes the noise contribution of circuits that are outside the feedback loop such as ALC [8] The noise fro control block such as teperature/process copensation circuit and tuning control signal supplied by the PLL indirectly contribute to the overall phase-noise; the noise fro these blocks is odulated by the frequency vs tuning transfer function of tuning circuit before showing up in the phase-noise of the icroechanical oscillator The ain source of echanical noise is the icroechanical resonator The echanical noise that is usually low frequency in the resonator originates fro two sources: first, the nonlinearity of the icroechanical resonator The resonator is driven into nonlinearity due to its liited power handling capability and nonlinearity of the transducer [83] The power handling is ostly liited by the nonlinearity echaniss in the resonator In a linear ass-spring syste the spring coefficient is a constant where as in a nonlinear syste, the spring coefficient does not linearly change with the displaceent [30] A nonlinear spring coefficient will cause larger haronics of the natural resonance 190

209 frequency, ω 0, to appear in the output Consequently, the resonance frequency is dependent on the vibration aplitude [88] The nonlinearity of the electroechanical transducers whether capacitive [6] or piezoelectric [30] contributes to the noise of the icroechanical resonator In capacitive resonators, the noise aliasing fro the polarization voltage further deteriorates the closeto-carrier phase-noise perforance The other ajor noise source in a icroechanical resonator is due to rando low frequency vibrations that is possibly caused by particle adsorption and desorption 64 LTI Phase-Noise Model for Series-Resonant Lateral MEMS Oscillators To be able to iprove the phase-noise perforance of the icroechanical oscillators, it is necessary to have a good understanding of the phase-noise echanis and derive analytical odels that are in good agreeent with easureent data This odeling work will be considered a significant step forward toward creating an advanced systeatic design ethodology for the design and optiization of high frequency icroechanical oscillators While the LTI classical phase noise theory [84] provides reasonable phase noise estiates for crystal type oscillators, the presence of resonator parasitics reduces its value as coprehensive and accurate analytical phase-noise odel for icroechanical oscillators The proble is ore severe for classical phase-noise theories such a Leeson s [81] that require curve fitting to obtain the epirical paraeters Although Hajiiri s 191

210 odel [85], [86] offers an IC designer a uch-needed insight into the factors affecting epirical paraeters by providing a ore realistic LTV approach, the ere coplexity of this approach diinishes its prospect as the coprehensive oscillator phase-noise theory The difficulty in finding the relationship between the ISF and nonlinearity echanis of the resonator adds to this coplexity for icroechanical oscillators The sae arguent can be ade for NLTI approach where the ipact of nonlinearity odeling is ore pronounced on the accuracy of the phase-noise odel In this study, we focus on the LTI approach that is the siplest odel aong the ones discussed in section 6 The inefficiency of the LTI approach including its poor accuracy is copensated by odifying the odel to include the effect of the resonator and aplifier parasitic ipedances 641 LTI Model for Oscillator with Ideal Lateral MEMS Resonator As described earlier, the LTI theory predicts that the PSD of the output noise of a feedback oscillator is equal to PSD of the input noise ultiplied by the closed-loop gain of the oscillator Considering ajor electronic noise sources of an aplifier, ie theral and flicker noise, the PSD of the input noise is given by (65) Finding the transfer function of the icroechanical resonator which acts as the frequency selective tank and expressing it in ters of known paraeters such as Q and R, is the precursor to deterining the closed-loop gain of the oscillator The resonator transfer function can be written in ters of the Q of the resonator [84]: H 1 =, (615) f 1+ j Q f0 ( f ) 19

211 where f and f 0 are the offset and career frequency, respectively Once the resonator transfer function is available, the closed-loop transfer function of feedback syste can be easily found: ( f ) 1 f0 1+ f Q Gnoise = (616) Substituting (616) in (67) and assuing half of the noise spectru is odulated as phase-noise, the output phase-noise can be derived as: L ktf f = + c 1 f0 10log (617) Ps f f Q ( f ) Note that the equation (617) does not predict the ipact of the echanical noise of the phase-noise perforance of the icroechanical oscillator Fro this analysis, the ajor ipact of the icroechanical resonator on the oscillator phase-noise perforance coes only through the Q; the higher the Q of the resonator, the better the close-to-carrier phase-noise perforance 64 LTI Approxiation of the 1 st -Order Parasitic Effects on the Phase-Noise The aforeentioned analysis is only valid for oscillators ade with ideal aplifier and icroechanical resonators In reality, however, both of these blocks have considerable parasitics associated with the At the beginning, we consider the first-order parasitic effects on the phase-noise perforance Let s assue a non-ideal aplifier with input resistance, R in, and output resistance, R out, is placed in shunt feedback with a seriesresonant icroechanical resonator with otional resistance, R, and unloaded Q, Q res, to ake an oscillator (Fig 65) The effect of these aplifier and resonator parasitic 193

212 ipedances can be considered in the for of Q loading The resonator transfer function should be odified to account for loss that is odeled by the otional resistance: H 1 = (618) f R 1 + j Q f0 ( f ) Fig 65 Equivalent odel with 1 st -order parasitics for series-resonant oscillator Since the icroechanical resonator is odeled as a series RLC tank, a ore appropriate transfer function would be the ratio between the output current to the input voltage to the resonator, R tank : R f ( f ) = R 1+ j Q k (619) f0 tan Using equation (619), the loop transfer function, G noise, can be expressed as: G noise ( f ) v ( f ) ( f ) out F = =, (60) i R in F 1 R in + R R out + R tan k ( f ) 194

213 where R F is the transipedance gain of the TIA Using the closed-loop transfer function and considering the effect of aplifier loading on the resonator, the phase-noise of the icroechanical oscillator can be calculated: ktf f ( ) = + c 1 f0 L f 10log , (61) Ps f f QL where Q L is the loaded Q of the resonator and is given by: Q L = R Q R + R + R (6) in out Equation (6) clearly shows the Q reduction due to the finite input and output resistance of the TIA 643 LTI Approxiation of the nd -Order Parasitic Effects on the Phase-Noise While considering the first-order parasitic ipedances of the TIA and icroechanical resonator certainly iproves the accuracy of the LTI phase-noise odel, the predicted phase-noise perforance of high frequency icroechanical oscillators reains significantly underestiated when copared with the easureent The ost iportant reason behind this discrepancy is second-order parasitic effects fro both the TIA and icroechanical oscillator These parasitic effects include shunt and feedthrough parasitic capacitances of the icroechanical resonator in addition to the input and output reactance of the TIA Since the feedthrough capacitance of lateral icroechanical resonators is sall (<10fF), it can be safely ignored in this analysis Fig 66 shows the equivalent circuit for phase-noise calculation when both first-order and second-order parasitic ipedances are considered Due to the fact that the operating 195

214 frequency is usually significantly lower than the f T of the IC technology in the specific biasing situation, the input and output ipedances of the TIA are odeled as an RC network rather than an RLC Siilar to analysis given in section 64, the first step is to find the closed-loop transfer function of the feedback syste The closed-loop gain of the feedback syste is then used to find the PSD of the output noise and consequently the phase-noise of the oscillator Cout Cin Iin Rin Vout Rout AZ=IinRF R L C C0 C0 Fig 66 Equivalent odel with nd -order parasitics for series-resonant oscillator 196

215 Solving the network of Fig 66 for v out /i in, the closed-loop transfer function of the feedback oscillator is obtained: i v in out = i noise = R i F + Z in out vout + Z eq Z Z out in = R = R in out 1 C s 1 C s in out v i out in Zout + Zeq = RF (63) Z + Z R out eq F Z eq = Z in s 1 Rtan k C0 s + 1 C s 0 where R tank is the transfer function of icroechanical resonator Equation (63) can be siplified if input and output capacitance of the TIA, C in and C out, are assued to be uch saller C 0 This is a valid assuption as the ever-shrinking device feature size in advanced CMOS processes help reduce the parasitic capacitance of the MOS devices which are the ajor contributor to the input and output capacitance of the TIA C in of the TIA appear in parallel with C 0 and can be easily absorbed into C 0 Siilarly, the equivalent capacitance at the output node can be approxiated by the uch-larger C 0 of the icroechanical resonator: C C in out << C 0 << C C 0 in C + C out 0 + C C, Z 0 0 in C, Z 0 R out in R out (64) With this assuption, the Z eq is reduced to: ( jω) Rtan k ( 1+ j Rin C0 ω) + Rin ( 1+ j R C ω) + ( 1+ j R C ω) 1 Zeq = (65) j R C ω tan k We can now find the closed-loop transfer function, G noise : 0 in 0 in 0 197

216 G noise ( jω) v = i out in = R F R tan k R ( ) ( ) ( ) tan k 1+ jrout C0 ω + Rin + Rout 1+ jrout C0 ω + Rin + Rout RF 1+ j Rtan k C0ω (66) Z eq and G noise can be further siplified for TIAs with large BW that are natural choice to ensure inial extra phase-shift due to presence of the sustaining aplifier in the oscillation loop This assuption is ore general and requires sall input and output ipedance; this ean both sall resistance and capacitance at critical nodes such as the input and output With this assuption, Z eq is given by: TIA Rtan k + Rin >> ωres j Rin C0ω << 1 Zeq( jω) = (67) 1 j R C ω BW + We can now find the closed-loop transfer function, G noise : tan k 0 G noise ( jω) TIA BW = R F >> ω R tan k res + R in j R Rtan + R out k out C ω << Rin + R R F out ( 1+ j R ω) tan k C0 (68) The next step is to express the G noise in ters of known paraeters such as the Q and R of the icroechanical resonator The oscillation frequency in the presence of shunt parasitic capacitances of the resonator can be approxiated by: 1 C ω osc = 1+, (69) L C C p where L is the equivalent otional inductance of the icroechanical resonator Since C << C p, the oscillation frequency is very close to the natural resonance frequency of the icroechanical resonator, ie ω osc ω res Having said that, G noise, can be approxiated by: 198

217 199 ( ) [ ] osc res F F out in osc res out in F noise Q j C R j R R R R Q j R R R R j G ω ω ω ω ω ω , (630) where Q res is the unloaded Q of the icroechanical resonator To find the PSD of the output noise, the next step is to find G noise : ( ) ( ) ( ) F osc res osc F F total osc res osc res total F F osc res osc F F total osc res total osc res F F total total F noise C R Q R C R R R R Q C R Q C R R R C R Q R C R R R R Q R R R C Q R R R R R R j G ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω (631) where R total =R in +R out +R Then, the phase-noise of the oscillator is given by: ( ) ( ) ( ) F osc res osc F F total osc res osc res total F F osc res osc F F total osc res total osc res F F total total c S C R Q R C R R R R Q C R Q C R R R C R Q R C R R R R Q R R R C Q R R R R R P F kt L ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω (63)

218 00 For feedback oscillators in the steady-state condition (unity gain), the transipedance gain, R F, is alost equal to total loss fro the resonator and the aplifier, ie R total Now for close-to-carrier frequencies where ω << ω osc, the phase-noise can be further siplified to: ( ) ( ) total osc res osc total osc res osc res total total total osc res osc total osc res total osc res total c S C R Q R C R R Q C R Q C R R R C R Q R C R R Q R R R C Q R R P F kt L ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω (633) The expression for phase-noise looks rather coplicated To better understand the effect of second-order parasitics on the phase-noise, it is beneficial to look into several particular cases and then use coputer-aided progras such as MATLAB to accurately approxiate the oscillator phase-noise Very sall C 0 (C 0 0): For very sall C 0, the equation (633) can be reduced to a for siilar to (61), in effect eliinating neglecting the effect of second-order parasitics For reasons stated earlier, the accuracy of this odel is greatly coproised for high frequency lateral icroechanical resonators Even if the resonator shunt parasitic is reduced, the ere presence of input/output parasitic of the aplifier akes the perforance worse and renders the first-order odel incapable of providing accurate phase-noise approxiation

219 01 Very large R (R >> R in + R out ): When otional resistance is very large, the Q loading effect due to the aplifier parasitic becoes insignificant As such, the total resistance, R total, can be approxiated by R and the equation (633) can be siplified to: ( ) osc res osc osc res osc res osc res osc osc res c S C R Q R C R Q C R Q C R R C R Q R C R Q R P F kt L ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω (634) This is the near iniu phase-noise that can be achieved with an ideal TIA with infinitely-sall input and output ipedance (and consequently very large BW), ie no loading effect fro the aplifier Turning into a powerful CAD tool such as MATLAB, it is possible to see the effect of variation in shunt parasitic capacitance on the phase-noise perforance of the oscillator Fig 67 shows the predicted phase-noise of a typical 1GHz lateral piezoelectric icroechanical oscillator when the shunt parasitic capacitance of the resonator, C 0, is varied between 05pF to 4pF The phase-noise perforance clearly gets worse with large shunt parasitic capacitance

220 pF pf 05pF 1pF L(f) [dbc/hz] Offset Frequency [Hz] Fig 67 Variation in phase-noise perforance with C p 65 Case Study After developing an analytical LTI phase-noise odel for lateral icroechanical oscillators, it is necessary to validate the odel with easured phase-noise data Since the characteristics of the lateral piezoelectric and capacitive icroechanical resonator differ (especially Q and R ), it is logical to bring exaples of each type of the icroechanical oscillator and separately study the application of the aforeentioned phase-noise odel in each case Both LTI phase-noise odels, one that only considers the effect of first-order parasitics and another one that takes into the account the effect of second-order parasitics are used 0

221 in this process The goal is to deterine the accuracy of the LTI phase-noise odel with second-order parasitics included by coparing it with the easured phase-noise data and the LTI odel that only considers first-order parasitic effects When applying the LTI phase-noise odel to the easured data, the epirical paraeters such as F are chosen based on the easured data and kept fixed throughout this process for both first-order and second-order approxiation 651 High-frequency capacitive icroechanical oscillator Capacitive icroechanical resonators usually offer high Q but they exhibit larger loss than piezoelectric icroechanical resonators with siilar resonance frequency This study envisions a capacitive SiBAR as the frequency selective tank High frequency capacitive SiBARs exhibit otional resistance in the range of 1kΩ to over 10kΩ with Q in excess of 10,000 [1] For this work, we use a 97MHz SiBAR with Q operating 40,000, R 5kΩ, and V p 16V (Fig 68) The 97MHz SiBAR is interfaced with a low-power two-stage TIA to sustain the oscillation The oscillation is sustained at V P 16V with output power around 3dB (after gain of +10dB fro the buffer) The easured phase-noise is better than -11dBc/Hz at 1kHz offset with floor reaching -135dBc/Hz (Fig 69) The phase-noise floor can be iproved by reducing the otional resistance of the SiBAR that is easily achieved by applying larger V p ; however, due to the sall gap size, this coes at the expense of potentially pushing the capacitive transducer into nonlinear region and negatively affecting the close-to-carrier phase-noise perforance of the oscillator 03

222 The next step is to apply the LTI odel that was derived in previous section to the easured phase-noise data and investigate the parasitic effects on the phase-noise Fig 610 shows the easured phase-noise of the 97MHz capacitive SiBAR oscillator with two lines showing the fitted LTI phase-noise odels The black line phase-noise approxiation only considers the effect of first-order parasitic ipedances, ie finite input/output resistance of the aplifier and non-zero otional resistance of the SiBAR The green line represents the phase-noise odel that takes into the account both the firstorder and second-order non-idealities of the aplifier and icroechanical resonator In both cases, the epirical paraeters such as F are kept constant For Fig 610, it is clear that the green line representing the odel with second-order parasitics is a better fit to the easured phase-noise in both close-to-carrier and far-fro-carrier regions f 0 = 97MHz V p = 16V Q operating = 30,000 R =5kΩ Fig 68 Frequency response of the 97MHz capacitive SiBAR 04

223 f osc ~97MHz P osc ~-7dB Span=100kHz Fig 69 Output spectru and phase-noise of the 97MHz capacitive oscillator L(f) [dbc/hz] Measured PN First-Order Model Second-Order Model E1 1E 1E3 1E4 1E5 1E6 1E7 Offset Frequency [Hz] Fig st - and nd -order odel fit to the phase-noise of the 97MHz oscillator 05

224 65 High-frequency lateral piezoelectric icroechanical oscillators The ain otivation behind using lateral piezoelectric icroechanical resonators is to facilitate the realization of low-power high frequency icroechanical reference oscillators in gigahertz range [66] In this section, we focus on TPOS resonators for their higher Q and power handling both of which enhance the phase-noise perforance of the oscillator High-order TPOS resonators with otional resistance in the range of 100Ω to 1kΩ and unloaded Q larger than 1000, have been successfully reported in the literature [7] For this work, we use two TPOS resonators, a 9 th -order 463MHz AlN-on-Si resonator with Q unloaded 3,600, R 00Ω that uses a very thin silicon oxide layer for TCF reduction (Fig 611) and the 1 st -order 1006GHz AlN-on-Si resonator with large shunt parasitic capacitance, C p ~3pF, that was introduced in chapter 3 (Fig 61) f 0 = 463MHz Q unloaded = 30,000 R =00Ω Fig 611 Frequency response of the 463MHz TPOS resonator 06

225 The 463MHz AlN-on-Si icroechanical resonator is interfaced with a low-power threestage TIA siilar to the one shown in [7] to sustain the oscillation The oscillation power is around -5dB The easured phase-noise is better than -90dBc/Hz at 1kHz offset with floor reaching -153dBc/Hz (Fig 613) The 1006GHz icroechanical oscillator is based uses the sae sustaining aplifier that was described in chapter 3 with phase-noise better than -94dBc/Hz at 1kHz offset and floor around -154dBc/Hz (Fig 341) The power of the oscillation is close to -3dB f 0 ~1006GHz Q unloaded ~7100 R ~150Ω Fig 61 Frequency response of the 1006GHz TPOS resonator Siilar to the previous case, both first-order and second-order LTI odels are fitted to the easured phase-noise data (Fig 614 and 615) In both cases, the epirical paraeters such as F are kept constant The coparison of the fitted curves reveals that the phase-noise approxiation by the second-order LTI odel that takes into the account 07

226 both the first-order and second-order parasitic effects is uch ore accurate than the approxiation done with the first-order LTI phase-noise odel f osc ~463MHz P osc ~-5dB Span=100kHz Fig 613 Output spectru and phase-noise of the 463 MHz AlN-on-Si oscillator The results in Fig 614 and 615 highlight the effects of shunt parasitics as the oscillation frequency increases toward the UHF A detailed coparison of fitted odel results in Fig 610, 614, and 615 show that as the frequency increases, the accuracy of the firstorder LTI phase-noise odel is reduced; while for 97MHz capacitive SiBAR oscillator, the first-order approxiation is still a viable approach, the first-order phase-noise approxiation of the 463MHz and 1006GHz AlN-on-Si icroechanical oscillator are at least 10dB off fro the easured values Fro the results obtained in MATLAB for the second-order LTI odel of the 463MHz and 1006GHz oscillators, C 0 ~1pF is 08

227 probably the reasonable threshold when the first-order LTI phase-noise odel should be duped in favor of the ore accurate second-order LTI odel L(f) [dbc/hz] Measured PN Second-Order Model First-Order Model E1 1E 1E3 1E4 1E5 1E6 1E7 1E8 Offset Frequency [Hz] Fig st - and nd -order odel fit to the phase-noise of the 463MHz oscillator 66 Conclusion The phase-noise optiization and eventual iproveent of icroechanical oscillators is hindered by the lack of coprehensive phase-noise odeling for such oscillators Several electronic and echanical noise sources contribute to the phase-noise of highfrequency lateral icroechanical oscillators, however, the ain contributor to close-tocarrier phase-noise are flicker and theral noise Several well-known phase-noise odels have been developed for predicting the phase-noise behavior of oscillator Aong the, the LTI odel has a descent track record in predicting the phase-noise of quartz crystal 09

228 oscillators Despite this relative success, their accuracy in predicting the phase-noise perforance of high-frequency lateral icroechanical oscillator is considered arginal at best This is partly due to the second-order parasitic effect fro both the resonator and aplifier Upon including these parasitics, the accuracy of the LTI phase-noise odel is draatically iproved This is supported by easureent data fro high frequency icroechanical oscillators L(f) [dbc/hz] First-Order Model Second-Order Model Measured PN E1 1E 1E3 1E4 1E5 1E6 1E7 1E8 Offset Frequency [Hz] Fig st - and nd -order odel fit to the phase-noise of the 1006GHz oscillator 10

229 CHAPTER 7: Conclusion and Future Directions This chapter discusses the contributions of this research study and briefly outlines the possible avenues that can be pursued for future research in icroechanical oscillators 71 Contributions This dissertation focused on the realization of high frequency icroechanical reference oscillators As the result of this research effort, UHF tunable icroechanical reference oscillators were deonstrated; the ajor contributions to the technical field of icroechanical reference oscillator design are outlined here: A novel ethod to reduce the loss of capacitive icroechanical resonators without Q reduction is proposed This is achieved by optiizing the thickness of the capacitive resonator for the iniu loss in the specific frequency This research enabled a 145MHz capacitive SiBAR oscillator that eets the GSM phase-noise perforance and to-date, is the highest frequency capacitive icroechanical oscillator reported in the literature A detailed study of transipedance aplifiers for series-resonant icroechanical oscillator applications was presented This study covered basics of both open-loop and feedback TIA s in detail Several gain and BW enhanceent techniques with ephasis on their application in low-power high-frequency icroechanical oscillators were introduced Finally soe of these techniques were used to design and characterize several low-power high-gain CMOS TIAs capable of interfacing with icroechanical resonators with large shunt parasitic capacitance Aong these TIA s, one particular 018μ design took advantage of a low-power broadband 11

230 current pre-aplifier to boost the input current before converting that to voltage This TIA showed the highest FoM aong 018μ TIAs with siilar BW In addition, when interfaced with a high-q 1GHz AlN-on-Si resonator, it deonstrated a low phase-noise 1GHz icroechanical oscillator with the highest reported FoM aong the lateral icroechanical oscillators Tuning ethods for icroechanical oscillators were studied in detail The study started with introduction of different frequency tuning ethods: resonator-based and electronic and oved to deterine the feasibility of electronic tuning for lateral icroechanical oscillators Both parallel and series tuning techniques were investigated with ephasis on series tuning for series-resonant icroechanical oscillators Liitations of series tuning techniques for series-resonant lateral icroechanical oscillators were identified; during this process, the role of shunt parasitic capacitance of the lateral icroechanical resonators in severely liiting the tuning range was highlighted Shunt parasitic cancellation techniques were proposed and ipleented with either active inductor or negative capacitor to iprove the tuning range with inial ipact on the phase-noise perforance of the oscillator Finally, using the aforeentioned ethods, several 47MHz tunable oscillators were deonstrated with tuning range beyond 800pp (when negative capacitance cancellation is used) and close-to-carrier phase-noise degradation less than 5dB across the entire tuning range This research introduced the first-ever electronically-tuned lateral icroechanical oscillator 1

231 First-ever fully electronic teperature copensation of the high-frequency lateral icroechanical oscillator was ade possible by the enhanced electronic frequency tuning echanis developed in chapter 4 In this section, not only different teperature copensation ethods such as aterial copensation are explained and supported by exaples, the details of the circuits used for teperature copensation was also provided These details included the bandgap and PTAT references, difference aplifier, linear V-to-I convertor, and square-root generator Another contribution of this research study was the analytical phase-noise odeling of series-resonant lateral icroechanical oscillators After introducing the basics of the phase-noise in oscillators and briefly introducing several well-known phase-noise odels, this work focused on iproving the LTI phase-noise odel for highfrequency series-resonant icroechanical oscillators by considering the effect of parasitic capacitances The effect of first-order and second-order parasitics of the aplifier and resonator were factored in to arrive at an iproved LTI phase-noise odel which was validated by easureent data for both capacitive and piezoelectric icroechanical oscillators 7 Future Directions A nuber of research areas can benefit fro high frequency icroechanical reference oscillators While the ajority of these ethods will take advantage of higher oscillation frequency to iprove the overall syste-level perforance of radio transceivers, lately, there has been a strong willingness to pursue several interesting and rather unconventional research topics These include taking advantage of nonlinear operation of 13

232 resonators for phase-noise iproveent, single-resonator ulti-frequency operation, ultra-stable icroechanical reference oscillators using a PLL-based closed-loop syste, array of widely tunable icroechanical resonators for spectru sensing These topics are briefly discussed in this section 71 Nonlinear Operation for Phase-Noise Iproveent According to the first-order LTI phase-noise odel, the phase-noise of an oscillator whose resonating tank is a second order bandpass filter can be approxiated as: ktf 1 f ( ) = + osc f + c L f 1 1 (71) Posc 4Q f f In practice, the sustaining aplifiers have finite input and output ipedance and hence, load the resonator If the resonator can be odeled as a series RLC tank and the sustaining aplifier is a transipedance aplifier (TIA) with finite input and output resistance, the first-order approxiation of the phase-noise is: ktf 1 f osc f + c L( f = + ) 1 1, (7) Posc f QL f where Q L is the loaded Q of the resonator: Q loaded R = Qunloaded R + Rin + R, (73) out where R, R in and R out are the otional resistance, input and output resistance of the aplifier, respectively The noise of the parasitic cancellation blocks and tuning networks are included in F It is clear fro (7) that the close-to-career phase-noise can be iproved by: Reducing the noise of the circuitry (including parasitic cancellation and tuning block) 14

233 Reducing the flicker noise corner Increasing the loaded Q of the resonator Increasing the oscillation power Since the phase-noise is noralized to the carrier power, increasing the oscillation power helps reduce the phase-noise The oscillation power is both a function of the nonlinearity of the resonator and the aplifier For linear operation, the oscillation power is liited well-below the power handling capability of the resonator; however, studies suggest that in nonlinear operation of the resonator, there exists a region in which the phase-noise of the oscillator can be lowered to a level just 3dB above the intrinsic noise of resonator when operating in linear region [89] In this case, for sufficiently low-noise resonators (ie noise of the aplifier is at least 3 noise of the resonator and is the doinant noise source in the loop), the phase-noise of the oscillator with resonator operating in nonlinear region, can be approxiated by double the noise of the sae oscillator with noiseless aplifier and resonator operating in linear region Using (7) developed for linear phasenoise approxiation, the F can be approxiated as (3dB) This result is significant iproveent for low-power CMOS oscillators as they are inherently noisy designs for gigahertz applications The phase-noise iproveent could be as uch as 7-10dB in close-to-carrier As an exaple the 463MHz AlN-on-Si oscillator was driven into nonlinear region and its phase-noise is easured (Fig 71) At P osc -5dB, the close-to-carrier slope is higher than 30dB/dec, a strong indication for the presence noise sources other than the flicker 15

234 noise of the TIA in the output spectru The phase-noise is better than -9dBc/Hz at 1kHz offset which is around 3dB better than the when it is operating in linear condition Future studies ay reveal potential for ore uch-needed phase-noise iproveent 30dB/dec f 0 ~46378MHz P 0 ~-5dB Span=100kHz Fig 71 Spectru and phase-noise of the 463MHz oscillator in nonlinear region 7 Single-Resonator Dual-Frequency Microechanical Reference Oscillator Multi-ode radio transceivers are becoing increasingly popular as standard platfor for siultaneous voice, data, and ulti-edia counications in a single chip [3], [4] Due to the inherent in-copatibility of the fabrication process of quartz crystal resonators with silicon, designers are forced to coproise on syste perforance by relying on a single reference oscillator to generate ultiple frequencies Lateral icroechanical resonators such as SiBAR and TPOS enable the integration of ultiple resonators with 16

235 different fundaental frequencies on the sae substrate; thus allowing for optiization of the transceiver perforance in each band Dual-frequency oscillators have shown excellent perforance in accurate sensors and highly-stable reference oscillators for ulti-ode wireless transceivers [90], [91] The difference in the phase-noise requireent of narrowband G standards such as GSM [8] and OFDM-based 3G/4G [3], [4] standards calls for ultiple reference oscillators, each optiized for a specific standard [1] Using a dual-ode resonator helps achieve this goal while aintaining the sae for factor and potentially lowering the cost High-order TPOS resonators exhibit a unique behavior in which both the fundaental and higher-order response can be exploited to create dual-ode oscillators [65] A cascade of inverting and/or non-inverting stages can produce the required 0º or 180º needed for oscillation in different odes An on-chip switching network can be used to change the oscillation frequency accordingly Exploiting 180º phase difference between fundaental and higher order ode, no precautions need to be taken for odesuppression in the loop (Fig 7) 17

236 Fig 7 Block diagra of the single-resonator dual-frequency TPOS oscillator Using a 1 st /5 th ode TPOS resonator operating at 35MHz and 175MHz (Fig 73) with the RGC TIA of chapter 3 cobined with a switching network (Fig 74) for ode selection, a dual-ode icroechanical oscillator can be created The oscillation spectru and phase-noise in both odes have been onitored for both oscillation odes (Fig 75 and 76) The phase-noise results are coparable with iniaturized crystal oscillators raising the hope for increased functionality and perforance in future advanced ulti-ode radio transceivers 18

237 (a) f 1 = 355MHz R =1600Ω Q unloaded,air ~ 1550 (b) f 1 = 355MHz R =1360Ω Q unloaded,air ~ 1800 (c) f 3 = 1749MHz R =70Ω Q unloaded,air ~ 900 (d) f 3 = 1749MHz R =60Ω Q unloaded,air ~ 300 Fig 73 Response of the 1 st /5 th order resonator: air, (a), (c) and vacuu, (b), (d) Fig 74 The block diagra of the switching network 19

238 f 0 ~ 355MHz P 0 ~11dB Span=40kHz Fig 75 Phase-noise and spectru of fundaental ode of the 1 st /5 th oscillator f 0 ~ 1749MHz P 0 ~38dB Span=100kHz (b) (a) Fig 76 Phase-noise and spectru of higher order ode of the 1 st /5 th oscillator 0