PE4140. Product Specification. Ultra-High Linearity UltraCMOS Broadband Quad MOSFET Array. Product Description

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1 Product Description The PE0 is an ultra-high linearity passive broadband Quad MOSFET array with high dynamic range performance capable of operation beyond 6.0 GHz. This quad array operates with differential signals at all ports (RF, LO, IF), allowing mixers to be built that use LO powers from -7 dbm to +0 dbm. Typical applications range from frequency up/down-conversion to phase detection for Cellular/PCS Base Stations, Wireless Broadband Communications and STB/Cable modems. The PE0 is manufactured on Peregrine s UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. PE0 Ultra-High Linearity UltraCMOS Broadband Quad MOSFET Array Features Ultimate Quad MOSFET array Ultra-high linearity, broadband performance beyond 6.0 GHz Ideal for mixer applications Up/down conversion Low conversion loss High LO Isolation Packaged in small 6-lead x mm DFN Figure. Functional Diagram Figure. Package Type 6-lead DFN LO IF RF Table. AC and DC Electrical + C Symbol Characteristics Test Conditions Min Typ Max Units F TYP Operating Frequency Range DC 6.0 GHz V DS Drain-Source Voltage V GS = +V, I DS = 0 ma mv V DS Match Drain-Source Voltage Match 0 mv V T Threshold Voltage V DS = 0.V; per ASTM F mv R DS Drain-Source ON Resistance V GS = +V, I DS = 0 ma Ω Note : Typical untested operating frequency range of Quad MOSFET transistors. Document No. DOC Peregrine Semiconductor Corp. All rights reserved. Page of 0

2 PE0 Figure. Pin Configuration (Top View) Table. Pin Descriptions Pin No. IF RF RF Pin Name Exposed Solder Pad (bottom side) Table. Absolute Maximum Ratings 6 IF LO LO Description IF IF Output Connection (Drain) RF RF Input Connection (Source) RF RF Input Connection (Source) LO LO Input Connection (Gate) LO LO Input Connection (Gate) 6 IF IF Output Connection (Drain) Symbol T ST T OP V DC + AC V DC+AC Parameters/ Conditions Storage temperature range Operating temperature range Maximum DC plus peak AC voltage across Drain- Source Maximum DC plus peak AC voltage across Gate- Drain or Gate-Source Min Max Units -6 0 C -0 8 C ±. V ±. V V ESD HBM ESD Voltage 00 V Electrostatic Discharge (ESD) Precautions This MOSFET device has minimally protected inputs and is highly susceptible to ESD damage. When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Device Description The PE0 passive broadband Quad MOSFET array is designed for use in up-conversion and down-conversion applications for high performance systems such as cellular infrastructure equipment and STB/CATV systems. The PE0 is an ideal mixer core for a wide range of mixer products, including module level solutions that incorporate baluns or other singleended matching structures enabling three-port operation. The performance level of this passive mixer is made possible by the very high linearity afforded by Peregrine s UltraCMOS process. Marking Packaged devices are marked with part number 0, date code and lot code. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE0 in the 6-lead x DFN package is MSL. Note : ML_STD 88 Method 0.7 Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. 08 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC UltraCMOS RFIC Solutions Page of 0

3 PE0 Evaluation Kit Figure. Evaluation Board Layout Peregrine Specification 0/0090 Applications Support If you have a problem with your evaluation kit or if you have applications questions, please contact applications support: help@psemi.com (fastest response) Phone: (88) Figure. Evaluation Board Schematic Peregrine Specification 0/0 Note: This is the complete evaluation board schematic; which can be used for multiple configurations. Not all components need be populated. Refer to 'typical schematics' on following pages. Document No. DOC Peregrine Semiconductor Corp. All rights reserved. Page of 0

4 PE0 Figure 6. Typical Schematic for a PCS Application J LO Input T M/A Com ETC.6--- R. nh R.7 nh T M/A Com ETC.6--- R6 pf J RF Input R. nh R8.7 nh 6 PE0 T TOKO 67DB-0 J6 IF Out Table. Typical Performance in a PCS + C Parameter Minimum Typical Maximum Units Frequency Range** LO RF IF Conversion Loss** (Includes balun losses) Isolation** LO-RF LO-IF db 6 db 6 db Input IP** dbm Input db Compression** dbm ** Data taken on an Evaluation Board narrow-band tuned to cover the PCS band, IF = 7 low-side, LO drive = 7dBm. 08 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC UltraCMOS RFIC Solutions Page of 0

5 PE0 Typical Performance Plots in a PCS + C (LO=7 dbm, IF=7 Low-side) Figure 7. IIP vs. Frequency Figure 8. Conversion Loss vs. Frequency 0 0 IIP 7dBm Lo Conversion Loss 7dBm Lo IF=7Mhz Low-side Conversion Loss Frequency () Frequency () Figure 9. LO-RF & LO-IF Isolation Isolation (db) LO-IF -0 LO-RF Frequency () Document No. DOC Peregrine Semiconductor Corp. All rights reserved. Page of 0

6 PE0 Figure 0. Typical Schematic for a CATV Application (Reference Designators Refer to locations on Evaluation Board: 0/0090) J ETC.6--- LO Input T.7nH L 6 U MLP6-X ETC.6--- T R6.0pF J RF Input L.7nH (Cut short between pads) T ETC-- J6 IF Out Note: L and L provide LO port matching for optimum performance. Typical gate capacitance is approximately. pf. Table. Typical Performance in a CATV + C Parameter Minimum Typical Maximum Units Frequency Range** LO RF IF Conversion Loss** (Includes balun losses) 6. db Isolation** LO-RF LO-IF 0 8 db db Input IP** dbm Input db Compression** dbm ** Data taken on an Evaluation Board tuned for a broadband CATV application, IF = 06, RF drive = - dbm, LO drive = 0 dbm. 08 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC UltraCMOS RFIC Solutions Page 6 of 0

7 PE0 Typical Performance Plots in a CATV + C Figure. IIP vs. Frequency Figure. Conversion Loss vs. Frequency 0 0 IIP LO 0 0 Conversion Loss LO Frequency () Frequency () Figure. LO-RF & LO-IF Isolation 0-0 Isolation (db) -0-0 LO-IF -0-0 LO-RF Frequency () Document No. DOC Peregrine Semiconductor Corp. All rights reserved. Page 7 of 0

8 PE0 Figure. Package Drawing 6-lead DFN 06L SLP (xmm) NOTE: The exposed solder pad (on the bottom of the package) is not electrically connected to any other pin (isolated). Figure. Marking Specifications 0 YYWW ZZZZZ YYWW = Date Code (last two digits of year and work week) ZZZZZ = Last five digits of Lot Number 08 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC UltraCMOS RFIC Solutions Page 8 of 0

9 PE0 Figure 6. Tape and Reel Specifications 6-lead DFN Tape Feed Direction Pin Table 6. Dimensions Dimension DFN x mm Ao. ± 0. Bo.7 ± 0. Ko.7 ± 0. P ± 0. W 8 +0., -0. T 0. ± 0.0 R7 Quantity 000 R Quantity N.A. Device Orientation in Tape Top of Device Note: R7 = 7 inch Lock Reel, R = inch Lock Reel Table 7. Ordering Information Order Code Part Marking Description Package Shipping Method 0-0 PE0G-06DFN xmm-000c Green 6-lead x mm DFN 000 units / T&R PE0B-z 0 PE0G-06DFN xmm-000c Green 6-lead x mm DFN 000 units / T&R 0-00 PE0-EK PE0-06DFN xmm-ek Evaluation Kit / Box EK0-0 PE0-EK PE0-06DFN xmm-ek Evaluation Kit / Box Document No. DOC Peregrine Semiconductor Corp. All rights reserved. Page 9 of 0

10 PE0 Sales Offices The Americas Peregrine Semiconductor Corporation 980 Carroll Park Drive San Diego, CA 9 Tel: Fax: Europe Peregrine Semiconductor Europe Bâtiment Maine - rue des Quatre Vents F-980 Garches, France Tel: Fax : High-Reliability and Defense Products Americas San Diego, CA, USA Phone: Fax: Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 0000, P.R. China Tel: Fax: Peregrine Semiconductor, Korea #B-607, Kolon Tripolis, 0 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 6-9 South Korea Tel: Fax: Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 0B-6 -- Uchisaiwai-cho, Chiyoda-ku Tokyo Japan Tel: Fax: Europe/Asia-Pacific Aix-En-Provence Cedex, France Phone: Fax: For a list of representatives in your area, please refer to our Web site at: Sales Contact and Information For additional information, contact Sales at sales@psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. : The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user s own risk. 08 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC UltraCMOS RFIC Solutions Page 0 of 0