DESIGN AND SIMULATION OF DC/DC BOOST CONVERTER

Transcription

1 Mna Unversty Frm the SelectedWrks f Dr. Adel A. Elaset Wnter Decemer 23, 2008 DESGN AND SMULATON OF DC/DC BOOST CONERTER Dr. Adel A. Elaset, Mna Unversty Dr. B. M. Hasaneen Avalale at:

2 DESGN AND SMULATON OF DC/DC BOOST CONERTER B. M Hasaneen Faculty f Eng., AlAzhar Unversty, Kena, Egypt. Tel: Barakat09@yah.cm Adel A. Elaset Mhammed Faculty f Engneerng, Mna Unversty, Mna, Egypt. Tel: Fax: Dr_AdeL72@yah.cm Astract : Ths paper presents a desgn and smulatn f DC/DC st cnverter. Ths system has a nnlnear dynamc ehavr, as t wrk n swtchmde. Mrever, t s expsed t sgnfcant varatns whch may take ths system away frm nmnal cndtns, due t changes n the lad r n the lne vltage at the nput. The nput usually s taned y P array and therefre the desgn and smulatn n ths paper cvers the whle range f radatns and temperature. n ths paper we analyze the equatns f a st cnverter and prpse a desgn cmpnents and smulatn f DC/DC st cnverter. Ths wrk s appled t phtvltac system fr trackng the pnt f maxmum pwer.. NTRODUCTON The DC/DC cnverters are wdely used n regulated swtch mde DC pwer supples. The nput f these cnverters s an unregulated DC vltage, whch s taned y P array and therefre t wll e fluctuated due t changes n radatn and temperature. n these cnverters the average DC utput vltage must e cntrlled t e equated t the desred value althugh the nput vltage s changng. Frm the energy pnt f vew, utput vltage regulatn n the DC/DC cnverter s acheved y cnstantly adjustng the amunt f energy asred frm the surce and that njected nt the lad, whch s n turn cntrlled y the relatve duratns f the asrptn and njectn ntervals. These tw asc prcesses f energy asrptn and njectn cnsttute a swtchng cycle. ntutvely speakng, f the energy strage capacty f the cnverter s t small r the swtchng perd s relatvely t lng, then the cnverter wuld have transmtted all the stred energy t the lad efre the next cycle egns. Ths ntrduces an dlng perd mmedately fllwng the njectn nterval, durng whch the cnverter s nt perfrmng any specfc task [,2,3]. The cnverter can therefre perate n tw dfferent mdes dependng upn ts energy strage capacty and the relatve length f the swtchng perd. These tw mdes are knw as the dscntnues cnductn and cntnuus mdes. Graphcally mdel f the st cnverter s shwn n Fg.. The full detals f the st cnverter tplgy have een already dscussed n [4,5,6]. The DC/DC st cnverter nly needs fur external cmpnents: nductr, Electrnc swtch, Dde and utput capactr. The cnverter can therefre perate n the tw dfferent mdes dependng n ts energy strage capacty and the relatve length f the swtchng perd. These tw peratng mdes are knwn as the dscntnuus cnductn mde, DCM, and cntnuus cnductn mde, CCM, crrespndng t the cases wth and wthut an dlng nterval respectvely [6,7]. 2. METHODOLOGY 2 Cnversn mdes The DC/DC cnverter has tw mdes, a Cntnuns Cnductn Mde, CCM fr effcent pwer cnversn and Dscntnuns Cnductn Mde DCM fr lw pwer r standy peratn, L (t) L(t) GBT t n T s t ff d(t) C c(t) Fg. Crcut Schematc f Stepup DC/DC Cnverter [8] 2 Cntnuns Cnductn Mde Mde (0<t t n ) Mde egns when GBT's s swtched n at t0 and termnates at tt n. The equvalent crcut fr the mde s shwn n Fg. 2a. The nductr current L (t) greater than zer and ramp up lnearly. The nductr vltage s. Mde 2 (t n <t T s ) Mde 2 egns when GBT's s swtched ff at tt n and termnates at tt s. The equvalent crcut fr the mde 2 s shwn n Fg. 2. The nductr current decrease untl the GBT's s turned n agan durng the next cycle. The vltage acrss the nductr n ths perd s. Snce n steady state tme ntegral f the nductr vltage ver ne tme perd must e zer. t n ( ) t ff 0 [4,6] () : The nput vltage,. : The average utput vltage,. t n : The swtchng n f the GBT's, s t ff : The swtchng ff f the GBT's, s Dvdng th sdes y T s and rearrangng tems yeld T s t ff D Ts : The swtchng perd, s. D : The duty cycle. (t) [4,6] (2) Lad /08/$ EEE 335

3 L v L L L t n t ff ( ) T s v L(t) L (t) v L(t) L (t) (t) L(t) L(t) (t) C Lad C Lad c(t) c(t) (a) Fg. 2 Equvalent Crcut fr st Cnverter n CCM [4,6] (a) Mde (0<t t n ) () Mde 2 (t n <t T s ) Thus, s nversely prprtnal t (D). t vus that the duty cycle, D, can nt e equal t therwse there wuld e n energy transfer t the utput. assumng a lssless crcut, PP, then [4,6] (3) and, D [4,6] (4) : The average utput current, Amp. : The average nput current, Amp. 22 Dscntnuns Cnductn Mde f the current fllwng thrugh the nductr falls t zer efre the next turnn f the swtchng GBT's, () then the st cnverter s sad t e peratng n the dscntnuus cnductn mde. f we equate the ntegral f the nductr vltage as shwn n Fg. 24 ver ne tme perd t zer, DT s ( ) D T 0 [4,6] (5) s Then; D D [4,6] (6) D and D (snce P P ) [4,6] (7) D D L v L L DT s t n DT s t ff ( ) T s (t) v L(t) L L(t) C c(t) (t) Lad v L L(t) (t) L(t) (t) C c(t) Lad v L(t) L (t) L(t) (t) C c(t) Lad (a) () (c) Fg. 3 Equvalent Crcut fr st Cnverter n DCM (a) Mde (0<t t n ) () Mde 2 (t n <t (DD)T s (c) Mde 3 (DD)T s <t T s 336

4 Frm Fg. 3c, the average nput current, whch s equal t the nductr current, s DT ( D D ) [4,6] (8) 2L s Usng Equ. (7) n the fregng equatn yelds T s DD [4,6] (9) 2L n practce, snce s held cnstant and D vares n respnse t varatn n, t s mre useful t tan the requred duty cycle, D, as a functn f lad current fr vares values f /. By usng Eqns (6) and (9), we can determne that: D [4,6] (0) 27, aver, max,aver,max :The maxmum average utput current at the edge f cntnuus cnductn and can e fund y the fllwng Equatn. T s 2, aver D( D) [4,6] () 2L The average utput current has ts maxmum at D/3. 2 T s, aver,max [4,6] (2) 27 L The crtcal nductance, L c, s defned as the nductance at the undary edge etween cntnuus and dscntnuus mdes and s defned as: 2 R D ( D) L c [4,6] (3) 2 F s where; R : The equvalent lad, Ω. F s : The swtchng frequency, Hz The swtchng frequency has een chsen artrarly t mnmze the sze f the st nductr and lmt the lss f the semcnductr devce. At hgher frequences the swtchng lsses n the GBT's ncrease, and therefre reduce the verall effcency f the crcut. At lwer frequences the requred utput capactance and st nductr sze ncreases, and the vlumetrc effcency f the supply degrades [9]. 22 Selectn Of The Semcnductr Devce The man swtchng element has een chsen t handle the wrst case current and vltage stresses. The maxmum vltage stress n the swtchng devce ccurs when the P utput vltage s maxmzed, s: max,stress pv,max (4) pv,max : s the maxmum nput vltage frm P array, lt. The maxmum current stress ccurs when system pwer s predmnately prvded y the P. Therefre, the peak current s [9] (5) peak utput rpple P * P n, max n, max (6) peak pv pv P n,max :s the maxmum utput pwer frm P array whch t s the nput t st cnverter. : s the percentage f rpple current t lad utput current. 23 Selectn f the nductr Large nductance values tend t ncrease the startup tme slghtly whle small nductance values allw the cl current t ramp up t hgher levels efre the swtch turns ff. nductrs wth a ferrte cre r equvalent are recmmended. t shuld e ensured that the nductr s saturatn current ratng fr hghest effcency s t e used a cl wth lw DC resstance. Bst nductance s selected ased n the maxmum allwed rpple current at mnmum duty cycle, D, at maxmum nput vltage, nput. Gven that the swtchng frequency, Fs, the st nductr value may e ptmally determned t set the cnverter peratng mde n the requred lad and lne range. The crtcal nductance s defned as the nductance at the undary edge etween cntnuus and dscntnuus mdes and s defned as [4,6]: R*D( D) 2 L c H (7) 2*Fs Where, Fs : The swtchng frequency, Hz D : The duty cycle, R : The equvalent lad, Ω. 24 Selectn f the Dde The st dde reverse vltage ratng s lmted t the utput vltage. The dde cnducts when the pwer swtch s n the OFF state and prvdes a current path fr the nductr t the utput. Smlar t the GBT's the wrst case peak current thrugh the dde ccurs at lw lne nput vltage and maxmum lad. Other mprtant cnsderatns n selectng the dde esdes ts alty t lck the requred ff state vltage stress and have suffcent peak and average current handlng capalty, s fast swtchng characterstcs, lw reverse recvery, and lw frward vltage drp. 25 Selectn f the capactance requred The prmary crtern fr selectng the utput flter capactr s ts capactance and equvalent seres resstance, ESR. Snce the capactr s ESR affects effcency, lwesr capactrs wll e used fr est perfrmance. Fr reducng ESR s als pssle t cnnect few capactrs n parallel. The utput flter capactrs are chsen t meet an utput vltage rpple 337

5 specfcatns, as well as ts alty t handle the requred rpple current stress. An apprxmate expressn fr the requred capactance as a functn f rpple vltage requrement,, D, swtchng frequency, Fs and utput vltage, s gven as [4,6]: * D C (8) Fs * * R 3 APPLCATON AND RESULTS 3 Desgn DC/DC Bst cnverter A cmputer prgram has een desgned t cmpute all nductances and capactances fr all duty cycle.e fr all radatns. T ensure DCM fr these peratng cndtns the nductance have een chsen at a value smaller than the crtcal nductance and fr ths cnverter s set at 0.67 mh, 78 µh and 22 µh fr varatn f the lad frm 2kW, 200 kw and 500 kw respectvely. Fgures 4 & 5 shw the value f crtcal nductance fr crtcal cnductn mde peratn ver the nput vltage range.e. fr all radatn change. Fgure 6 shws the relatn etween utput capactance and duty cycle. Frm ths Fgure t can e seen that requred capactance C req 3500 µ F 32 Smulatn f DC/DC Cnverter T verfy the respnse f the cnverter as nlne algrthm, a cmplete dynamc mdel f P array and DC/DC cnverter scheme have een smulated y Matla/Smulnk sftware [0],[]. The DC/DC cnverter has een smulated fr varatn f the lad frm 2 kw, 200 kw and 500 kw respectvely. The smulnk lck dagram f a st cnverter and ts cntrller s shwn n Fg 7. The mdel's nput s taken pwer frm slar cells array and the utput f the mdel s fed t the lad demand. The utput vltage frm P array, dcpv whch s the nput t st cnverter s shwn n Fg. 8. The P array has een tested fr lad change due t change n slar radatn. The lad set 2 kw at 9.30 A.M. fr slar radatn 0.2 kwh/m 2, 200 kw at.00 A.M. fr slar radatn 0.6 kwh/m 2 and fnally t 500 kw at.00 A.M. fr slar radatn.0 kwh/m 2 and then ack t 200 kw then 2 kw as shwn n Fg. 9. Radatn Fg. 7 Smulnk Mdel fr the Bst Cnverter wth the Onlne Algrthm. Fg. 4 Relatn Between Duty Cycle and Crtcal nductance. Fg. 5 Relatn Between nput ltage and Crtcal nductance. Fg. 8 Output ltage frm P Slar Cells array due t Change f Radatn. Fg. 6 The Relatn Between Output Capactance and Duty Cycle. Fg. 9 Lad curve durng the Day. 338

6 Smulatns have een run at varus lads t check the apprxmate undary cndtn f the nductr and the sft swtchng f the devces. Once the smulatn have een cmpleted, the smulated respnse f dde's current and nductr's current fr a radatn f 0.2 kw/m 2 and lad 200 kw, and.0 kw/m 2 and lad 500 kw are shwn n Fg. 0 and Fg.. Als, Fg. 2, Fg. 3 and Fg. 4 shw the nput vltage and utput vltage at a radatn f 0.20 kw/m 2, 0.6 kw/m 2 and.0 kw/m 2 respectvely. On the ther hand Fg. 5, Fg. 6 and Fg. 7 shw the GBT's current, c and cllectr t emtter vltage, ce at a radatn f 0.2 kw/m 2, 0.6 kw/m 2 and.0 kw/m 2 respectvely. Fg. 3 Smulated Respnse f nput ltage and Output ltage at Radatn f 0.6 kw/m 2 Fg. 0 Smulated Respnse f Dde's Current and nductr's Current at Radatn f 0.2 kw/m 2 Fg. 4 Smulated Respnse f nput ltage and Output ltage at Radatn f.00 kw/m 2 Fg. Smulated Respnse f Dde's Current and nductr's Current at Radatn f.0 kw/m 2 Fg. 5 Smulated Respnse f GBT's Current and CllectrEmtter ltage at Radatn f 0.2 kw/m 2 Fg. 2 Smulated Respnse f nput ltage and Output ltage at Radatn f 0.2 kw/m 2 Fg. 6 Smulated Respnse f GBT 's Current and CllectrEmtter ltage at Radatn f.6 kw/m 2 339

7 Fg. 7 Smulated Respnse f GBT 's Current and CllectrEmtter ltage at Radatn f.0 kw/m 2 The smulated respnse f utput vltage s dsplayed n Fg. 8 fr all radatn cndtn durng the day. On the ther hand, the smulated nductr current, dde current and GBT's current fr all perds.e. fr all varatn f radatn durng the day are shwn n Fg. 9, Fg. 20 and Fg. 2 respectvely. Fnally, frm all the ave fgures, verall cnverter wrks well. The utput vltage varatn can e reslved wth the nverter cntrl strategy. Fg. 8 Smulated Respnse f Output ltage due t change f Radatn durng the Day Fg. 9 Smulated Respnse f nductr Current due t change f Radatn fr all Day Fg. 20 Smulated Respnse f Dde Current due t change f Radatn durng the Day Fg. 2 Smulated Respnse f GBT's Current due t change f Radatn durng the Day 4 Cnclusn Ths paper cncerns wth desgn and smulatn f DC/DC st cnverter t perate n P system. Frm the results taned ave, the fllwng are the salent cnclusns that can e drawn frm ths paper: Desgn the DC/DC cnverter fr all peratng cndtn have studed and prpsed. Detaled mdelng and smulatn f a DC/DC cnverter cnnected t P system have prpsed. Bst nductr s chsen t e 0.67 mh, 78µH and 22µH fr varatn f the lad frm 2kW t 500kW. Bst capactance s chsen t e greater than r equal 3500µF fr varatn f the lad frm 2kW t 500kW. 5References [] Knstantn P. Lugansk, "Mdelng and Analyss f A DC Pwer Dstrutn System n 2 st Century Arlfters", M. Sc., Electrcal Engneerng Dept., Faculty f the rgna Plytechnc nsttute and State Unversty, Septemer 30, 999, Blacksurg, rgna. [2] Jaer AuQahuq and ssa Batarseh, "Generalzed Analyss f SftSwtchng DCDC Cnverters", SCAS 2000 EEE nternatnal Sympsum n Crcuts and Systems, May 28 3, 2000, Geneva, Swtzerland, pp [3] Wywde, O.; Güldner, H. "Applcatn f Statstcal Analyss t DCDC Cnverter" nternatnal Pwer Electrncs Cnference, PEC 2000, Tky, Japan [4] Mhammad H. Rashd, "Pwer Electrncs: Crcuts, Devces and Applcatns", PrentceHall, nc., Englewd Clffs, Bk, Secnd Edtn, 993. [5] B. W. Wllams, " Pwer Electrncs; Devces, Drvers, Applcatns and Passve Cmpnents", Bk, Secnd Edtn, Educatnal LwPrced Bks Scheme; ELBS, 992. [6] Mhan Ned, Undeland Tre M. and Rns Wllam P.,"Pwer Electrncs,Cnverters Applcatns and Desgn", Jhn Wley & Sns, nc., Bk, 995. [7] C. K. Tse and K. M. Adams, "Qualtatve analyss and cntrl f a DCtDC Bst Cnverter Operatng n Dscntnuus Mde", EEE Transactns n Pwer Electrncs, l. 5, N. 3, July 999, Pp [8] Adel A. Elaset Mhammed, " Study f ntercnnectng ssues f Phtvltac/Wnd Hyrd System wth Electrc Utlty Usng Artfcal ntellgence ", Ph. D. Thess, Faculty f Eng., Electrcal Engneerng Dept., Mna Unversty, [9] AND8035D.pdf [0] MatlaSmulnk User s Gude, Themathwrks, ersn R2. [] Pwer System Blckset User s Gude, The Mathwrks, ersn R2. 340