INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET)

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1 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET) Proceedings of the 2 nd International Conference on Current Trends in Engineering and Management ICCTEM ISSN (Print) ISSN (Online) Volume 5, Issue 8, August (2014), pp IAEME: Journal Impact Factor (2014): (Calculated by GISI) IJEET I A E M E PHASE SHEDDING IN MULTIPHASE BUCK CONVERTERS TO IMPROVE THE EFFICIENCY Suman Rama Harikantra 1, Divya K. Pai 2 1 Dept. of E&EE, St. Joseph Engineering College, Mangalore, India, 2 Dept. of E&EE, St. Joseph Engineering College, Mangalore, India, ABSTRACT With industry moving to higher performance platforms, efficiency of the power converter is critical. To improve the efficiency in this paper Phase Shedding is implemented in multiphase synchronous buck converter. In order to obtain the more efficiency in different loads in multiphase synchronous buck converter there is a requirement of phase shedding. Phase Shedding is disconnecting of phases in multiphase synchronous buck converter at different loads to get maximum efficiency in a particular load current. Working of multiphase synchronous buck converter with phase shedding is verified with the help of Mat lab / Simulink software. Keywords: Multiphase synchronous buck converter, Phase Shedding. 1. INTRODUCTION As processor based system, such as laptop and desktop computers, become more complex, more power is consumed by both active and standby system. Consequently, efficient power management solution for such a system imposes new challenges to energy management, especially for improved light load efficiency and extending battery life.[1] In power management applications, the multiphase converter with pulse width modulation (PWM) signals interleaved among the phases is widely used, since it provides several advantages in terms of input and output current ripple reduction, and faster transient response. When the load current is decreased, it is not necessary to continuously modulate all phases, since the load current can be shared among a reduced number of cells. The operation of disconnecting some phases at light load in order to improve the converter efficiency is usually denoted as phase shedding (PS). PS can be implemented with minimum output-voltage deviations and minimum transient-response time. In a more recent contribution, a PS with an adaptive voltage controller, based on the number of active phases, is proposed. The number of active phases is based on the inductor current measurement and the voltage loop (or droop controller) handles the transient due to the PS. 53

2 2. Ps IN MULTIPHASE BUCK CONVERTERS The synchronous buck converter is used to step a voltage down from a higher level to a lower level. With industry moving to higher performance platforms, efficiency of the power converter is critical. Multiphase synchronous buck converter consists of a MOSFET, Shottky diode, inductor, capacitor and load. A diode is placed in parallel with the MOSFET to provide a conducting path for inductor current during the dead time when both MOSFETs are off. This diode may be the MOSFET body diode, or it may be an extra diode or Shottky diode, for improved switching. Fig.2.1: Basic Scheme of a Multiphase Buck Converter Consider only two switches ie S1 and S1 1. When S1, the high side MOSFET, is connected directly to the input voltage of the circuit. When S1 turns on, current is supplied to the load through the high side MOSFET. During this time, S1 1 is off and the current through the inductor increases, charging the LC filter. When S1 turns off, S1 1 turns on and current is supplied to the load through the low side MOSFET. During this time, the current through the Inductor decreases, discharging the LC filter. Advantage of this configuration is that the MOSFETs will have a much lower voltage drop across it compared to a diode, resulting the high current efficiency. This is especially important in low-voltage, high-current application. A Shotty diode have a voltage of 0.3 to 0.4V across it while conducting, where as a MOSFETS will have an extremely low voltage drop due to an RDs on as low as single-digit milli ohms. So this circuit is known as synchronous rectification or synchronous switching. 3. SIMULATION AND RESULTS 3.1 Open Loop Analysis Single stage N=1 for synchronous buck converter 54

3 Fig 3.1: Block diagram of single stage buck converter The simulation is designed for synchronous buck converter for the stage N=1, where N is the number of phase. In this stage it consisting of two switches S1 and S1 1. Carrier signal is ramp signal of 100 khz and gate signal of two switches are complimentary to each other as shown in Figure 3.2 Fig 3.2: Carrier signal, ref signal, gating signal for S1 and S1 1 55

4 Fig 3.3: output voltage and output current for single stage. The Fig 3.3 shows the cross section waveform of output voltage and the output current.this simulation result is obtained by the resistor R=1Ω.Where first waveform shows output voltage of 5.749V and it contain high ripple.similarly second waveform shows output current of 5.749A and having high ripple in the stage N=1.As the number of stages increases the output of the current ripple will also reduceses. Fig 3.4: inductor current waveform of single stage. The output obtained for simulation in the matlab is shown where the inductor current that is 6.23A wit respect to time,for the load resistor R=1Ω is shown in Fig 3.4 Table 3.1: Obtained o/p current and efficiency value from stage 1. Resistor (Ω) O/P Current(A) Efficiency (%)

5 The tabular column 3.1 is based on output current and efficiency by varing different value of resistors.as a load resistor increases the value of the output mean current is decreases and efficiency is also decreases. Fig 3.5: Efficiency v/s load current graph for single stage. The Fig 3.5 shows the efficiency v/s load current for the stage N=1.Where X axis denotes the load current and y axis denotes the efficiency. By using the table 3.1 we can plot the efficiency graph.efficiency can be calculated by Pout/Pin. [2] Two stage N=2 for synchronous buck converter Fig 3.6: SIMULINK block diagram of two stage synchronous buck converter. The simulation is designed for synchronous buck converter for the stage N=2, where N is the number of phases. In this stage it consist of four switches S1, S1 1 and S2, S2 1.The switch S1 is ON till 5.9e -06 until that the switch S1 1 is OFF. And similarly the switch S2 is ON for the period of e -06 until that the switch S2 1 is OFF as shown in the Fig

6 Fig 3.7: Gating signal for S1, S1 1 for stage1 and S2, S21for stage 2.. Fig 3.8: output voltage and output current for two stages. The Fig 3.8 shows the output voltage and the output current.this simulation result is obtained by the resistor R=1Ω.Where first waveform shows output voltage of 6.559V and it contain high ripple.similarly second waveform shows output current of 6.559A and having high ripple in the stage N=2.Compare to stage 1 the ripple is reduced in stage 2. Fig 3.9: inductor current waveform of two stages. 58

7 The output obtained for simulation in the matlab is shown.the inductor current for IL1 is 2.512A and for IL2 is 3.591A wit respect to time,for the load resistor R=1Ω is shown in Fig 3.9. Table 3.2: Obtained o/p current and efficiency value from stage 2 Resistor(Ω) O/P mean Current(A) Efficienc y (%) The tabular column is based on output mean current and efficiency by varing different value of resistors.as a load resistor increases the value of the output mean current is decreases and efficiency is also decreases. Fig 3.10: Efficiency v/s load current graph for two stages. The Fig 3.10 shows the efficiency v/s load current for the stage N=2.Where X axis denotes the load current and y axis denotes the efficiency. By using the table 7.3 we can plot the efficiency graph.efficiency can be calculated by Pout/Pin. [2] Third stage N=3 for synchronous buck converter 59

8 Fig 3.11: SIMULINK block diagram of Third stage synchronous buck converter. The simulation is designed for synchronous buck converter for the stage N=3, where N is the number of phases. In this stage it consisting of six switches S1, S1 1, S2, S2 1 and S3, S3 1. The switch S1 is ON till 5.9e -06 until that the switch S1 1 is OFF. And similarly the switch S2 is ON for the period of e -06 until that the switch S2 1 is OFF and the switch S3 is ON for the period of e -06 until that the switch S3 1 is OFF as shown in the Fig 3.12 Fig 3.12: Gating signal for S1, S1 1 for stage1 and S2,S2 1 for stage 2 and S3,S3 1 for stage 3. 60

9 Fig 3.13: Simulated waveforms of output voltage and output current for third stage. The Fig 3.13 shows the cross section waveform of output voltage and the output current.this simulation result is obtained by the resistor R=1Ω.Where first waveform shows output voltage of 6.612V and it contain high ripple.similarly second waveform shows output current of 6.612A and there is no ripple in stage N=3.Compare to stage 1 and stage 2. Fig 3.14: inductor current waveform of third stage. The output obtained for simulation in the matlab is shown below where the inductor current il1,il2 and il3 that is 1.531A, 2.611A and 2.294A wit respect to time,for the load resistor R=1Ω is shown in Fig Table 3.3: Obtained o/p current and efficiency value from stage 3 Resistor (Ω) O/P Current(A) 61 Efficiency (%)

10 The Table 3.3 is based on output current and efficiency by varing different value of resistors.as a load resistor increases the value of the output mean current is decreases and efficiency is also decreases. Fig 3.15: Efficiency v/s load current graph for third stage. The Fig 3.15 shows the efficiency v/s load current for the stage N=3.Where X axis denotes the load current and y axis denotes the efficiency. By using the table 7.4 we can plot the efficiency graph. Efficiency can be calculated by Pout/Pin.[2]. 4. COMPARISON OF ALL THE THREE STAGES OF CONVERTER Fig 4.1: Efficiency v/s load current graph for all the three stages. The Fig 4.1 shows the efficiency v/s load current for the different stages.where if the load current is in between A to 0.76A the stage N=1 will be selected because compare to other two stages,the stage N=1 will give high efficiency i.e 97.22% and load current current is less and load resistor value is high for the lower current.as the load current is increases the number of stages will also increases. Where if the load current is in between 0.72A to 1.04A the stage N=2 will be selected because compare to other two stages, the stage N=2 will give high efficiency i.e 96.04% and load current is high compare to stage N=1. and load resistor value is high for the lower current. Where if the load current is greter then 1.04A the stage N=3 will be selected because compare to other two stages,the stage N=3 will give high efficiency i.e 97.57% and load current is high compare to other two stages and load resistor value is high for the lower current.as the load current is increases the number of stages will also increases. 62

11 5. CONCLUSIONS This paper presents successfully the analysis of the synchronous buck converter for the different stages are designed by Simulink in mat lab. And in command window we got the efficiency v/s load current graph for the different stages. So when compare all the stages together, stage N=1 is good for the low load current and it gives maximum efficiency compare to other two stages. And for the high load current the stage N=3 is good compare to other two stages. So when the load is increase the numbers of stages will also increases. As the number of stages increases the ripple of output voltage and output current are free. 6. ACKNOWLEDGEMENT The satisfaction and euphoria that accompanies the successful completion of the task would be incomplete without the mention of the people who made it possible. Their constant guidance and encouragement crowned our efforts with success. Primarily, I am deeply grateful to my supervisor Smt. Divya k.pai for his priceless and meticulous supervision at each and every phase of work inspired me in innumerable ways. I specially acknowledge him for his advice, supervision, and the vital contribution as and when required during this research. His involvement with originality has triggered and nourished my intellectual maturity that will help me for a long time to come. I would like to thank our Director Rev Fr Joseph Lobo for providing the institutional support facilities required for completion of the project, and a heart full thank for our beloved Principal Dr Joseph Gonsalvis for his constant support throughout the academics. I would like to thank our Head of the Department, Dr. Pinto Pius A.J and all the teaching and non-teaching staff of our department for their sustained encouragement throughout the task. I am truly grateful to my friends Ameet R.T, Vishnuprasada V Bhat, Shyni R Nambiar, for their well wishes and support. Finally, I want to express utmost gratitude to the invaluable moral and social support extended from none other than my dad Mr. Rama B Harikantra, mother Ms. Sumitra Rama Harikantra,my brother Mr. Prashantha and my sister Shweta and Reshma, for their blessing throughout my studies and without whom this work would not have reached a conclusive stage. My dad is a source of inspiration for me. 7. REFERENCES [1] B. Oraw and R. Ayyanar, Multivariable analysis o f VR controllers with load line r egulation and phase current balancing, in Proc. I EEE APEC 2008, Feb , pp [2] P. Zumel, C. Fernandez, A. de Castro, and O. Garcia, Efficiency im- provement in multiphase converter by changing dynamically the number of phases, in Proc. I EEE Proc. PESC 2006, Jun., pp [3] Y. Panov and M. Jovanov ic, Design considerations for 12V/1.5V, 50A voltage regulator m odules, IEEE Trans. Power Electron., vol. 16, no. 6, pp , Nov [4] K. Yao, K. Lee, M. Xu, and F. C. Lee, Optimal design of the active droop control m ethod for the transient r esponse, in Proc. I EEE Appl. Power Electron. Conf. Expo. (APEC), Feb. 9 13, 2003, vo l. 3, pp [5] K. Yao, Y. R en, J. Sun, K. Lee, M. Xu, J. Zhou, and F. C. Lee, Adaptive voltage position d esign f or vo ltage r egulators, in Proc. 19th IEEE Appl. Po wer Electron. Conf. Expo. (APEC), 2004, vol. 1, pp