PSK Demodulator IP Core Specifcatoon

Transcription

1 PSK Demodulator IP Core Specifcatoon

2 PSK Demodulator IP Core Release Ionformatoon Features Deliverables IP Core Structure Port Map PSK Demodulator IP Core Release Ionformatoon Name Version 2.0 PSK Demodulator IP Core Build date Ordering code Specification revision ip-psk-demodulator r1383 Features The IP core is full-featured digital PSK demodulator. Deliverables IP Core Structure The PSK Demodulator IP Core includes: EDIF/NGC/QXP/VQM netlist for Xilinx Vivado/ISE, Intel (Altera) Quartus, Lattice Diamond or Microsemi (Actel) Libero SoC IP Core testbench scripts Design examples for Xilinx, Intel (Altera), Lattice, and Microsemi (Actel) evaluation boards Figure 1 shows the PSK Demodulator IP Core block diagram. HSP50110 Digital Quadrature Tuner HSP50210 Digital Costas Loop MCU Interface MCU Interface Figure 1. The PSK Demodulator IP Core block diagram The PSK Demodulator consists of a HSP50110 (Digital Quadrature Tuner) and a HSP50210 (Digital Costas Loop). The IP Core is fully compatible with HSP50110 and HSP50210 ICs and is exact FPGA replacement. Port Map Figure 2 shows a graphic symbol, and Table 1 describes the ports of the PSK Demodulator IP Core. 2

3 PSK Demodulator IP Core iclk idati idatq imcu1_addr imcu1_data imcu1_rd imcu1_wr imcu2_addr imcu2_data imcu2_rd imcu2_wr irst odcldati odcldatq odclsofti odclsoftq odclval odqtdati odqtdatq odqtval olock omcu1_data omcu1_datv omcu2_data omcu2_datv ongc1_det Figure 2. The PSK Demodulator port map Table 1. The PSK Demodulator port map description Port Width Description iclk 1 The main system clock. The IP Core operates on the rising edge of iclk. idati idatq 10 ADC samples for demodulation. imcu1_addr 3 HSP50110 MCU address imcu1_data 8 HSP50110 MCU data imcu1_rd 1 HSP50110 MCU read signal imcu1_wr 1 HSP50110 MCU write signal imcu2_addr 3 HSP50210 MCU address imcu2_data 8 HSP50210 MCU data imcu2_rd 1 HSP50210 MCU read signal imcu2_wr 1 HSP50210 MCU write signal irst 1 The IP Core synchronously reset when irst is asserted high. odcldati, odcldatq odclsofti, odclsofti 8 HSP50210 output constellation 3 HSP50210 soft decision odclval 1 HSP50210 output valid signal 3

4 IP Core Parameters PSK Demodulator IP Core odqtdati, odqtdatq 10 HSP50110 output data odqtval 1 HSP50110 output valid signal olock 1 Lock detector signal imcu1_data 8 HSP50110 MCU data imcu1_datv 1 HSP50110 MCU read/write select signal imcu2_data 8 HSP50210 MCU data imcu2_datv 1 HSP50210 MCU read/write select signal ongc1_det 1 Input AGC detector signal IP Core Parameters Table 2 describes the PSK Demodulator IP Core parameters, which must be set before synthesis. Table 2. The PSK Demodulator IP Core parameters description Parameter Description There are no parameters available to change 4

5 IP Core Description Performaonce aond Resource Utliiatoon IP Core Ionterface Descriptoon IP Core Descriptoon Performaonce aond Resource Utliiatoon The values were obtained by automated characterization, using standard tool flow options and the floorplanning script delivered with the IP Core. The IP Core fully supports all Xilinx and Altera FPGA families, including Spartan, Zynq, Artix, Kintex, Virtex, Cyclone, Arria, MAX, Stratix. Table 3 summarizes the PSK Demodulator IP Core measurement results. Table 3. The PSK Demodulator performance IP Core parameters FPGA type Resource Altera Cyclone V 5CEFA ALMs (8%) 2 M10K RAM blocks (1%) 8 DSP (18x18) (6%) Xilinx Virtex-7 XC7VX330T 2588 Slices (6%) 2 18K RAM blocks (1%) 12 DSP (18x18) (1%) Speed grade, maximal system frequency -8, Fmax -7, Fmax -6, Fmax 78.0 MHz 39.0 Msymb/s 90.0 MHz 45.0 Msymb/s MHz 51.0 Msymb/s -1, Fmax -2, Fmax -3, Fmax MHz 62.0 Msymb/s MHz 85.0 Msymb/s MHz 95.0 Msymb/s IP Core Ionterface Descriptoon Description of the interface can be found in the original HSP50110 and HSP50210 user guide from the Intersil (Harris) company. 5

6 Contacts Upgrade aond Techonical Support Feedback Revisioon history Coontacts Upgrade aond Techonical Support Free remote technical support is provided for 1 year and includes consultation via phone, and Skype. The maximum time for processing a request for technical support is 1 business day. For up-to-date information on the IP Core visit this web page Feedback IPrium LLC 39, via Umberto I, Ischitella (FG), 71010, Italy Tel.: +39(334) info@iprium.com Skype: fpgahelp website: Revisioon history Version Date Changes Added CPU interface Official release 6