Open Access Implementation of PSK Digital Demodulator with Variable Rate Based on FPGA

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1 Send Orders for Reprints to 180 The Open Automation and Control Systems Journal, 015, 7, Open Access Implementation of PSK Digital Demodulator with Variable Rate Based on FPGA Xiquan Xia * Institute of Applied Electronics, Chongqing College of Electronic Engineering; Chongqing , China Abstract: Aiming at QPSK modulation digital system with variable rate, a novel implementation method based on field programmable gate array (FPGA) is proposed, which can support 4.88Kbps to Mbps and even higher continuous bit rate. The design adopts mixed multiplier, numerically controlled oscillator (NCO) and integral comb filter (CIC), and describes the structure of carrier recovery circuit and signal recovery circuit, which can be ported to any FPGA device. The proposed design has its hardware test in the Xilinx Virtex-5 FPGA platform. The hardware test results show that the proposed demodulator only takes up 15% available logical unit of Xilinx Virtex-5 FPGA device, revealing superior ability in efficiency. Keywords: Bit rate, Field programmable gate array (FPGA), Modulator, Variable rate. 1. INTRODUCTION With the growing demand for personal communications in the whole world, the using scale of satellite communications has been increasing. Because of its better noise immunity (even at low Eb / N o, it has a lower bit error rate compared to other methods)and regeneration ability, Phase Shift Keying (PSK) can maintain a high quality of communication service(qos), which has become the most commonly used digital modulation technique in satellite communication. In order to meet the users demands for greater bandwidth of voice, video and data communications, advanced inter-satellite communications must support different rates. The demodulator is a critical part of any air and ground communication receivers, which is used to obtain the needed baseband data from modulated signals. In order to achieve the demodulator with Mbps or even higher digital rates, the FPGA can be used to implement variable rate demodulator. The simulation and implementation of current digital demodulators are only for data rate at Mbps. However, through rational choice of sampling frequency, higher speeds can be achieved using the current structure of the demodulator. Literature [1] has proposed a QPSK digital demodulator to complete the demodulation of QAM modulation by adjusting the circuit structure of demodulator; Literature [] has put forword a digital demodulator without changing the circuit configuration to demodulate QPSK and 8PSK; Document [3] proposed a high-speed digital demodulator with parallel configuration, which can work quickly to achieve QPSK demodulation. However, these all are for fixed-rate, and the rate is lower than Mbps. *Address correspondence to this authors at the Institute of Applied Electronics, Chongqing College of Electronic Engineering; Chongqing , China; Tel: ; xiaxiquan1969@163.com The article designs a variable rate QPSK demodulator based on FPGA, and verifies VC707 evaluation board of the Xilinx Virtex 5 FPGA family. The design adopts hybrid multiplier, numerically controlled oscillator (NCO) and integralcomb(cic), and gives the design structures of carrier and signal recovery circuit. The system may support 4.88Kbps to Mbps and even higher continuous bit rate. As a stand-alone design structure, it can be ported to any FGPA platform. Hardware implementation results show that the proposed demodulator only takes 15% of the available logic cells in a Xilinx Virtex-5 FPGA devices, revealing superior efficiency.. PRINCIPLE OF PSK COMMUNICAITON SYSTEM Fig. (1) shows the basic schematic of a typical satellite communication PSK system. It contains the source coding of baseband data, carrier phase modulation and AWGN channel(a communication medium between the antenna and the terminal, RF signal transmission model)[4]. Fig. (1). The basic block diagram of an exemplary PSK communication system. A reverse process is demanded to obtain the baseband data at the receiving end. The demodulated data can be realized through the regeneration or an analog or digital receiver. The digital implementation of demodulator should prefer to choose the method in literature [5] because digital demodulator is programmable and faster timing recovery compared to analog demodulation. Table 1 shows the technical parameters of QPSK demodulation. According to the central value in the spectrum of the / Bentham Open

2 Implementation of PSK Digital Demodulator The Open Automation and Control Systems Journal, 015, Volume modulated signal of the processing inverted image, the sampling frequency is set to 70MHz. Table 1. Technical parameters of the demodulator. IF center frequency ADC sampling frequency IF power QPSK modulation Signal mode Symbol rate FEC decoding mode Phase ambiguity resolution method Judgment Type 70MHz 40 Mbps -5dBm -0dBm QPSK continuous signal 4.88Kbps to Mbps Viterbi decoding by different encoding and decoding methods 3-bit soft decision 3. PROPOSED DESIGN OF THE DEMODULA- TOR Fig. () shows a block diagram of the digital QPSK demodulator design proposed. It includes three tracking loops: automatic gain circuit (AGC), carrier acquisition/tracking loop and symbol tracking loop. The tracking and adjustment of AGC loop changes from the variation of input signal power caused by path loss. Carrier tracking loop can eliminate the uncertainty of carrier frequency and phase(due to the instability of the oscillator, the phase elimination in symbol tracking loop, frequency uncertainty of data and the clock synchronization of the receiving data) [6]. A finite state machine is used to select the mode of capture or tracking, and selects and outputs of false lock and solid lock. 4. DESIGN OF NUMERICALLY CONTROLLED OSCILLATOR AND MIXER The design of a numerically controlled oscillator (NCO) is used to generate sine and cosine carrier [7], binding with the input data after digital modulation. Sinusoidal signals are used as phase components, and cosine signal for generating a quadrature component of a complex signal [8]. Fig. (3) shows the design of the structure of NCO. Phase jitter is for obtaining better frequency response. Table shows the technical parameters of NCO. In the vicinity of the carrier frequency of dependent channel, mixer multiplies digitized input data samples and synthetic carrier, so as to put the needed channel into the Fig. (). Proposed structure of digital PSK demodulator. Fig. (3). The design structure of NCO in FPGA.

3 18 The Open Automation and Control Systems Journal, 015, Volume 6 Xiquan Xia Table. Technical parameters of NCO. The bandwidth of second-order phase-locked loop B n is: baseband range. The output of the mixer contains both the and value and difference value of frequency components in the input sampling frequency. In order to verify the design proposed in this article through hardware, the mixer must work under the sampling frequency of ADC in the structure. Table 3 below shows the technical parameters of the mixer. Table 3. Sampling frequency Phase increment byte length Output bit width IQ carrier frequency Technical parameters of the mixer. Input data bits Carrier bit ADC sampling frequency Carrier center frequency 5. DESIGN OF LOOP FILTER 10bits 10bits 40MHz 10MHz The loop filter in the demodulator structure proposed is a second order lag filter, as shown in Fig. (4). Filter transfer function is: Fig. (4). Digital loop filter. 40MHz 3bits 10bits 10MHz F (z ) = C 1 + C!1 (1) 1! z! B n = " H (w) df = w # n! + 1 & $ % 4! ' 0 ( () According to the loop bandwidth of carrier and symbol tracking loop, loop filter coefficients can be calculated by the following formula: C C 1 8ξ wt 1 = KK o d 4+ 4 ξ wt + ( wt ) 4( wt ) 1 = KK o d 4+ 4 ξ wt + ( wt ) In which, wn is the natural frequency of the loop, Tsamp is the sampling interval, ξ is the damping coefficient, Ko and K are the gain for the NCO and mixer. d 6. DESIGN OF CIC AND RRC FILTER In the proposed structure of the digital demodulator, two functions are needed to further process the signal: low-pass filtering and sampling. Low-pass filtering must be immediate after the mixer in order to eliminate unwanted signal frequency caused by the mixing function. Sampling is to reduce the input sample rate, so as to reduce the process of required release signal to the maximum extent for the subsequent stages [9]. CIC filter is a very efficient method of sampling implementation [10]. Fig. (5) shows the structure of the CIC filter, which comprises N cascaded integrators (locked sampling frequency f s ), rate changing factor R, N cascaded comb stages(operating frequency is fs / R), wherein N is the specific number or the order of filter. CIC filter is an efficient hardware filter structure for performing filtering function with shift register and adder only [5]. The filter has a frequency response function, which is shown below. sin( π fr) HCIC ( f) = k sin( π f ) Wherein, f is the normalized frequency relative to the input sampling rate, and k is the filter gain and R is the sampling rate. The pass bandwidth of the filter can be controlled by 3 (3) (4) Fig. (5). Structure diagram of CIC sampling filter.

Implementation of PSK Digital Demodulator The Open Automation and Control Systems Journal, 015, Volume 6 183 Table 4. Technical Parameters of CIC Filter.

4 Implementation of PSK Digital Demodulator The Open Automation and Control Systems Journal, 015, Volume Table 4. Technical Parameters of CIC Filter. Input sampling frequency f s 40Mbps N 3 this paper, and simulation of performance function uses Questa Sim 10.0b which is matched with Xilinx Virtex-5 FPGA. Fig. (7) shows the implementation of hardware test system of the proposed design, including COMTECH modem for modulated input, Tektronix TLA501B logic analyzer for capturing and observing the output of demodulator. Delayed a check points 1 Sampling factor R sampling factors [11], and R can be adjusted to provide a flexible demodulation bandwidth to match symbol boundary. The technical parameters of the filter are shown in Table 4. In order to compensate for the band tilt, a programmable finite impulse response filter(pfir) is used after CIC filter. The accuracy of the density factor can be developed within the range from 1 to 3bits. Figure 6 shows the CIC filter response compensated when the symbol rate is Mbps. In order to increase the signal to noise ratio (SNR) to achieve better signal estimation, the root cosine filter is applied as a matched filter in the demodulator. The amplitude response of raised cosine filter is: 1 α Ts, f Ts πt s 1 α 1+ α H( f) = Ts cos f, f α T s Ts 1+ α 0, f > Ts (5) In which, T s indicates the interval of unit symbols,! expresses roll-off factor and is set to 0.35 in the system implementation. 7. EXPERIMENTAL RESULTS AND ANALYSIS The whole design is realized through Verilog HDL 001, and without FPGA IP cores, so the proposed design belongs to independent platform that can be applied to any FPGA module such as Xilinx and Actel. Nevertheless, Xilinx- ISE9.i is used in the FPGA implementation experiment in Fig. (7). Diagram of hardware test system. Simulink models are used to simulate different parameters of the design, making it easier to complete the hardware implementation. Fig. (8) shows the phase constellation diagram and eye diagram at port 4 of demodulator when the symbol rate is Mbps. Fig. (9a) shows phase error response of carrier tracking loop between the input and the local carrier in the condition of closed loop. Fig. (9b) shows the theoretical value and the simulation value of BER when the symbol rate is Mbps. PSK coding system reaches the realization margin of 0.5dB and the coding gain is approximately 5dB. Fig. (6). CIC filter response compensated.

(9a). Carrier phase error of the locking carrier tracking loop. Fig.

5 184 The Open Automation and Control Systems Journal, 015, Volume 6 Xiquan Xia Fig. (8). QPSK constellation and eye diagrams. Fig. (9a). Carrier phase error of the locking carrier tracking loop. Fig. (10) shows the FFT plot of point by 70MHz carrier after ADC and 40Mbps sampling. The spurious-free dynamic range (SFDR) is larger than 50dB, which can be seen in that the performance of demodulator is independently distributed in relation to the ADC dynamic range.

Implementation of PSK Digital Demodulator

(10). FFT plot with ADC characteristics. Fig.

6 Implementation of PSK Digital Demodulator The Open Automation and Control Systems Journal, 015, Volume Fig. (9b). BER curves of carrier tracking loop. Fig. (10). FFT plot with ADC characteristics. Fig. (11). Functional simulation results of digital demodulator.

7 186 The Open Automation and Control Systems Journal, 015, Volume 6 Xiquan Xia Modulated signal should go through the ACD Analog Devices AD9054A integrated by Xilinx development board, and capture its output by the logic analyzer. The data is stored in the ROM of FPGA, and used as the simulation input of the entire design. The result of Questa Sim 10.0b is shown in Fig. (11), which shows the output signal at different stages of the digital demodulator. The simulation results include modulated signal input when phase-error is in locked state, combined carrier of NCO, output of mixer, output of digital ADC and output of CIC filter. CONCLUSION This paper presents a hardware efficient QPSK digital demodulator structure. The design uses a programmable data rate, which is applicable to advanced satellite communication system. Proposed hardware architecture occupies only 15% of the overall chip resources of Xilinx Virtex-5 FPGA hardware platform, and the presented design is platformindependent, which can be transplanted at any targeted FPGA. CONFLICT OF INTEREST The authors confirm that this article content has no conflict of interest. ACKNOWLEDGEMENTS Declared none. REFERENCES [1] D. Xiang, H. Zhang, and Z. Li, A Simple FPGA Implementation Structure of Symbol Timing Estimator for QPSK Demodulation of Telemetry Receiver. Computer Measurement & Control, vol. 1, no. 9, pp , 013. [] Y. Zhu, An Anti-false-lock Optimization Method on Carrier Recovery Loop of QPSK Demodulation, Radio Communications Technology, vol. 38, no. 1, pp , 01. [3] R.V.D. Wal, QPSK and BPSK Demodulator chipset for satellite applications, IEEE Transactions on Consumer Electronics, vol. 41, no. 1, pp , [4] N.C. Shivaramaiah, A.G. Dempster, and C. Rizos, Time- Multiplexed Offset-Carrier QPSK for GNSS, IEEE Transactions on Aerospace and Electronic Systems, vol. 49, no., pp , 013. [5] R. Rodriguez-Gomez, E.J. Fernandez-Sanchez, J. Diaz, and E. Ros. FPGA implementation for real-time background subtraction based on Horprasert model, Sensors, vol. 1, no. 1, pp , 01. [6] Y. Linn, A self-normalizing symbol synchronization lock detector for QPSK and BPSK, IEEE Transactions on Wireless Communications, vol. 5, no., pp , 006. [7] Y. Zhang, Z.X. Ouyang, and Y. Deng, New high performance non-data-aided frequency estimation and implementation of QPSK, Journal of Xidian University (Natural Science), vol. 40, no., pp , 013. [8] S. Mao, B. Zhu, and Y. Wang, Coherent reception technology based on DSP in 100Gbit/s DP-QPSK system, Laser & Infrared, vol. 43, no. 1, pp , 013. [9] X. Lv, L. Wang, and D. Xu, Analysis of Optical Phase-locked Loop for Coherent Optical communication based on QPSK modulation, Journal of Changchun University of Science and Technology (Natural Science Edition), vol. 36, no. 3-4, 013. [10] L. Fang, R. Zhang, and L. Li, Verilog HDL Model and Functional Simulation of QPSK Modulation and Demodulation, Journal of GuiZhou University (Natural Science Edition), vo1.30, no. 6, pp , 013. [11] Z. Zhou, and Y. Xu, QPSK modulation and demodulation system design and simulation based on VHDL, Electronic Design Engineering, vol. 1, no. 9, pp , 013. Received: January 06, 015 Revised: April 04, 015 Accepted: May 15, 015 Xiquan Xia; Licensee Bentham Open. This is an open access article licensed under the terms of the Creative Commons Attribution Non-Commercial License ( licenses/by-nc/4.0/) which permits unrestricted, non-commercial use, distribution and reproduction in any medium, provided the work is properly cited.

Research on DQPSK Carrier Synchronization based on FPGA

Journal of Information Hiding and Multimedia Signal Processing c 27 ISSN 273-422 Ubiquitous International Volume 8, Number, January 27 Research on DQPSK Carrier Synchronization based on FPGA Shi-Jun Kang,