Simulation Study for the Decoding of UHF RFID Signals

Transcription

1 PIERS ONLINE, VOL. 3, NO. 7, Simulation Study for the Decoding of UHF RFID Signals Shengli Wang 1, Shan Qiao 1,2, Shaoyuan Zheng 1, Zhiguang Fan 1 Jiangtao Huangfu 1, and Lixin Ran 1 1 Department of Information and Electronic Engineering, Zhejiang University Hangzhou , China 2 Zhejiang University City College, Zhejiang University Hangzhou , China Abstract In this paper, we present a simulation model for the decoding of the UHF (Ultra High Frequency) RFID (Radio Frequency IDentification) signals utilizing MATLAB/Simulink. A digital phase-locked loop (DPLL) was designed for recovering the external clock which is used for the bit synchronization and sampling. The IDs are well recovered under the existence of an additive signal noise ratio (SNR). DOI: /PIERS INTRODUCTION Radio Frequency Identification (RFID) is a technology using radiated and reflected RF power to identify a variety of objects. A typical RFID system consists of a transceiver, or RFID reader, and a transponder, or tag. Generally, an RFID reader includes an RF transmitter, one or more antennas and an RF receiver. A generic RFID tag consists of a microchip attached to an antenna. In a UHF RFID system, communication between the reader and the transponder is via backscatter reflection [1, 2]. According to the Class 1, Gen 2 UHF Air Interface Protocol Standard [3], the return link data from the transponder to the reader is encoded by a scheme of Bi-phase space (FM0). Figure 1 illustrates the basic functions of the FM0 data coding. FM0 inverts the baseband phase at each symbol boundary, and a bit 0 has an additional mid-symbol phase inversion. Figure 1: Fm0 data coding. In this paper, a decoding model of the UHF RFID signals is described by use of MATLAB/ Simulink [4]. In the simulation model, a DPLL is designed for recovering the external clock which is used for bit synchronization and sampling. Sub-blocks of the decoding model are described in detail, and the results of the simulation model are presented under the existence of an additive signal noise ratio (SNR). 2. DECODING MODEL DESCRIPTION Figure 2 is the simulation environment of the decoding model realized in Simulink. In the FM0 Code Generator block, the state machine produces a digital stream carrying a random noise based on the communication protocol implementation. The stream enters into the FIR (Finite Impulse Response) block to filter out the noise. The digital phase-locked loop (DPLL) was designed for recovering an external clock from an input serial data stream directly. Then the signal is sampled by the synchronization clock coming from the DPLL and is converted to a bit stream described by

2 PIERS ONLINE, VOL. 3, NO. 7, binary digit 0 or 1. The Decoding block is used to finally recover the source IDs. The outputs from the FM0 Code Generator block and the Decoding block are simultaneously sent to the Error Rate Calculation block, to compute the Bit Error Rate (BER). The Scope and Display blocks are used for demonstraing the results of the simulation. Figure 2: Top-level block diagram of the decoding model in this paper. 3. FM0 CODE GENERATOR MODULE Figure 3 shows the basic blocks of the FM0 Code Generator Module in Simulink. The Bernoulli Binary Generator block generates a 40 kbps random binary stream satisfying a Bernoulli distribution. The FM0 Encoding block is an S-functions (system-functions) block, providing a powerful mechanism for extending the capabilities of Simulink. In this paper it was written in M-language of MATLAB. The Band-Limited White Noise block produces normally distributed random numbers that are suitable for the use in continuous or hybrid systems. Finally, the output of this module is a sumation of the above two with a constant offset of 0.5. Figure 4 shows the waveform produced by this module. Figure 3: Implementation of the FM0 Code Generator Module.

3 PIERS ONLINE, VOL. 3, NO. 7, Figure 4: Waveform of the FM0. 4. DPLL MODULE The block diagram of the digital phase-locked loop (DPLL) used to directly recover the external clock from the input stream is shown in Figure 5. The Local Clock block produces two clocks with a phase difference of π, and both with the frequency f0 equals mrb, where Rb is the data rate of the input stream and m is the dividing factor of the divider. The input data stream passes through the Edge Detector circuit and was converted to a narrow pulses sequence. The gate AND1 will be a pulse output when the phase of the said narrow pulses sequence lags the divider s clock pulse output, then it will be added to the divider through the Controller circuit to add a clock pulse which will be divided by the divider, in order to adjust the phase of the clock output. If the phase of the said narrow pulses leads the said clock pulses, the gate AND2 will be a pulse output which will employ the divider to minus a clock pulse to make the clock output a little delay. Until the Phase Comparator has no pulse output, the loop is locked. Figure 6 is the simulation results of the DPLL, in which the lower waveform is the clock recovered from the input steam. Figure 5: Simulation blocks of the DPLL. 5. SIMULATION RESULTS As shown in Figure 7, the IDs are well recovered from the noisy FM0 code stream. Comparing with the source IDs, the recovered just have a time delay. In the simulation, we adjusted the noise power in the model to obtain the Bit Error Rate (BER) by the Error Rate Calculation block. The

4 PIERS ONLINE, VOL. 3, NO. 7, Figure 6: The input stream and the recovered clock of the DPLL. Figure 7: Waveforms of the simulation results. results (not shown in this paper) indicate that when the SNR > 1.0 db, the BER is still zero, which implies a good performance of the simulation proposed in this paper. To verify the simulation aforementioned, we collected the baseband data from a real UHF RFID reader, as shown in Figure 8, where Figure 8(a) is the waveform of the digital signal that was sampled from the ADC, and 8(b) shows the waveform of the data that was filtered by the FIR filter. Then the data steam was imported into the simulation environment as a block instead of the FM0 Code Generator module. It was finally decoded successfully with the simulation model. (a) (b) Figure 8: The baseband signal from the DSP, (a) Signal data form the ADC, (b) The filtered waveform. 6. CONCLUSION A simulation environment for the decoding of the UHF RFID signals has been discussed in this paper. A DPLL module was designed in the simulation model for recovering the synchronous clock, and the results of the simulation show that the ID can be well decoded whether the FM0 code stream is provided by the Simulink module or it was sampled from an actual RFID reader. Such simulation model has been realized in a TI C54X series DSP of a UHF RFID reader. ACKNOWLEDGMENT This work is supported by ZJNSF R105253, and in part by NSFC and

5 PIERS ONLINE, VOL. 3, NO. 7, REFERENCES 1. Landt, J., The History of RFID, IEEE Potentials, Vol. 24, No. 4, 8 11, Oct. Nov Finkernzeller, K., RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification, second edition, Wiley and Sons, NJ, Class 1 Generation 2 UHF Air Interface Protocol Standard Simulink manual from