Cascading Techniques for a High-Speed Memory Interface

Transcription

1 Session 12.7 Cascading echniques for a High-Speed Memory Interface Zheng Gu, Peter Gregorius, aniel Kehrer, Lydia Neumann, Evelyn Neuscheler, homas Rickes, Hermann Ruckerbauer, Ralf Schledz, Martin Streibl, Juergen Zielbauer Qimonda AG, Munich

2 Outline rade-off channel bandwidth vs. density repeater architectures ransparent Repeater estchip Measurement Results Summary

3 Interface atarate Roadmap transition single-ended to differential signaling

4 Example for R3 Multidrop Configuration Problems with multidrop channels (reflections, crosstalk, etc.) North Bridge

5 Challenge for Post-R3 increase peak bandwidth x Gbps for single ended I/Os Gbps for differential I/Os given byfixed connector pin count increase density - Need to have up to 72 devices per IMM (e.g. for Servers) => problem with point-to-point signaling

6 Alternative Approach: repeater cascade of s, commands and is piped through the chain IMM with multi-drop connections cmd,, IMM with repeater s cmd,,

7 Repeater System View power, repeat latency, circuit complexity rade-off jitter accumulation, signal integrity

8 Repeater estchip transparent repeat resample path RXp RXn RX amp ctrl<63:0> serial control interface I/Q sampler phase interpolator 1:2 freq. divider serializer selector ring oscillator Predrv Rank5 Rank2 X drv Xp Xn global clock buffer half rate clock trunk Rank1 Rank0 L6 6.5mm L5 L4 L3 L2 L1 CL 1cm

9 Repeater estchip transparent repeat transparent repeat resample path RXp RXn RX amp ctrl<63:0> serial control interface I/Q sampler phase interpolator 1:2 freq. divider serializer selector ring oscillator Predrv Rank5 Rank2 X drv Xp Xn global clock buffer half rate clock trunk Rank1 Rank0 L6 6.5mm L5 L4 L3 L2 L1 CL 1cm

10 Repeater estchip transparent repeat resample path RXp RXn RX amp ctrl<63:0> serial control interface resample path global clock buffer I/Q sampler phase interpolator 1:2 freq. divider serializer selector ring oscillator half rate clock trunk Predrv Rank5 Rank2 Rank1 Rank0 L6 X drv 6.5mm Xp Xn L5 L4 L3 L2 L1 CL 1cm

11 Repeater estchip: Reveiver Amplifier

12 Repeater estchip: Pre-river and Offchip-river (OC)

13 ie Photograph of a Single ata Repeat Lane

14 estboard Photographs op View Bottom View

15 ata Eyes vs. Rank in ransparent Repeat L6 Rank0 L5 L4 L3 L2 L1 CL Rank1 Rank2 Rank3 Rank4 Rank5

16 Eye Opening resolved by the sampler vs. Rank #

17 Important Issue : evice Mismatch Effects in Clock istribution Path transparent repeat resample path RXp RXn RX amp ctrl<63:0> I/Q sampler serializer selector Predrv X drv Xp Xn serial control interface global clock buffer phase interpolator 1:2 freq. divider ring oscillator half rate clock trunk # of samples Eye1_meas Eye1_sim 0 70% 80% 90% 100% 110% 120% 130% Eye width (UI)

18 Impact of Clock Path evice Mismatch => Needs correction circuits or increased transistor size (power!) # of samples % 80% 90% 100% 110% 120% 130% Eye width (UI) Eye1_meas Eye1_sim standard deviation = 9% UI (7% UI from the clock generator)

19 Sampler Eye Characterisation vs. Rank # receiver offset shmoo phase interpolator shmoo clock vs. offset shmoo clock-to- shmoo PI R0 R1 R2 R3 R4 R5

20 Sampler Eye Characterisation vs. Rank # offset shmoo clock-to- shmoo PI R0 R1 R2 R3 R4 R5 Rank 2 Rank 3 Rank 4 Rank 5 5.3Gbps phase interpolator setting shmoo (60 steps) receiver offset shmoo -200mV mV

21 Power & Latency Comparison Functional Block RX Amplifier Sampler Serializer Selector / Predriver X Buffer (@ 50Ohm ermination) Global Clock runk per Lane 1:2 ivider, CML-2-CMOS, CC Phase Interpolator otal Current Consumption Latency Rank to Resample Mode 3mA 8mA 4mA 7mA 16mA 11mA 6mA 5mA 60mA 1.5ns ransparent Mode 3mA - - 7mA 16mA 11mA mA 280ps

22 Conclusion demonstrated a transparent repeater chain of 6 ranks - standard process - standard single-layer wire-bond package achieved up to 5.3Gbps with a BER<1e-14 transparent repeater mode - consumes 40% less power - has 80% less latency attractive option to increase memory density for a differential point-to-point high-speed interface