Discrete-Time Analysis of an All-Digital and Multirate Symbol Timing Recovery Scheme for Sampling Receivers

Transcription

1 Discrete-Time Analysis of an All-Digital and Multirate Symbol Timing Recovery Scheme for Sampling Receivers Mehmet R. Yuce,, Ahmet Tekin, and Wentai Liu Dept. of Electrical Eng., University of Newcastle, Callaghan, NSW, Australia Dept. of Electrical and Comp. Eng., University of California at Santa Cruz, Santa Cruz, CA , USA Abstract An all-digital symbol timing recovery technique that uses a -bit ADC, delay-xor unit and a digital prefilter before the all-digital loop is analyzed. This approach provides a lowpower, all-digital implementation in CMOS integrated circuit and exhibits very low jitter. The prefilter is arranged to eliminate frequency offsets on the input signal. The system is robust against fast and large Doppler shift and is therefore well suited for receivers in satellite applications. A symbol timing circuit based on this technique has been implemented for a wide range of bit rates (0.-00 Kbps). It is synchronized within 3 or 4 bits in the presence of high carrier frequency offsets. A detailed performance study is carried out by both analytical simulation and hardware implementation to provide guidelines when the proposed scheme is applied to other transmission systems. I. INTRODUCTION Many forms oymbol timing recovery (STR) circuits have been used in digital communication for synchronization. The most common traditional STR circuits are square-law [], maximum-likelihood [][3] and early-late gate [3]. However, the implementations of these STR circuits are complex and costly. They require longer synchronization time and therefore are not well suited for burst transmission. To take advantage of low-power and flexibility, it is desirable to implement STR circuits all-digitally. All digital approach eliminates the issues in analog design such as mismatch, non-linearity and parasitics. All-digital or partially digital approach of PLL to implement in STR circuits has also been studied extensively [4]-[7]. However, they cannot be employed directly in digital communication systems where there exists fast Doppler rate. This paper analyzes a digital STR circuits for low-cost and low timing error for sampling receivers in space communications. The proposed STR circuit consists of a -bit A/D converter (ADC) at the front to convert analog signal to digital NRZ signal, a delay unit together with exclusive-or (XOR) gate to detect transitions, a prefilter to eliminate frequency error, and then an all-digital PLL (ADPLL) feed back system. In addition, the circuit is designed for multiple bit rates and is programmable to extract the timing clock from either a phaseshift keyed (PSK) modulated signal or a demodulated baseband signal by using a serial XNOR or XOR gate, respectively. The simulation and measurement results show that the circuit is synchronized within 3 or 4 bits and exhibits low-cost, low jitter and low-timing error. An example of this STR technique has been implemented in SOI CMOS technology and the chip level measurement results have been presented in [8]. PSK Signal r (t) CR: Carrier Recovery STR : Symbol Timing Recovery BPF r (k ) ADC r(k) J n Accumulator STR CR Sgn 90 0 s Figure. A block diagram of the digital BPSK demodulator with symbol timing recovery Although using the delay-xor unit to obtain transition pulses before a PLL has been employed before in [4], the PLL used was based on discrete components that were analog, while the PLL in the proposed STR implementation is all-digital and a digital control oscillator (DCO) is used instead of a VCO. As a particular case, the design in this paper focuses on the implementation of the proposed technique in the CMOS integrated circuit (IC). Currently all-digital PLL s (ADPLL s) are replacing rapidly conventional analog PLL s because they are more flexible and can be on-chip with other communication circuits [6][7]. An all-digital PLL version in STR consumes ultra-low power and takes up minimal area. It is also easy to design a loop filter with adaptive bandwidth in digital domain for fast synchronization. Combining all these and having the feature of robustness against Doppler shift, the proposed STR circuit is especially well suited for receivers in space applications. Herein, we demonstrate the performance of the proposed STR with various simulation and circuit results as well as some mathematical analysis. Unique features of the proposed techniques are fast synchronization (3, 4 bits) under high frequency offsets, low jitter, the multirate implementation in CMOS and flexible input signal selection. II. ALL-DIGITAL MULTIRATE SYMBOL TIMING RECOVERY Although the proposed symbol timing recovery technique and its analysis can be applied to other digital modulated systems, we will consider it for a PSK modulated channel. As an example, a sampling Binary PSK (BPSK) receiver with symbol timing recovery is illustrated in Fig.. As shown in this configuration, the symbol-timing clock can be recovered by using either the digital PSK signal or the demodulated output signal. I n Q n J n

2 Signal in r (t) -Bit ADC f i Digital PLL Additional Components s(k) s(k) z (k) y(k) up Digital loop Prefilter Delay PFD dn filter Jn S T τ s d (k) Output Clock N Freq. Divider DCO Figure. Proposed timing recovery system with additional components to recover multirate clock via all digital PLL. The block diagram of the proposed symbol timing recovery circuit is illustrated in Fig.. To analyze this STR circuit assume that the input is a phase-modulated sine wave. The input waveform to the ADC can be described as r ( t) = A cos(π ( f i + f ) t + φi ( t)) + n( t) () where A is the amplitude of the signal, f i is the input signal frequency which is usually a carrier frequency f c or a down converted IF frequency f IF, f is the frequency offset generally caused by Doppler as well as oscillators instability, the information is modulated on the phase φ i, and n(t) is additive white Gaussian noise (AWGN) from the communication channel. In sampling front-ends, the carrier is either sampled directly or is down converted to an intermediate frequency (IF) via one-stage analog down conversion and then sampled by the ADC (IF-sampling). The final down conversion is done in the digital domain in sampling receivers (Fig.). The - bit ADC is used at the front-end of the proposed STR to convert the input analog signal to digital non-return to zero (NRZ) signal. Then the rest of the circuit is realized alldigitally. The bit ADC is ideally suited for deep-space communication due to the absence of interference signals. Furthermore, the -bit ADC (i.e. hard-limiter) has been widely used as a part of many satellite transponders [9],[]. The sampling frequency is chosen as =4 f i /(n+), () where n is an integer number. The principal motivation behind this sampling rate is that it reduces the hardware complexity when employed at the front-end of receivers [8][9][0]. The sampling clock is assumed to be generated from the local oscillator (LO) frequency that is available at the front-end of sampling receivers. In case of n >, the input signal will be sampled with a frequency lower than the Nyquist rate (i.e. subsampling) [0]. To avoid aliasing, the sampling frequency must be at least twice the data rate (i.e. f b ) or the bandwidth of band pass filter (BPF) used at the front-end. Here we assume the input signal is a PSK modulated signal (i.e. f i = f b ) rather than a demodulated signal. After being sampled at t=kt s, the signal () will be given by f r ( k ) = A cos{( n + ) π k / + π k + φi ( k )} + n( k ) (3) f s The analog signal is actually -bit quantized (i.e. hardlimiting) to obtain NRZ data s(k). At the output of the -bit ADC, the signal can be written as if r ( k ) 0 s ( k ) = sgn( r ( k )) = (4) 0 if r ( k ) < 0 As can be seen from (4), the signal at the output of -bit ADC is a digital NRZ signal, whether the input is a PSK signal or demodulated baseband signal. The multiplexer used after the ADC selects one of these input signals. The transition pulses in z(k) are generated from s(k) with the circuit illustrated in Fig. 3. The NRZ signal s(k) and the delayed replica s d(k) are multiplied to obtain a modified returnto-zero (RZ) signal z(k) (e.g. Z(t)=S(t).S(t-τ)). Since the term π( f/ )k and the AWGN noise in (3) cause variation in pulse duration o(k) after the ADC, they will create some error pulses between two transition pulses in z(k) (Fig.4). These error pulses are eliminated by Prefilter before the loop. The Prefilter is a digital narrow band filter that eliminates pulses with the duration smaller than τ = mt s. The signal at the output of the Prefilter is shown in Fig. 4, which is the same as z(k) with no errors pulses. Finally, all-digital PLL derives symbol timing clock from the cleaned signal y(k). The goal of the Prefilter here is to eliminate effect of frequency offsets on the input signal via delay-xor. To calculate the power spectrum of the transition pulses y(k), assume its waveform in time domain can be given by y( t) = s ( t nt ) (5) T b n = where T b is the bit period and h( t nt ) with probability b s ( t nt ) = (6) T b 0 with probability The waveform h(t-nt b ) is described as the following: nt < + = b t ( ntb τ ) h( t ntb ) (7) 0 ( ntb + τ ) < t ( n + ) Tb Output Clock y(k) z(k) s(k) Digital PSK Signal (r(k)) s (k) f i FF FF Delay unit FF m Figure 3. Implementation of the delay unit Output of Prefilter τ = mts = mt s 0 Transition z (k) pulses To Timing circuit τ = mt s Figure 4. Timing diagram of the STR circuit for a PSK input signal The transition pulses are obtained when a transition occurs in adjacent two symbols such as 0 or 0. There will be no transition pulses for 00 or which is indicated in Eq. (6).

3 where τ is the width of the transition pulses obtained from the delay element depicted in Fig. 3. The power spectral density of y(t) in (5) is given by [4][3] Y ( f ) = ( Tb ) H ( f ) + ( Tb ) H (0) δ ( f ) + 4 ( Tb ) (8) + H ( k / Tb ). δ ( f k / Tb ) k = where + j π ft jπ fτ H ( f ) = h( t ntb ) e dt = τ sin c( π fτ ) e (9) By substituting the above equation into (8), the power spectral density becomes Y ( f ) = (τ / Tb ) sin c ( π fτ ) + ( τ / Tb ). + + kπτ (0) δ ( f ) sin c ( ). δ ( f k / Tb ) k = Tb Delaying and multiplying (using XOR or XNOR), the input signal yields discrete spectral lines at the symbol rate frequency, which is the last term in (0). A. Selection of the Delay, τ The delay is selected as mt s, where m is the number of flipflops (FF s) used in the delay unit shown in Fig. 3. Unlike the previous designs [4][5], herein the delay duration should be equal to the half period of the digital PSK signal (mt s =T c /). As a result, the error pulses or jitter pulses in z(k) will result only from the frequency offsets in the PSK signal s(k) as well as from AWGN. Therefore, the selection of the delay in this design is different from those given in [4][5] where the input was assumed a demodulated NRZ bit signal. The prefilter passes only the transition pulses with the width of mt s and eliminates all unexpected error pulses that may appear between two transition pulses due to the effect of Doppler shift on the input PSK signal. The largest error pulse should be guaranteed to be less than mt s for the worst-case Doppler shift, which is the case in all space communications. B. Evaluation of Transition Pulses and SNR The digital phase-lock loop part of the STR circuit behaves as a narrow-band tracking filter (with bandwidth = BW Loop ) and recovers data clock from the signal Y(f ). Note that since the clock is extracted after two-narrow band filtersthe prefilter and the loop of PLL, the contribution of the wide band Gaussian noise is significantly smaller than that of the discrete spectrum in Y(f ) and hence can usually be neglected. This assumption is valid by looking at the time domain as well since any significant error pulse between two transition pulses caused by AWGN will be eliminated by employing prefilter as explained in Fig. 4. To analyze the transition pulses in a real application, we replaced a small pad between the prefilter and the PLL in the implemented CMOS chip. The measured frequency response of the random transition pulses from the implemented chip proves that the noise level is extremely lower than that of the discrete data spectrums plotted in Fig. 5. This measurement y(k) Transition pulses in Time domain a) Y(f) Frequency Domain b) - 60 db BW loop f b /T b /T b 3/T b.... T b =0 T s µs f b =/T b =00 khz Sinc envelope (as calculated in Eq.(0)) Noise level Figure 5. Transition pulses in time and frequency domain for a random data of 00 Kbps. This measurement result is obtained from a probe pad placed at the output of the Prefilter in the test chip. Sampling frequency is 4MHz. shows waveform of the transition pulses and its frequency spectrum for a random data rate of 00 Kbps. The power spectrum of y(k) shows the existence of discrete spectral lines at multiples of the data rate frequency because the pulses are repeated every period of data rates. The distance between two pulses is 0 µs and pulse duration is equal to T s = 0.5µs (Fig. 5-(a)). The amount of delay is τ = T s = 500 ns. In the frequency domain, the distance between two discrete spectral lines is /T b =00 khz, as can also be seen in (0). Note that the symbol timing clock information is contained in these discrete spectral lines at /T b (Fig. 5-(b)). The bandwidth of the PLL, BW Loop simply defines the signal-to-noise ratio (SNR) and thus the jitter performance. The jitter that is calculated via SNR (i.e. t j SNR f b /BW loop ) [5][6] has to be taken into consideration when the system is employed for high speed applications. The jitter performance of an alldigital timing recovery has been extensively analyzed in [5]. It has been shown that a system using XOR-delay and then all digital PLL exhibits extremely lower jitter. In fact, adding a prefilter before the loop requires additional analysis for such systems; we refer [5] for theoretical jitter performance analysis. Although the goal of the prefilter here is to eliminate the effect of frequency offsets on the input signal via delay-xor, it has additional advantage of reducing jitter by rejecting lowfrequency additive Gaussian noise as well as other possible higher frequency components in the system [][3]. This system is thus very suitable for high-speed applications where the jitter is a fundamental issue in the PLL. C. Stability Analysis of All-Digital Multirate STR In this section, we will examine the stable condition of the proposed technique. In order the PLL support a multiple set of data rates, an initial timing synchronization is needed at the beginning when each time data rate is changed in order to distinguish two consecutive data rates. This is accomplished via transmission of a preamble sequence as a packet header in the information. In addition, a phase-frequency detector (PFD) is required to sense variations both in phase and in frequency. The type of PFD assumed here is built with two D flip-flops whose output generates UP and DOWN signals [6]. The duration of UP and DOWN signals gives good measure of

4 frequency differences between two input signals. If the duration of UP pulses is longer than the DOWN pulses, this means that the input frequency is higher than that of output. The difference in duration is proportional to the ratio of two frequencies. Due to the discrete nature of the symbol timing recovery circuit that uses sampling technique, z-domain technique is employed to analyze its behavior [7]. Since the phase detector obtains the phase error of the previous reference period, the transfer function of the phase detector is Kp.z -, where K p is the gain factor of the PFD. All-digital loop filter consists of a frequency detection part that is a counter determines the current frequency of the DCO. This counter is necessary since the system is designed for multirate. Its output is an average of PFD pulses and its transfer function, H c (z), is defined as 3 c ( z) = ( + z + z + z...) H () z A programmable adaptive loop filter for phase detection can easily be design in digital domain. The transfer function of the all-digital loop filter is given by [7] H L ( z) = α + () z where α and α are proportional gain and integral gain. They define the filter response and adjusted to arrange the steps in the programmable counter used in the loop filter. To provide better stability, greater gain is used when phase error is large and smaller gain is preferable while the phase error is small. One of advantages of all digital PLL is that, α and α can be programmable adaptively to ensure better stability while maintaining different data rates with minimal jitter. Since the target application of the proposed STR is sampling receivers, the sampling clock can be used as the reference clock in the STR. This frequency is quite higher than the symbol clock. A programmable divide by N should be used to bring this frequency to a lower bit rate. The value of N is identified by the output of the frequency detection as well as by the output of the loop filter. The DCO is simply a discrete programmable divider. Therefore it can be represented with a constant value. The overall acquisition model of the STR system in Fig. is illustrated in Fig 6. Assuming K= K p.k DCO =, the closed loop transfer function is φ ( ) z (( + ) z ) H ( ) = out z α α α z = (3) φi ( z) + ( α ( ) + α ) z + α z An important requirement of PLL is that it has to be stable. The stability condition for a discrete time system is that the poles of the transfer function must be within the unit circuit, r= z =,in Z-domain. The system should be stable with combination of α and α. To obtain the desired α and α values that makes the poles below the r =, we plotted the poles of the transfer function in (3) in Fig. 7 via extensive simulation. Fig. 7 shows how poles move varying α and α. It was observed that the system tends to be stable for the values for α from 0.0 to.95 and from 0.0 to 3.94 for α. Normally when the system is to be implemented, the numerical coefficients are substituted α Imaginary Part K p.z - + φ i (z) φ out (z) - Frequency H c(z) detection counter K=Kp.K DCO Digital Loop Filter α + z - z - α K DCO Figure 6. Z-transform model of all digital STR α a-) Real Part α b-) Figure 7. Stability characteristic of STR with the loop filter coefficients, a-) pole positions of H(z) for varying α and α ; increasing the value of α pushes poles towards left while increasing α pushes poles towards the middle point of the unit circle, b-) magnitude of the poles below r =. in the system. It is desirable to push the poles deep inside the unit circle to make sure that despite any variation in the implementation of the filter in CMOS technology, system still will stay inside the stable region. III α A DESIGN EXAMPLE The STR technique presented in the previous section has been implemented in CMOS technology to successfully demonstrate its functionality for a sampling receiver. The block diagram of the symbol timing recovery circuit for digital PSK receivers is illustrated in Figure 8. The sampling frequency was particularly chosen equal to 4 MHz (i.e. =4 MHz). Some examples of input frequencies with appropriate sampling factors based on the equation given in () are f i = MHz (n=0), =3 MHz (n=), =5 MHz (n =). As indicated earlier, the reference clock for the proposed STR circuit is the sampling frequency. The STR design recovers timing clock () for multiple bit rates 0. Kbps, Kbps, 0 Kbps and 00Kbps. The selection of those bit rates are based on the requirement of space applications [8], which was primary target of this STR circuit. However, it can easily be extended to different data rates by changing the ratio of the programmable divider or the value of the sampling frequency. NRZ code is used to represent data. A preamble sequence of 00 or 00 is sent at the beginning of each data transmission for initial synchronization to distinguish between two different data rates. From circuit test results, the length of preamble bits for the worst cases (considering the largest Doppler shift) is observed to be 4 bits. In addition to the preamble, additional two transition bits ( 0 or 0 ) are included after every 6 bits in data to introduce enough transitions in order for the timing circuit to track the data accurately when data rate is being changed during transmission. These additional two bits assure that 5 consecutive 0 s or s would not appear at the same time during transmission. This can usually be performed via some sort ocrambler/descrambler in transceivers. This is necessary in order to distinguish between two discrete data rates. As an example, assume a data rate of 00 Kbps is being transmitted and 5 0 s and 5 has appeared (i.e ). The circuit will rather consider it as a data rate of 0 Kbps. To avoid this to happen for an NRZ coded data, additional two bits are required. 0 0 α 3 4

5 Signal in r(t) -Bit ADC f i Baseband signal (Jn) PSK Sig. (rn(k)) τ =T s =/ fs: Sampling frequency XOR XNOR Output Clock Phase Estimator Reference clock ( = 4 MHz ) Digital PLL r(k) s(k) z(k) y(k) up Prefilter Frequency Delay PFD dn Detection Jn τ ST sd(k) a).. = KHz 0 0 KHz 0 KHz Freq. Divider N Figure 8. An STR circuit for multiple bit rates. The implementation of programmable divider stages for different bit rates are shown. The divider-scaling factor N is programmable and controlled by the Frequency Detection unit based on the frequency of the incoming signal. The Frequency Divider is designed as an increment-decrement counter. As an example, if = 4 MHz and the required clock is for data rate of 00 Kbps, N must be 40 (i.e. /40 = 00 KHz). The selection of XOR or XNOR gate is based on the input signal. If the input is a PSK modulated signal, which is taken directly from the front-end of the receiver after the ADC, XNOR needs to be used. Otherwise, XOR is used for the demodulated baseband signal. The motivation behind this is to be able to obtain the transition pulses y(k), as explained in Figure 4. The delay is selected as T s = 0.5 µs because it is equal to the duration of each pulse in the input digital PSK signal having a frequency of MHZ. The Frequency Detection unit selects the appropriate down conversion stage in the divider section by counting the number of transition pulses in the incoming data signal. The reference clock is the sampling clock which is already available in all digitally-implemented receivers. This is one of the advantages of digitally-implemented receivers, eliminating the need for a separate oscillator to generate a reference clock. The phase synchronization is done by Phase Estimator (e.g. a digital filter acting as a loop filter) together with the counters used for frequency division by using the outputs of PFD. Like all other units, it uses the sampling clock as a reference to detect the phase. The system is locked when the phase error is within the duration of the sample clock period T s. In other words, there is a phase ambiguity of ±T s (= ±50 ns), which is quite small considering low data rates (T s <<T b =/f b-max = 0 µs). IV. STR PERFORMANCE ANALAYSIS The waveform in Fig. 0 shows how the timing circuit recovers the clock from a data sequence of 00 Kbps. The input signal (Fig. 0-(a)) is a MHz PSK signal in which a data of 00 Kbps is modulated. It includes a random frequency offset f =±0 KHz (i.e. f i =MHz ± 0KHz). As clearly seen from the transition pulses in Fig. 0-(b), the input signal is a random data after first four bits. The circuit is synchronized in phase within 4 bits (Fig 0-c.). After synchronization, the output clock is still a proper clock despite the fact that no transition may occur sometimes during random information [8]. The pulses smaller than T s resulted from random N frequency offsets are eliminated at the output of the prefilter. The measured jitter is approximately 84 ps for a 00 KHz clock, as shown in Fig.. This jitter will have no effect on the communication system since the data rates are small enough. The worst-case observed timing offset for all data rates is less than /0 of the symbol period of the highest bit rate 00 Kbps (i.e T = µs). A) Overall Performance of the STR in a Sampling PSK System The PSK model given in [] was selected to evaluate the proposed STR performance. It was given in Fig.and uses - bit ADC at the front-end which is a common technique in satellite communications [9][]. The accumulators in the sampling receiver as shown in Fig. takes the recovered bit clock from the STR output for bit detection. However, unlike analog PSK implementations, the output clock cannot be used directly in sampling receivers. An RC (reset circuit) is necessary between the STR and accumulators to define edges of each bit. This is illustrated in Fig.9. Each accumulator has to be reset (by RC unit) periodically (i.e. every bit period) in order to realize uncorrelated samples. The output of the accumulators I n and Q n are the binomial probability mass functions obtained from the received signal samples []. ) Timing Error: After timing acquisition (i.e. lock condition), the receiver is still affected by timing error due to the inaccuracy of the timing circuit, timing clock jitter and uncertainties in the reset circuit. Timing error is an important impairment in the receivers, which usually affects the bit-error rate (BER) performance and should be kept small in the design. If ε is the timing error in symbol duration T, then the ratio of the timing offset to the symbol period is given by ~ ~ ~ ε f k I I Q Q sε n n n n = = = =, (4) Tb Tb K K K where k ~ is defined as the total samples that are missing due to the timing error ε, K is the total available samples, I ~ n and Q ~ n are accumulated samples when there exists timing error (Fig.9). This equation indicates a good relation of the timing error in timing domain and discrete domain. It defines an expression between timing error and the accumulators outputs. D Q Q Accumulated samples RC RC_Out RC_Out / Delay = width of RC pulses RC_Out I n / 0 ±ε Total timing error ε T b I ~ n I n ±ε error samples: ~ ~ ~ k = I n I n = Q n Qn Error Margin Figure 9. The effect of timing error in the sampling receiver and reset pulses; RC circuit generates pulses to reset accumulators periodically.

6 There will be sample losses when two consecutive bits are different -either 0 or 0. However, for or 00, there will be no loss due to timing error. The effect of timing error on the BER performance is found by replacing K- k ~ with K in the accumulators. Maximum timing offset from the implementation was measured to be µs (i.e T max = µs). This timing offset is negligible for lower data rates. In this case, the total possible missing samples are given in (5). ~ k ~ K K= = k. (5) K 0 0 In Fig., the BER for a data rate of 00 Kbps (where K = 40) is given with ( K = 0. worst-case) and without timing error ( K=0, ideal). Simulations show that timing offset of up to /0 of the symbol period causes approximately db SNR loss. The data rate of 00 Kbps is the only critical data rate where T max =ε = T 00Kbps /0= µs. The performance loss becomes negligible at lower data rates. For example, for data rate of 0 kbps, this offset is /00 of the symbol period (i.e. K = T =µs /00µs =0.0). The loss will be insignificant. V. CONCLUSION Analysis of a new symbol timing recovery technique to achieve multirate clock detection has been presented for sampling PSK receivers. The significance of the STR is that it offers the design of low-cost in CMOS, low timing offset, and fast synchronization. A prefilter is arranged between the delay- XOR unit and the PLL to eliminate frequency offsets. The design is especially suited for digital communication systems where there exists strong and fast Doppler shift. Although the presented circuit is designed for PSK receivers, it could be applied to other modulation schemes with some necessary modification. REFERENCES [] M. Oerder and H. Meyr, Digtal filter and square timing recovery, IEEE Trans. Commun. vol.36, May 988. [] M. Morelli, A. N. D Andrea and U.Mengali, Feedforward ML-based timing estimation with PSK signals, IEEE Commun. Lett., vol., pp. 80-8, May 997. [3] J. G. Proakis, Digital Communications. 4 nd Edition, McGraw-Hill Book Company. 00. [4] T. Le-ngoc and K. Feher, A digital approach to symbol timing recovery systems, IEEE Trans. Commun. vol. 8, pp , Dec [5] E. Panayirci, Jitter analysis of a phase-locked digital timing recovery system,, IEE Proceedings Commun., Speech and Vision, vol. 39, pp , June 99. [6] R. E. Best, Phase-Locked Loops: Theory, Design, and Applications. McGraw-Hill Inc., 003. [7] L. Xiu and W. Li, J. Meiners, and R. Padakanti, A novel all-digital PLL with software adaptive filter, IEEE J. Solid-State Circuits, vol. 39, pp , March, 004. [8] M. R. Yuce and W. Liu, The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers, in Proc. IEEE Custom Integrated Circuits Conference (CICC 04), pp , October 004. [9] E. Gravyer and B. Daneshrad, A low-power all-digital FSK receiver for space applications, IEEE Trans. Commun., vol. 49, pp. 9-9, May 00. [0] S. Lindfors, A. Parssinen and K. A. I. Halonen, A 3-V 30-MHz CMOS decimation subsampler, IEEE Trans., Circuit and Systems-II., vol. 50, pp. 05-7, March 003. [] P. H. Wu, The optimal BPSK demodulator with a -bit A/D front-end in Proc. MILCOM 98, vol.3.3, 998, pages [] A. N. D'Andrea, U. Mengali, and M. Moro, Nearly optimum prefiltering in clock recovery, IEEE Trans. Commun., vol. 34, pp , Nov [3] L. E. Franks and J. P. Bubrouski, Statistical properties of timing jitter in a PAM timing recovery scheme, IEEE Trans. Commun., pp.93-90, July 974. d) c) b) a) Output clock Lock-signal y(k) No transition pulse s(k) preamble data " 0" " 0" " " 0" Phase changes Figure 0 A circuit simulation result showing STR locks in 4 bit duration BER Figure. Jitter performance of the STR circuit from measurement 0 0 K=0 K= SNR Figure. The BER of a sampling binary PSK with timing error