ericssonz MAINTENANCE MANUAL GPS TIMING MODULE ROA /1, 2 SPECIFICATIONS TABLE OF CONTENTS

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1 MAINTENANCE MANUAL GPS TIMING MODULE ROA 7 0/, TABLE OF CONTENTS Page SPECIFICATIONS Front Page DESCRIPTION CIRCUIT ANALYSIS CONTROL POINT TRANSMIT SITE TEST AND TROUBLESHOOTING PARTS LIST IC DATA OUTLINE DIAGRAM SCHEMATIC DIAGRAM SPECIFICATIONS Input Voltage + Vdc 0% Current Drain 7 Milliamps (Typical) Operating Temperature -0ºC to +0ºC Dimensions 8.0 inches long x.0 inches wide Connector P + Vdc A0, A, B0, B Ground A, B, C, C, A, B, C ericssonz Ericsson Inc. Private Radio Systems Mountain View Road Lynchburg, Virginia 0 AE/LZB 9 87 RA (Outside USA, ) Printed in U.S.A.

2 Connector P Definition Terminal A B C REF 900 OUT A REF 900 OUT B REF 900 OUT A REF 900 OUT B REF 900 OUT A REF 900 OUT B REF 900 OUT A REF 900 OUT B REF 900 OUT A REF 900 OUT B 7 REF 900 OUT A REF 900 OUT B 8 COMP REF OUT A COMP REF OUT B RC_IN 9 COMP REF OUT A COMP REF OUT B RC_OUT 0 COMP REF OUT A COMP REF OUT B COMP REF OUT A COMP REF OUT B COMP REF OUT A COMP REF OUT B COMP REF OUT A COMP REF OUT B COMP REF IN A COMP REF OUT A COMP REF OUT B COMP REF IN B COMP REF OUT A COMP REF OUT B COMP REF IN A COMP REF OUT A COMP REF OUT B COMP REF IN B 7 COMP REF OUT A COMP REF OUT B 8 COMP REF OUT A COMP REF OUT B SEL 900 OUT 9 COMP REF OUT A COMP REF OUT B SEL 900 OUT 0 GPSA 900 IN A GPSA 900 IN B SEL 900 OUT GPSA 900 IN A GPSB 900 IN B SEL 900 OUT GPSA 00 IN A GPSA 00 IN B LAND LINE BACKUP GPSB 00 IN A GPSB 00 IN B SEL 00 OUT GPSA IPPS IN A GPSA IPPS IN A SEL 00 OUT GPSB IPPS IN A GPSB IPPS IN B SEL 00 OUT GPSA FREQ ALM IN GPSA FREQ LOCK IN SEL 00 OUT 7 GPSB FREQ ALM IN GPSB FREQ LOCK IN IN 8 CLK IN A CLK IN B MAJOR ALM OUT 9 MINOR ALM OUT MINOR ALM OUT MAJOR ALM OUT 0 +Vdc +Vdc +Vdc +Vdc DESCRIPTION Global Positioning Satellite (GPS) Timing Module ROA 7 0 is used in the GPS Simulcast Synch Shelf. There are multiple Synch Shelves in the GPS Simulcast System, one at the Control Point and one at each Transmit Site. Each Synch Shelf has two GPS Timing modules, A and B. Each of these are fully redundant. The Timing Module plugs into slots 9 & 0 of the Synch Shelf located at both the Control Point and the Transmit Site. At the Control Point, the Timing Module is an ROA 7 0/ and the module at the Transmit Site is an ROA 7 0/. One difference is that there is a different PROM in socket XU with different programming used between the two locations. Also, front panel LED s and labels differ: CPTM for Control Point Timing Module (Figure ) and TXTM for Transmit(X) Timing Module (Figure ). The Timing Module has three functions. Each function, though related, is performed differently at each location, control point or transmit site. At the Control Point, these functions: Generate 00 Hz (Frame Sync Line) Generate Composite References Select 900 Hz Clocks At the Transmit site, these functions: Select 900 Hz clocks Recover references from composites Control T delay Refer to Figures and. The following is a description of the LED indicators found on the front panel of the modules. PWR - Green LED indicates when power is applied to the module. ACTV - Green LED indicates when this is the active module. MAJ - Red LED indicates when a major alarm condition exists. MIN - Yellow LED indicates when a minor alarm condition exist. GPS - Yellow LED indicates that there is no signal coming from the GPS receivers. This is at the Control Point. LL - Yellow LED, at the transmit site, indicates that there is no signal coming from the GPS receivers and the Land Line signals are being used. - Yellow LED indicates there is a loss of the Frame Synch Line at the Control Point. REF - Yellow LED indicates when there is a loss of composite reference at the Transmit Site. PROG - Switch resets PROM U and the Xilinx (FPGA) module U to the initial state. TEST - Connector is an RJ, 8-Pin connector used for test purposes (Refer to TEST AND TROU- BLESHOOTING). NOTE Repairs to this equipment should be made only by an authorized service technician or facility designated the supplier. Any repairs, alterations or substitution of recommended parts made by the user to this equipment not approved by the manufacturer could void the user s authority to operate the equipment in addition to the manufacturer s warranty. NOTICE! The software contained in this device is copyrighted by Ericsson Inc. Unpublished rights are reserved under the copyright laws of the United States. This manual is published by Ericsson Inc., without any warranty. Improvements and changes to this manual necessitated by typographical errors, inaccuracies of current information, or improvements to programs and/or equipment, may be made by Ericsson Inc., at any time and without notice. Such changes will be incorporated into new editions of this manual. No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Ericsson Inc. Copyright September 99, Ericsson Inc.

3 PWR (H) POWER: ON INDICATES THAT POWER IS APPLIED TO MODULE PWR (H) POWER: ON INDICATES THAT POW ER IS APPLIED TO MODULE C PWR ACTV ACTV (H) ACTIVE: ON INDICATES WHEN THIS IS THE ACTIVE MODULE T PWR ACTV ACTV (H) ACTIVE: ON INDICATES WHEN THIS IS THE ACTIVE MODULE P T M MAJ MIN GPS MAJ (H) MIN (H) MAJOR: MINOR: ON INDICATES WHEN A MAJOR ALARM CONDITION EXISTS ON INDICATES WHEN A MINOR ALARM CONDITION EXISTS X T M MAJ MIN LL REF MAJ (H) MIN (H) MAJOR: MINOR: ON INDICATES WHEN A MAJOR ALARM CONDITION EXISTS ON INDICATES WHEN A MINOR ALARM CONDITION EXISTS PROG GPS (H) GLOBAL POSITIONING SYSTEM: ON INDICATES THAT THERE IS NO SIGNAL COMING FROM THE GPS RECEIVERS. PROG LL (H) LAND LINE: ON INDICATES THAT THERE IS NO SIGNAL COMING FROM THE GPS RECEIVERS (LAND LINE BACKUP MODE). (H) FRAME SYNC LINE: ON INDICATES THAT THERE IS A LOSS OF THE FRAME SYNC LINE AT THE CONTROL POINT REF (H) COMPOSITE REFERENCE : ON INDICATES THAT THERE ISALOSSOFCOMPOSITE REFERENCE AT THE TRANSMIT SITE TEST PROG (S) SWITCH THAT RESETS PROM U AND THE XILINX (FPGA) MODULE U TO THE INITIAL STATE TEST PROG (S) SWITCH THAT RESETS PROM U AND THE XILINX (FPGA) MODULE U TO THE INITIAL STATE TEST (P) CONNECTOR USED FOR TEST PURPOSES (REFER TO TEST AND TROUBLESHOOTING ) TEST (P) CONNECTOR USED FOR TEST PURPOSES (REFER TO TEST AND TROUBLESHOOTING) Figure - Control Point Timing Module Front Panel Figure - Transmit Site Timing Module

4 CIRCUIT ANALYSIS CONTROL POINT Functional circuitry is primarily contained in a Xilinx 90A FPGA (Field Programmable Gate Array) integrated circuit (U). This circuitry is programmed differently for control and transmit applications. The GPS Timing module has hot standby capability. Circuitry outside the FPGA provides this capability as well as I/O interfaces and a Phase-Lock-Loop (PLL). The PLL is used at the transmit site. Xilinx 90A FPGA U is wired in master serial mode, which determines how programming is accomplished (Figures & ). These figures are included for those familiar with Xilinx technology and are not described within this document. At power up, following the release of the Reset/reprogram push-button switch S, or following automatic detection of a Xilinx fault, data PROM U is read serially into U. A watchdog function is performed by timer, U in the Activity Detector circuit. This timer causes a reprogramming if the 900 Hz selected clock is not provided by U (automatic Xilinx fault detection). Crystal B provides a.9 MHz clock used internally by the Xilinx logic. This board operates from a single + volt supply. An onboard thermister fuse (F) prevents module failure from causing this shelf supply to collapse. Input signals arrive as RS- levels and are converted to TTL logic levels by RS-8 receivers U9, U, and U. Input fault lines connect directly to U, as they arrive at TTL logic levels. The outputs driving the GPS ReSync modules (located in the same shelf) are buffered with tri-state line drivers U7, U and U. The RS- level outputs are generated using RS-8 drivers U-U0. The tri-state controls on all these drivers are used by the hot standby circuitry to turn the output to high impedance when the module is in hot standby. The circuitry attached to RC_IN and RC_OUT provides operational/hotstandby selection; these leads tie through the backplane to the companion module. PLL U provides a de-jitter filter with zero phase shift on the recovered landline 900 clock. This PLL is used only at the transmit site. The major functions performed at the Control Point are shown in Figure. The GPS signal selection block selects a 900 clock and pps signal from either of the redundant GPS locked clock sources. The Clock Generator block generates a 900 Hz clock for use by the other blocks. The 00 Hz Generator generates the 00 Hz required by the ReSync by dividing the selected 900 Hz by. It also ensures that the phase of this 00 Hz is proper relative to the Frame Sync Line () input. The Composite Reference Generator takes the selected 900 Hz clock and inserts tags at the proper times to create reference signals that contain: Composite Reference contains 900 Hz clock plus tags for 00 Hz and pseudo. Composite Reference contains 900 Hz clock plus tags for pps. These Composite References are extracted at the transmit site. The 00 Hz generator and the Composite Reference Generator are implemented as state machines. TRANSMIT SITE The major functions performed at the transmit site are shown in Figure. There are similarities to the Control Point. The clock generator generates a 9,00 Hz clock for internal use; the GPS signal selection block selects the pps and 900 Hz clock from the two redundant GPS locked clock sources. In addition it also provides for selection of the landline 900 Hz in the unlikely event that both GPS sources are failed. The Signal Recovery block is the corresponding function of the Composite Reference Generator at the Control Point. It extracts the 900, 00 pps and pseudo from the reference signals. The 900 Hz landline is routed off the Xilinx IC (U) to be filtered by the PLL and returned for use by the T delay module. The T delay module examines the selected GPS signals ( pps and 900) and compares their phase to the corresponding landline signals. If certain hysterisis hurdles are exceeded the number of T cycles of delay desired are serially sent to the Intraplex MUX where the actual delay is accomplished. This Delay Control block and Signal Recovery block are implemented with state machines. SELECTOR CLOCK TO CPTC (RS-) 9. CLOCK SELECTOR FROM CPTC 9. DATA AND CLOCK FROM CPTC (RS-) pps SYNC GENERATOR. Generate 00 Hz Coded w/. Generate Composite References 9. GPS INPUT SELECTION pps 9. GPS A pps ALARM (RS-) RESYNC MODULE (Not part of CPTM) 9./00 DRIVERS ALARM 9. GPS B COM REF COM REF 9. DATA AND CLOCK TO MUX (RS-) TO MUX (RS-) Figure - Functions at the Control Point (CPTM)

5 P 00 Hz P *drive P0 900set.9MHz 00HzGen 00Hz 00Hz set pps COMREF Gen * gnd COMPREF COMPREF P P9 *test CompRef P79 CompRef FreqAlarmGPSA gxtl 900GPSA ppsgpasa P8 fgpsa UnlockGPSA P P7 P P9 FreqAlarmGPSA 900GPS GPS SIGNAL SELECTION 900GPSA ppsgpsa fgpsa f UnlockGPSA CLOCK GEN 900CLK COMP_REF.9MHz Vcc P fsel P LDC P 900Sel P 900Sel ppsgpsb UnlockGPSB 900GPSB P9 fgpsb P9 FreqAlarmGPSB P9 P P8 900CLK 900GPSB ppsgpsb fgpsb UnlockGPSB FreqAlarmGPSB ppsgps GPSminor GPSmajor P8 P8 GPSminor GPSmajor TO MUX T CONTROL RS- FROM GPS T CLOCK RS- COMP REF COMP REF TEST POINT TO RESYNC MODULES /00 DRIVERS T DELAY CONTROL pps PPS 900 SIGNAL SELECTION LANDLINE SIGNAL RECOVERY 9. PPS PLL GPS INPUT SELECTION pps ALARM pps ALARM GPS A GPS B Figure - Functions at the Transmit Site (TXTM) Figure - Xilinx 90A FPGA at the Control Point

6 f f TEST AND TROUBLESHOOTING To test as a Control Point module: T DELAY MODULE T_DELAY_OUT DELAY_OUT ppsgps ppsll S S S S S 900GPS S S0 S0 900PLL TCLK ASM_CLR ASMCLK SIGNAL RECOVERY COMP_REF COMP_REF 900LL 900LL ppsll ppsll CLOCK GEN 00LL SEL00 900CLK 900CLK gclk 900CLK COMP_REF.9MHz GPS SIGNAL SELECTION 900GPSA 900GPSA ppsgpsa ppsgpsa fgpsa fgpsa UnLockGPSA FreqAlarmGPSA 900GPS 900GPS UnLockGPSA FreqAlarmGPSA ppsgps ppsgps 900PLL 900CLK 900GPSB 900GPSB ppsgpsb ppsgpsb SEL900A SEL900A fgpsb fgpsb UnLockGPSB SEL900B SEL900B FreqAlarmGPSB UnLockGPSB FreqAlarmGPSB The GPS Timing operates in two functionally different applications. Some of the functionally is the same for both applications and some is complementary to the other application. The module contains a PROM which holds the configuration information for the application. The functions to be tested are described previously for the control point and transmit site application. Signal on test connector P: Control Point Pin - Composite Ref. Pin - pps GPS Pin - nc Pin - * Pin - Selected 900 (ReSync) Pin - 00 out Pin 7 - Composite Ref. Pin 8 - nc Transmit Site Pin - T Delay Data Pin - pps GPS Pin - pps landline Pin - * Pin - Selected 900 (ReSync) Pin - 00 out Pin 7 - nc Pin PLL * Pseudo. The module must be powered up and supplied with GPS signals (900 Hz, pps and an ). The presence of the selected signals at all the proper outputs and of the generated signals (00, Comp Ref. and Comp Ref. ) must be verified. This is done for GPS A and B. The generated Comp Ref. and Comp Ref. need to be checked to verify the tag is placed consistently following the corresponding event. With no signals present, the MINOR alarm goes active; the green activity (ACTV) LED goes out and the red MAJOR alarm LED comes on. To test the Transmit Site: It is desirable to have an operational module in the Control Point mode to provide the Comp Ref. and Comp Ref. signals. Signal selection is checked similar to that done at the Control Point with the additional fault mode of reverting to landline 900 if neither GPS source is present. A second GPS source allows a precise time difference between the landline pps and the direct pps to test the T delay portion of the module. A known time difference is programmed onto the local GPS and the T delay output is examined to verify that a new delay value is sent. As there is no MUX (& T delay module) the correction will successively add to itself. T_CLOCK ASM_CLR COMP_REF 900PLL.9MHz COMP_REF Figure - Xilinx 90A FPGA at the Transmit Site

7 PARTS LIST IC DATA SYMBOL PART NO. DESCRIPTION CRYSTAL B RTM 0 7/07.9 MHz CAPACITORS C RJE 99 7/ Tantalum: µf, ±0%, WVDC. C RJC 0/ Ceramic: 0.0 µf ±0%, 0 WVDC. C RJE 99 8 / Tantalum: µf 0%, WVDC. C RJC 0/ Ceramic:. nf %%, 0 WVDC. C RJE 99 7/7 Tantalum:.7 µf 0%,, WVDC. C RJC 0/ Ceramic: 0.0 µf 0%, 0 WVDC. C7 RJC 0/7 Ceramic: 70 pf %, 0 C. C8 RJC 0/ Ceramic: 0.0 µf 0%, 0 WVDC. C9 and RJC 0/7 Ceramic: 7 pf %, 0 C. C0 C thru RJC 0/ Ceramic: 0.0 µf 0%, 0 WVDC. C C RJA 0/ 0. µf %, WVDC. C thru RJC 0/ Ceramic: 0.0 µf 0%, 0 WVDC. C0 C RJE 99 8/ Ceramic: 0 µf 0 %, WVDC. C thru RJC 0/ Ceramic: 0.0 µf 0%, 0 WVDC. C C RJE 8 8/7 Tantalum: 7 µf 0%,. WVDC. C RJC 0/ Ceramic: 0.0 µf 0%, 0 WVDC FUSE F REZ 70 8/ 0.A V PTC/Thermistor DIODES H RKZ 7/ LED: yellow H RKZ 7/ LED: red H RKZ 7/ LED: green H RKZ 7/ LED: yellow H RKZ 7/ LED: yellow H RKZ 7/ LED: green CONNECTORS P RPV 0 80/0 Right Angle, 9 Pin, Male. P RNV 0 /08 RJ Right Angle, 8 Pin connector RESISTORS R thru REP /7 Chip: 70 Ohms %,,/8 W R R REP / Chip: 00k Ohms %, /8 W R7 REP / Chip:.k Ohms %, /8 W R8 REP /8 Chip: 8k Ohms %, /8 W R9 REP / Chip: 00k Ohm %, /8 W R0 REP /7 Chip: 7k Ohms % /8 W R REP 7/ Chip: MEG Ohms %, /8 W. R thru REP /7 Chip: 7k Ohms % /8 W R R and REP / Chip: 00k Ohms %, /8 W R R7 REP /7 Chip:7k Ohms %, /8 W R8 REP /7 Chip:.7k Ohms %, /8 W. R0 REP /7 Chip:.7k Ohms %, /8 W. R and REP /7 Chip: 70 Ohms %,,/8 W R R and REP / Chip: 00k Ohms %, /8 W R R and REP /7 Chip: 7k Ohms %, /8 W R R7 thru R REP /7 Chip: 70 Ohms %,,/8 W SWITCH S RMD 9 00/0 Right Angle, Momentary. - -INTEGRATED CIRCUITS- - U RON PROM w/socket (Used with ROA 7 0/ Control Point). U RON PROM w/socket (Used with ROA 7 0/ Transmit Site). U RYT 0 00/C Dual D Flip/Flop: Sim to 7HC7. *COMPONENTS ADDED, DELETED OR CHANGED BY PRODUCTION CHANGES SYMBOL PART NO. DESCRIPTION U RYT 0 0/C Phase-Lock-Loop: Sim to 7HCT0. U RYT 9 009/C Xilinx: Sim to 90A U RYT08 00/C Timer U RYT 0 00/C Quad NAND; Sim to 7HC00. U7 RYT 0 09/C Tri-state Buffer; Sim to 7C. U8 RYT 0 00/C Quad NOR; Sim to 7HC0. U9 RYT /C RS-8 Quad Receiver: Sim to LTC89. U0 RYT 0 0/C Inverter, Open Drain; Sim to 7HC0. U RYT /C RS-8 Quad Receiver: Sim to LTC89 U RYT 0 007/C Inverter; Sim to 7HC0. U RYT 0 09/C Tri-state Buffer; Sim to 7C. U RYT /C RS-8 Quad Receiver: Sim to LTC89 U RYT 0 09/C Tri-state Buffer; Sim to 7C. U thru RYT /C RS-8 Quad Driver; Sim to LTC8. U0 U RYT 0 007/C Invertor 7HC0 U RYT 0 00/C And Gate, -input, 7HC08 U RYT 0 09/C Tri-state Buffer; Sim to 7C. U RYT 0/ Power- on reset chip; Sim to MAX TRANSISTORS V thru V, V RYN / FET, n channel SCHOTTKY DIODE V RKZ 0 Signal Diode SOCKET XU RNK 80 /00 0 Pin, PLCC socket for U MISCELLANEOUS SXA 0 7/ Panel: Front (Control Point) SXA 0 7/ Panel: Front (Transmit Site) U PROM RON CPTM (XC7D) RON TXTM (XC7D) CE RESET/ OE or OE/ RESET CLK DATA CLK RESET/OE (OE/RESET) CE Address Counter EPROM Cell Matrix U DUAL D FLIP/FLOP RYT 0 00/C (7HC7) CLR D CK PR Q Q TC Output Vcc CLR D CK PR Q Q Vcc Vpp CEO Inputs Outputs Preset Clear Clock D Q /Q L H X X H L H L X X L H L L X X H* H* H H á H H L H H á L L H H H L X Q0 /Q0 á = Transition from low to high level Q0 = The level of Q after the previous clock pulse * = Nonstable, don t preset when PR and CLR are set high X = Any input, including transition OE CEO DATA U PHASE-LOCK-LOOP RYT 0 07/C (7HCT0) 8 9 CONNECTIONS Terminal Symbol Function PCPout Phase comparator pulse output PCout Phase comparator output COMPin Comparator input VCOout VCO output INH Inhibit input CA Capacitor C connection A 7 CB Capacitor C connection B 8 Ground 9 VCOin VCO input 0 DEMout Demodulator output R Resistor R connection R Resistor R connection PCout Phase comparator output SIGin Signal input PCout Phase comparator output Vcc Supply Voltage

8 IC DATA U XILINX RYT 9 00/C (90A) Terminal Symbol Function VSS Ground VCC Supply Voltage A-I/O A-I/O A-I/O A7-I/O 7 I/O 8 A-I/O 9 A8-I/O 0 A0-I/O A9-I/O PWRDWN PWRDWN (active low) TCLKIN-I/O I/O I/O I/O 7 I/O 8 I/O 9 I/O 0 I/O VSS Ground VCC Supply Voltage I/O I/O I/O I/O 7 I/O 8 I/O 9 I/O Terminal Symbol Function 0 I/O M-RDATA RDATA (active low) MO-RTRIG M-I/O HDC-I/O I/O LDC-I/O LDC (active low) 7 I/O 8 I/O 9 I/O 0 I/O INIT-I/O INIT (active low) VCC Supply Voltage VSS Ground I/O I/O I/O 7 I/O 8 I/O 9 I/O 0 I/O I/O I/O XTAL(IN)-I/O RESET Active Low DONE/PG PG (active low) D7-I/O 7 XTAL (OUT)- BCLKIN-I/O 8 D-I/O 9 I/O 0 D-I/O CSO-I/O CSO (active low) D-I/O I/O VCC Supply Voltage VSS Ground D-I/O 7 CS-I/O CS (active low) 8 D-I/O 9 I/O 70 D-I/O 7 RDY/BUSY- RCLK-I/O BUSY-RCLK (active low) 7 DO-DIN-I/O 7 DOUT-I/O 7 CCLK 7 A0-WS-I/O WS (active low) 7 A-CS-I/O 77 A-I/O 78 A-I/O 79 I/O 80 I/O 8 A-I/O 8 A-I/O 8 A-I/O 8 A-I/O U TIMER RYT 08 00/C () HRESHOLD () TRIGGER CONTRO L VDD () (8) () RESET () TRIG OUT U QUAD NAND GATE RYT 0 00/C (7HC00) A B Y A B Y Positive Logic: Y=A B RESET R R S V DD DSCH THRES CONT Vcc B A Y B A Y () OUTPUT (7) DISCHARGE U7, U, U TRI-STATE BUFFER RYT 009/C (7HC) C A Y C A Y Positive Logic: Y=A+B Vcc 9 C A Y C A Y Inputs Outputs A C Y H L H L L L X H Z U8 QUAD NORGATE RYT 0 00/C (7HC00) Y A B Y A B 7 Vcc Y B A Y B A 7

9 IC DATA U9, U, U RS-8 QUAD RECEIVER RYT /C (LTC89) U - U0 RS-8 QUAD DRIVER RYT /C (LTC8) CONNECTIONS Terminal Symbol Function B A R0 EN R0 A R R R Vcc B A R0 EN R0 DI DOA DOB E DOB DOA DI 7 Vcc DI DOA DOB E\ DOB 0 DOA DI Driver Input DOA Driver Output A DOB Driver Output B E Enable DOB Driver Input B DOA Driver Output A 7 DI Driver Input 8 Ground 9 DI Driver Input 0 DOA Driver Output A DOB Driver Output B E\ Enable\ DOB Driver Output B DOA Driver Output A DI Driver Input Vcc Supply Voltage B 7 0 A R 8 9 DI FUNCTION TABLE 8 9 B Input Enables Outputs E E () () DI E E DOA DOB H: High Level H H X H L L: Low Level L H X L H X: Irrelevant H X L H L Z: High Impedance (Off) L X L L H X L H Z Z DI () DI (7) DI (9) DI () () () () () (0) () () () DOA DOB DOA DOB DOA DOB DOA DOB 8

10 OUTLINE DIAGRAM OUTLINE DIAGRAM (078 ROA 7 0, Rev. B) 9

11 SCHEMATIC DIAGRAM SCHEMATIC DIAGRAM (9 ROA 7 0, Sh., Rev. B) 0

12 SCHEMATIC DIAGRAM SCHEMATIC DIAGRAM (9 ROA 7 0, Sh., Rev. B)

13 SCHEMATIC DIAGRAM SCHEMATIC DIAGRAM (9 ROA 7 0, Sh., Rev. B)

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