Due date: Sunday, November 8 (midnight) Reading: HH sections , (pgs , )

Transcription

1 Logic Gates Due date: Sunday, November 8 (midnight) Reading: HH sections , (pgs. 7 9, 7 ) The next few labs will deal with digital logic. In practice, you will probably find these circuits easier to set up and use than the analog circuits we ve been studying up to now. This first lab introduces the basic logic gates and the different logic families.. NAND Gate The NAND operation ( Not And ) can be considered as an AND gate followed by an inverter. It has the truth table: A B H H L L X H X L H where X stands for any value. Its output is thus low if and only if both inputs are high. Four NAND gates are available in the 700 chip, shown in Fig.. Each set of numbered pins (A, B, ) refers to an independent gate. This is a TTL chip. Get one, but be sure it is an actual 700 and not a 7LS00, 7HC00, or 7HCT00. (We ll look at some of those others later.) Wire up the chip with power and ground, using V cc =. Note that most of the logic functions of the ELVIS board are located on the right-hand side, including a hookup to the supply and ground. Pick one of the gates, and wire the A input to the DIO 0 connector and the B input to DIO (located on the upper right corner of the board). The DIO connections are configurable digital inputs and outputs, and are convenient for testing logic circuits. Wire the output to DIO 8. Start up the DigIn and DigOut tools (also called the Digital Reader and Digital Writer, respectively). In the Writer, set the Lines to Write to 0-7, and in the Reader, set Lines to Read to 8-. Turn on the board power and run the tools. The HI/LO buttons in the Writer A B A B GND Vcc B A B A A B Figure : The 700 quad NAND gate.

2 set the output levels, and the lights on the Reader indicate the input levels. Verify that the truth table for the NAND gate works as advertised. Unhook one of the inputs, and confirm that a floating input acts like an H signal.. TTL Characteristics We shall now investigate in detail how the TTL logic family performs. To start, construct the circuit of Fig., which will allow you to measure the threshold input voltage at which the gate changes state. Describe what the output signal does as you vary the input voltage. What is the threshold voltage, and how well-defined is the transition? What is the direction of current flow, and how much current is required to reach the threshold? How much current flows when the input is grounded, and how much flows when the input is? The circuit of Fig. (a) lets us measure the output current capacity. We use the second gate so that we can identify the point where the output can no longer maintain the desired logic level. Adjust the pot until the output of the second gate switches. How much current can the H-state output source? Then change the voltages to circuit (b), and measure the current that the L-state output can sink. What voltage levels does the (unloaded) output of the second gate produce in the high and low states? Finally, wire up the circuit of Fig., driving the A input from the Sync output of the function generator. Monitor the Sync signal on your scope as well. How much delay is there between when the input crosses the threshold level and when the output crosses the threshold level? You should make sure the BW limit button on the scope is out for this measurement, to obtain the maximum scope speed. You will also likely need to use scope probes with the 0x setting. We can use the same circuit to measure the power consumption of the 700 chip. Hook up an ammeter in series with the supply voltage, and measure the current drawn when the output is low, when the output is high, and when the output is switching at MHz. 0 V 0 V I 0k Scope I 0k Scope Figure : Circuit for measuring the input threshold of a logic gate. Figure : Circuit for measuring the output current capacity of a gate, in (a) the high state and (b) the low state

3 Figure : Circuit for observing the timing characteristics of a gate. Calculate the power consumed in each case by multiplying the current times the voltage and report your results in mw.. LS Characteristics The 7LS00 chip has the same pinouts as the 700, and should behave in the same way. Verify this by repeating your measurements of the input threshold and current, the output current, the switching speed, and the power consumption. Compare in each case to the results for the 700. What is the primary difference between these two families?. HC Characterization The same measurements can be performed for the 7HC00 chip, which is again pin compatable with the 700. Since this is a CMOS chip, you should expect to see more differences here. Perhaps the main practical difference is the need to tie unused inputs to a definite level. Do that to start, using either high or low levels as convenient. Observe one of the outputs on the scope, and unhook the corresponding A input. What do you observe? Run a wire to the input and touch its end with your finger. You shoud be able to set the logic state by either first discharging your finger on the grounding pad, or charging your finger by rubbing it on your clothes. Can you switch the output just by putting your hand near the wire, without actually touching it? Now repeat the same four tests with the 7HC00 that you did with the 700 and 7LS00. Record your results, and note any differences you observe from the other chips. The other logic family you will encounter is the 7HCT series. In the interests of time, you don t need to characterize it. If you did, you would find that it acts much like the 7HC series, except that its threshold is. V and it switches a bit slower.. Three-State Logic Another type of logic gate that is often useful is the three-state device. At first, this might be mistaken for trinary logic, where three output levels represent the values 0,,. But in fact, the outputs of a three-state device are 0,, and off. In the off state, the device asserts neither a high or a low value, but is instead effectively disconnected from the

4 OE A OE A GND 7HCT Vcc OE A OE A A OE Figure : The 7HCT quad three-state buffer. output pin. This is useful when several devices are wired together to a common output. A common output is normally called a bus, and is used when multiple devices take turns sending signals to one receiver. The 7HCT is a three-state buffer, shown in Fig.. It has the truth table OE A L L L L H H H X off Here OE should be read as output enable and the bar indicates that you need to supply the inverse of the enable signal. In other words, if output enable is supposed to be true, then you need to supply a false value for OE. As with the NAND gates, there are four separate buffers on each chip. To demonstrate the use of three-state logic, we will implement a -input multiplexer (or MUX), as shown in Fig.. This is a device with four inputs and one output. The output simply follows one of the inputs, with which input being determined by two address bits according to X Y L L a L H b H L c H H d where a, b, c, and d stand for the value at the corresponding input. The multiplexer thus operates like a digital SPT switch, with the address bits setting the switch position. Just like switches, multiplexers are useful in many situations. The three-state buffer provides a convenient way to implement the multiplexer. Simply hook each input signal (a, b, c, d) to a corresponding buffer pin (A, A, A, A), hook all four outputs (,,, ) together, and then use the OE pins to set which input is applied to the common output bus. The only tricky part is to set up some logic gates to convert the two address bits to

5 x y d x c y b Figure : A -input multiplexer. Figure 7: Partial circuit for translating the address (xy) to the enable signal (abcd). one of four enable signals. Figure 7 shows one way the enable signals for the b, c, and d signals can be obtained. How can the enable signal for the a channel be derived? Set up the circuit, and verify that the multiplexer works as desired. It will probably be convenient to use the Digital Writer and Reader tools to observe the behavior. Make sure that for each combination of address bits, the output signal follows the corresponding input signal and is unaffected by the other inputs. Note, however, that integrated multiplexer circuits are available, such as the 8-input 7. It would be unusual for you to actually build your own multiplexer in practice.. Monostable Multivibrator* Do this section only if you have time. The monostable multivibrator is a useful device for generating triggerable pulses and delays. When triggered by a transition on its input, it generates a single output pulse with a duration determined by an RC network attached to the chip. Because of this behavior, another common name for the device is a one-shot. A common one-shot is the 7, shown in Fig. 8. It has a fairly complicated input logic arrangment in order to provide maximum triggering flexibility. Referencing the circuit diagram, however, an output pulse will be produced whenever the input to the square block sees a rising edge. If we let the A, B, and B inputs float high, then what type of transition applied to the A terminal will produce a pulse? Wire up the circuit that way. You will also need to let the CLR terminal float high (so that the device is not cleared ). The output pulse duration is given approximately by t w = 0.RC The resistor R should be in the range of 0 kω to 00 kω, and the capacitor larger than nf. (More detailed information about the timing elements can be found on the 7 data sheet, if needed.) Set up your circuit using a 00k pot and a 0 nf capacitor, and drive the input at 00 Hz with the Sync pulse from the function generator. Observe the input and output signals on the scope, and verify that the output behaves as claimed when you change the pot resistance.

6 A A B B CLR GND Vcc R/C NC C NC Rint A A B B R R/C C C Figure 8: The 7 monostable multivibrator. CLR One-shots end up being so handy that Horowitz and Hill spend some effort warning against their overuse. The main concern is that the timing they produce is not very precise, so you shouldn t use them when precision is important. Incidentally, the term multivibrator refers to a circuit with two possible states. In a monostable multivibrator, only one of the states is stable: when the circuit is put in the unstable state, it returns to the stable one after time t W. A bistable multivibrator remains in whichever state you place it, and is more commonly called a latch. An astable multivibrator won t stay put in either state, and thus forms an oscillator.