Testing Integral and Differential Non-Linearity of ADC Using Servo Loop Solution

Transcription

1 Testing Integral and Differential Non-Linearity of ADC Using Servo Loop Solution Jin-Soo Ko Teradyne

2 Overview Solution for INL/DNL testing of high-resolution Analog-to- Digital converter (ADC) Supported device types 20-bit parallel 32-bit serial max. Single-ended and differential input signals Supports multiple data formats 1 s Complement, 2 s Complement, Inverted etc. Designed for multi-site testing capability Dedicated Servo Loop Module per DUT Shared DC Reference Module

3 Servo Loop Operation Target Transition Code Verror Code Pedestal level SAR mode INT mode Code Lock and start capture Verror Target Level = Pedestal level + Verror

4 DC Reference Module: The DC Reference Module provides Pedestal Voltage near target code transition level Common-Mode voltage for differential signal Max +/- 12.5V driving capability

5 DC Reference Module SCLK_1 CS_1 DIN_1 Pedestal DAC PED_DAC + VS -VS + VS -VS 5V Reference PED_REF VIN AGND VIN AGND 5V Reference CM_REF DGND DGND DIN_2 Common- Mode DAC COMMON_DAC CS_2 SCLK_

6 ΔOutput DC Reference Stability DC Reference Module Output over 2 hours minutes

7 Servo Loop Module: The Servo Loop s makes the main decisions Updates the input to the ADC based upon the current output. Asserts Code Lock after the code has been successfully found. Driving error voltage between Pedestal level and SAR DAC through gain amplifier

8 Servo Features Ability to amplify error voltage and measure it to calculate the transition voltage for the code Gain of 1, 10, 100, 1000 Programmable SAR cycles (max. 14) For initial binary search of transition edge Adjustable servo range +/- (Reference Voltage / 10) Ref. voltage 1 to 5V Programmable integrator step size (max. 15 steps) Ability to control servo step size during integration Ability to lock on rising or falling edge

9 Servo Loop & Ref Source DC Ref. Source Module Pedestal DAC Max +/- 12.5V PGA SERVO_ERROR Digitizer MEM_DECR LOAD_PARAM Target Code Memory R R SERVO_OUT TEST_START DATA_VALID FPGA CODE_LOCK DUT_CLOCK DUT (ADC) 32-bit State Machine SAR/INT DAC R SERVO_OUT + Common- Mode DAC SERVO_OUT - Servo Loop Module

10 Programming-Software Calibration Three calibration factors need to be measured for each code Pedestal Voltage / Common-Mode Voltage Composite Offset Error Composite Gain Error The calibration data is stored in a global structure object and written to a file that is later read and accessed when required by the test program

11 Calculating code edge voltage Code transition voltage is calculated from the measured ERROR_OUT voltage and calibration factors as follows. code transition voltage = pedestal voltage + [ (averaged error voltage - offset error) / {servo error amplifier gain * (1 + gain error)} ]

12 Test Time Reduction Test time reduced by testing a reduced code set For example, for a 16-bit application 2000 codes are tested out of a possible codes For a 16-bit application test time was reduced to 12 seconds vs. 22 seconds using Ramp INL/DNL Multi-site test

13 Typical Performance Expect code = 33 Servo Loop Module

14 Linearity Results using Servo Loop Technique vs. Ramp Histogram Method

15 Servo Loop INL

16 Ramp Histogram INL

17 Servo Loop DNL

18 Ramp Histogram DNL

19 Code Edge Voltages 16 bits +/- 10v ADC, 2000 codes tested Zoom in

20 Code Edge Voltages (Zoomed) 0.3mv /LSB Test 4 codes Skip 10 LSBs

21 Application DIB