STD1LNK60Z-1 STQ1NK60ZR - STN1NK60Z N-CHANNEL 600V 13Ω 0.8A TO-92/IPAK/SOT-223 Zener-Protected SuperMESH MOSFET
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1 STD1LNK60Z-1 STQ1NK60ZR - STN1NK60Z N-CHANNEL 600V 13Ω 0.8A TO-92/IPAK/SOT-223 Zener-Protected SuperMESH MOSFET Table 1: General Features TYPE V DSS R DS(on) I D Pw STQ1NK60ZR STD1LNK60Z-1 STN1NK60Z 600 V 600 V 600 V < 15 Ω < 15 Ω < 15 Ω 0.3 A 0.8 A 0.3 A TYPICAL R DS (on) = 13Ω EXTREMELY HIGH dv/dt CAPABILITY ESD IMPROVED CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED 3 W 25 W 3.3 W DESCRIPTION The SuperMESH series is obtained through an extreme optimization of ST s well established strip-based PowerMESH layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOS- FETs including revolutionary MDmesh products. Figure 1: Package TO-92 (Ammopack) IPAK TO-92 Figure 2: Internal Schematic Diagram SOT-223 APPLICATIONS AC ADAPTORS AND BATTERY CHARGERS SWITH MODE POWER SUPPLIES (SMPS) Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STQ1NK60ZR Q1NK60ZR TO-92 BULK STQ1NK60ZR-AP Q1NK60ZR TO-92 AMMOPAK STD1LNK60Z-1 D1LNK60Z IPAK TUBE STN1NK60Z N1NK60Z SOT-223 TAPE & REEL Rev. 6 September /14
2 Table 3: Absolute Maximum ratings Symbol Parameter Value Unit IPAK TO-92 SOT-223 V DS Drain-source Voltage (V GS = 0) 600 V V DGR Drain-gate Voltage (R GS = 20 kω) 600 V V GS Gate- source Voltage ± 30 V I D Drain Current (continuous) at T C = 25 C A I D Drain Current (continuous) at T C = 100 C A I DM ( ) Drain Current (pulsed) A P TOT Total Dissipation at T C = 25 C W ( ) Pulse width limited by safe operating area (1) I SD 0.3A, di/dt 200A/µs, V DD V (BR)DSS, T j T JMAX. Table 4: Thermal Data Derating Factor W/ C V ESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 800 V dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns T j T stg Operating Junction Temperature Storage Temperature (#) When mounted on 1 inch² Fr-4 board, 2 Oz Cu Table 5: Avalanche Characteristics Table 6: Gate-Source Zener Diode -55 to 150 C IPAK TO-92 SOT-223 Rthj-case Thermal Resistance Junction-case Max C/W Rthj-amb Thermal Resistance Junction-ambient Max (#) C/W Rthj-lead Thermal Resistance Junction-lead Max C/W T l Maximum Lead Temperature For Soldering Purpose C Symbol Parameter Max Value Unit I AR E AS Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max) Single Pulse Avalanche Energy (starting T j = 25 C, I D = I AR, V DD = 50 V) 0.8 A 60 mj Symbol Parameter Test Conditions Min. Typ. Max. Unit BV GSO Gate-Source Breakdown Igs=± 1mA (Open Drain) 30 V Voltage PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/14
3 ELECTRICAL CHARACTERISTICS (T CASE =25 C UNLESS OTHERWISE SPECIFIED) Table 7: On /Off Symbol Parameter Test Conditions Min. Typ. Max. Unit V (BR)DSS Drain-source I D = 1 ma, V GS = V Breakdown Voltage I DSS I GSS Zero Gate Voltage Drain Current (V GS = 0) Gate-body Leakage Current (V DS = 0) V DS = Max Rating V DS = Max Rating, T C = 125 C 1 50 V GS = ± 20V ±10 µa V GS(th) Gate Threshold Voltage V DS = V GS, I D = 50 µa V R DS(on) Static Drain-source On V GS = 10V, I D = 0.4 A Ω Resistance µa µa Table 8: Dynamic Symbol Parameter Test Conditions Min. Typ. Max. Unit g fs (1) Forward Transconductance V DS = V, I D = 0.4 A 0.5 S C iss C oss C rss C oss eq. (3) t d(on) t r t d(off) t f Q g Q gs Q gd Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Turn-on Delay Time Rise Time Turn-off-Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge V DS = 25V, f = 1 MHz, V GS = V GS = 0V, V DS = 0V to 480V 11 pf V DD = 300V, I D = 0.4 A R G = 4.7Ω V GS = 10 V (see Figure 21) V DD = 480V, I D = 0.8 A, V GS = 10V (see Figure 25) pf pf pf ns ns ns ns 6.9 nc nc nc Table 9: Source Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Unit I SD I SDM (2) Source-drain Current Source-drain Current (pulsed) V SD (1) Forward On Voltage I SD = 0.8A, V GS = V t rr Q rr I RRM t rr Q rr I RRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 0.8 A, di/dt = 100A/µs V DD = 20V, T j = 25 C (see Figure 23) I SD = 0.8 A, di/dt = 100A/µs V DD = 20V, T j = 150 C (see Figure 23) Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS A A ns nc A ns nc A 3/14
4 Figure 3: Safe Operating Area for IPAK Figure 6: Thermal Impedance for IPAK Figure 4: Safe Operating Area for TO-92 Figure 7: Thermal Impedance for TO-92 Figure 5: Safe Operating Area for SOT-223 Figure 8: Thermal Impedance for SOT-223 4/14
5 Figure 9: Output Characteristics Figure 12: Transfer Characteristics Figure 10: Transconductance Figure 13: Statis Drain-Source On Resistance Figure 11: Gate Charge vs Gate-source Voltage Figure 14: Capacitance Variation 5/14
6 Figure 15: Normalized Gate Thereshold Voltage vs Temperature Figure 18: Normalized On Resistance vs Temperature Figure 16: Source-Drain Diode Forward Characteristics Figure 19: Normalized BVdss vs Temperature Figure 17: Maximum Avalanche Energy vs Temperature Figure 20: Max Id Current vs Tc 6/14
7 Figure 21: Unclamped Inductive Load Test Circuit Figure 24: Unclamped Inductive Wafeform Figure 22: Switching Times Test Circuit For Resistive Load Figure 25: Gate Charge Test Circuit Figure 23: Test Circuit For Inductive Load Switching and Diode Recovery Times 7/14
8 In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: 8/14
9 TO-92 AMMOPACK DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A T T T d P P F1, F delta H W W W W H H H D t L l delta P /14
10 TO-251 (IPAK) MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A A A B B B B B C C D E G H L L L H A1 C2 A3 A C L2 D L E = = B2 = = G = = B3 B6 B B5 L E 10/14
11 TO-92 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A b D E e e L R S W V /14
12 SOT-223 MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A B B c D e e E H V 10 o 10 o A P008B 12/14
13 Table 10: Revision History Date Revision Description of Changes 19-Mar First Release 15-May Removed DPAK 09-Jun Final Datasheet 17-Nov Inserted SOT Feb Modified Curve 4 07-Sep Inserted Ecopack indication 13/14
14 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 14/14
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