150V, 1.5A, Unipolar Ultrasound Pulser Demoboard +5.0V VLL AVDD PWR VSS VDD VPP CWD VDD VDD VDD. Q[7:0] Data Latch. Shift Register D0 SDI SUB VSUB

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1 HV755DB 5V,.5A, Unipolar Ultrasound Pulser Demoboard General Description The HV755 is a monolithic eight-channel, high-speed, high voltage, unipolar ultrasound transmitter pulser. This integrated, high performance circuit is in a single, 8x8x.9mm, 5-lead QFN package. The HV755 can deliver guaranteed ±.5A source and sink current to a capacitive transducer with to +5V peak voltage. It is designed for medical ultrasound imaging and ultrasound material NDT applications. It can also be used as a high voltage driver for other piezoelectric or capacitive MEMS transducers, or for ATE systems and pulse signal generators as a signal source. The HV755 s circuitry consists of controller logic circuits, level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of each channel are designed to provide peak output currents typically over ±.5A for pulsing, with up to 5V swings. The upper limit frequency of the pulser waveform is dependent upon the load capacitance. With different capacitance load conditions the maximum output frequency is about MHz. Block Diagram +.V This demoboard datasheet describes how to use the HV755DB to generate the basic high voltage pulse waveform as an ultrasound transmitting pulser. The HV755 circuit uses DC-coupling from a.v logic input to output TX~7 internally, therefore the chip needs three sets of voltage supply rails: V LL (+.V), V DD /V SS (+/-5.V) and V PP (up to +5V). The V PP high voltage supply can be changed rather quickly, compared to the capacitor gatecoupled driving pulsers. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. The control signal logic-high voltage should be the same as the V LL voltage of the IC, and the logic-low should be referenced to. The HV755DB output waveforms can be displayed using an oscilloscope by connecting the scope probe to the test points TX~7 and. The soldering jumper can select whether or not to connect the on-board dummy load, a capacitor paralleling with a.5kω resistor. The test points can be used to connect the user s transducer to easily evaluate the pulser. +5.V +5. to 5V +.V EXCLK OSC MHz JTAG WAVE FREQ SEL CW/RTZ CLK IN Waveform Generator CPLD CW LR RTZ PWR IN IN7 SCK VLL PWR CWD Q7 Q[7:] Data Latch Q7 SDO Q Shift Register D SDI A VSUB LR SUB LT LT LT LT VPF VPF CPF VPF TX TX7 C R TX7 Dummy Load R.5k -5.V

2 The PCB Layout Techniques The large thermal pad at the bottom of the HV755 package is internally connected to the IC s substrate (VSUB). This thermal pad should be connected to V or externally on the PCB. The designer needs to pay attention to the connecting traces on the outputs TX~7, as the high-voltage and high-speed traces. In particular, controlled-impedance to the ground plane and more trace spacing needs to be applied in this situation. High-speed PCB trace design practices that are compatible with about 5 to MHz operating speeds are used for the demo board PCB layout. The internal circuitry of the HV755 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors and the driver to the FET s gate-coupling capacitors should be as close to the pins as possible. The pin should have low inductance feed-through via connections that are connected directly to a solid ground plane. The,, and CPP voltage-supply and/or bypass capacitor pins can draw fast transient currents of up to.a, so they should be provided with a low-impedance bypass capacitor at the chip's pins. A ceramic capacitor of. to.µf may be used. Only to capacitors need be high voltage. CPF to capacitors only need be low voltage. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise when using multiple HV755 ICs, insert another ferrite bead between each chips supply line. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of the HV755 s high voltage power stages is very low, to obtain better waveform integrity at the load terminals after long cables, in some cases it may be desirable to add a small value resistor in series with the outputs TX~7. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Be aware of the parasitic coupling from the outputs to the input signal terminals of the HV755. HV755DB This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to.v, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry. Testing the Integrated Pulser The HV755 pulser demoboard should be powered up with a DC power supplie that has current limiting functions. To meet the typical loading conditions, the on-board dummy load //.5kΩ should be connected to the high voltage pulser output through the solder jumper when using an oscilloscope s high impedance probe. To evaluate different loading conditions, the values of the RC within the current and power limit of the device may be changed. In order to drive the user s piezo transducers with a cable, one should match the output load impendence properly to avoid cable and transducer reflections. A 7 to 75Ω coaxial cable is recommended. The coaxial cable end should be soldered to TX~7 and directly with very short leads. If a user s load is being used, the on-board dummy load should be disconnected by cutting the small shorting copper trace in between the zeroω resistor s (R, R etc.) pads. They are shorted by factory default. All of the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may have limited input voltage. When using the probe on these high voltage test-points, make sure that V PP voltages do not exceed the probe limit. Using the high impendence oscilloscope probe for the on-board test points, it is important to have short ground leads to the circuit board ground plane.

3 HV755DB Schematic HV755DB J EXCLK D D D5 D D7 RED YLW YLW GRN RED SCK SDI C9 µf V DA DB DA DB D7 D5 TP VZ TP VZ VZ VZ5 TP7 VZ VZ7 VZ8 TP VZ9 TP7 V CC = +.V V DD /V SS = +/-5.V V PP = +5. to +5V TP BAT5DW-7 BAT5DW-7 BAT5DW-7 EX= MHz X OUT TP 5 TX TX IN IN IN IN IN IN5 IN IN7 SCK SDI SDO TX TX TX TX TX TX TX TX TX5 TX5 TX TX TX7 TX7 TP VLL A CPF CPF TP TP9 TP TP TP TP8 R.k 5 JTAG J SW SW SW SW SW5 C R9.k JX9577 TP7 TP TP TP TP TP CLK 9 SCK SDO W ZE;79ZNaXS TP TP R5.55k TP9 R.55k TP8 B- J R.k R7 5 R 5 R 5 R 5 R 5 R9 5 R5 5 R 5 C R5 k TP5 TP TP R C7 5V BAT5DW-7 B- C R5.k R.k R7.k R8.k C8 R7 5 R8 5 R9 5 R5 5 R5 5 C C C R 5 R5 5 R 5 TP IN IN IN IN IN IN5 IN IN7 R k R7 k R8 k R9 k R. R. R8. R5. R R R R R5 5 HEADER J C C C C5 MH MH MH MH TP TP9 TP5 TP8 TP8 TP5 TP5 C µ C µ C µ C5 µf C8 µf C7 µf V C9 TP TP TP7 TP C µ C µf V C8 µf V C 5V R C 5V R8 C 5V R C9 5V R C7 5V R7 C 5V R5 C 5V R5 R.55k R.55k R9.55k R.55k R.55k R.55k TP WAV FRE SEL A MOD TMS TDI TDO TCK SCK SDI

4 HV755DB HV755DB PCB and Board Layout Actual Board Size: 7.mm x 8.mm Power Connector Description +.V Logic voltage input for VLL and CPLD. (ma) +5.V HV755 positive supply. (5mA) -5.V HV755 negative supply. (-5mA) 5 V, Ground V, Ground + to +5V positive high voltage supply. (5mA) Voltage Supply Power-Up and Operation Sequence + + / V positive logic supply voltage for HV755 s VLL and CPLD. ±5.V positive and negative and power supply. + to +5V positive high voltage. Note: Power-down in reverse order Push Button Operations WAV FREQ Toggle select pulse B-mode waveforms: None, -cycle, -cycles, 7-cycles. Toggle select frequency:,, 5,.5,.5 and.5mhz when X oscillator is MHz. SEL Toggle select. Increases the off-time between consecutive pulses. Toggle ON or OFF HV755 chip enable MODE Toggle select between B-mode and CW. D Indicator Set the latch registers of serial interface, when high, all latches are set to logic high. Latch enable when low, data can be latched into the registers of serial interface. Mode control, high indicates B-mode and low indicates CW. PWR HV755 VLL.V and CPLD chip power supply indicator. HV755 chip enable signal indicator. Power state initially is OFF until is pushed.

5 Typical Waveforms HV755DB Figure. Input logic and TX output waveforms of 5.MHz ( to +5V with //.5kΩ load) Figure. Rise and fall time at to +5V (with //.5kΩ load) 5

6 Typical Waveforms (cont.) HV755DB Figure. Multiple channel at 5.MHz ( to +5V with //.5kΩ load) Figure. FFT Plot of Second Harmonic Distortion (HD) -db at 5.MHz, V PP = 5V (with //.5kΩ load)

7 HV755DB Typical Waveforms (cont.) Figure 5. Output Waveform at MHz and V PP = V (with //.5kΩ load) Figure. Output Waveform at.5mhz and V PP = V (with //.5kΩ load) 7

8 Typical Waveforms (cont.) HV755DB Figure 7. Output Waveform at MHz at V PP = 75V (with //.5kΩ load) Figure 8. Power on chip enable to VPF setting time 8

9 Bill of Materials HV755DB Component Description Manufacturer Part Number C - C, C8, C9, C, C - C5 C, C7, C - C, C9, C7 C5, C8, C, C, C, C CAP CER µf V X7R % TDK C8X7RCK CAP CER V X7R Panasonic ECJ-VBDK CAP CER.µF V X7R TDK C8X7RC5M C, C9, C7, C8 CAP CER µf V X7R % TDK C5X7RA5M D, D7 D THIN 5NM RED DIFF 85 SMD Lumex SML-LXT85IW-TR D, D5 D THIN 585NM YEL DIFF 85 SMD Lumex SML-LXT85YW-TR D D THIN 55NM GRN DIFF 85 SMD Lumex SML-LXT85GW-TR D5, D7 DIODE SCHOTTKY V A SMA Diodes Inc. B- D, D DIODE SCHOTTKY DUAL V SOT- Diodes Inc. BAT5DW-7 J CONN HEADER POS. VERT GOLD Molex -8- J CONN JACK D LAUNCH PCB GOLD SMA Johnson -7-8 J CONN HEADER POS. VERT GOLD Molex -8- J CONN HEADER POS. VERT GOLD Tyco -5- R, R, R, R8, R, R7, R5, R5 R, R, R, R9, R, R, R, R5 R, R5, R, R7, R8, R9, R R5 - R7, R - R, R, R, R9, R5 - R5 R5, R, R7, R8, R9 Solder Gap (SHORT) NA NA RES.55kΩ % 5 SMD Panasonic ERJ-TNF55U RES.kΩ /W % SMD Panasonic ERJ-EKFV RES 9.9Ω /W % SMD Panasonic ERJ-EKF9R9V RES.kΩ /W % SMD Panasonic ERJ-EKFV R, R, R5, R8 RES.Ω / % SMD Rohm REZPFLR R, R, R, R, R SW, SW, SW, SW, SW5 RES Ω /W % SMD Panasonic ERJ-EKFV SWITCH LT.7MMX.5MM GF SMD Panasonic EVQ-PM TP, TP5 TEST POINT PC MULTI PURPOSE BLK Keystone 5 U IC CPLD 7 ELL C-TEMP -VQFP Xilinx XC957XL-5VQC U IC HV755K-G -ch RTZ Supertex Inc. HV755K-G X OSC CLOCK.MHz.V SMD CTS CBLV-C-.-T does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) All rights reserved. Unauthorized use or reproduction is prohibited. 9 5 Bordeaux Drive, Sunnyvale, CA 989 Tel: