Supertex inc. MD2134DB1. MD2134 Ultrasound Beamforming Transmitter Demoboard CPLD MD2134

Transcription

1 MD Ultrasound Beamforming Transmitter Demoboard Introduction The MD is a high-speed, arbitrary waveform, push-pull source-driver. It is designed for medical ultrasound imaging and HIFU beam forming applications. It also can be used in NDT, sonar and other ultrasound phase-array focusing beamforming applications. The integrated circuit (IC) consists of the CMOS digital logic input circuits, an 8-bit current DAC for the waveform amplitude control, and four pre-stored Sine waveforms with pulseamplitude-modulation (PAM) current sources. These current sources are constructed with the high-speed current-switch array and SPI programmable LV[:] PAM level registers. The PAM level resolution of the waveform is 7-bit, 8-step plus sign. There are four logic inputs M[:0] as fast control signals. They control the push-pull current-source s output timing, frequency, cycle in the burst, as well as the currentlevel output. The level registers, along with the DAC value, together can be written and read-back via a SPI serial interface. The MD s output stage is designed to drive two depletion mode high voltage Supertex DN N-type MOSFETs as the source drivers. The MOSFET drains are connected to a center-tap ultrasound frequency pulse transformer. The secondary winding of the transformer can connect to the ultrasound piezo or capacitive transducer via cable and with a good impedance match. MD has a high-speed 0MHz serial data interface that can quickly update the beam forming apodization between scans. MDDB General Description This demoboard datasheet describes how to use the MD- DB to generate the ultrasound transmit beam forming waveform with the Gaussian profile, and the adjustable frequency, amplitude and phase angle. It also provides information about how to design a user application circuit and PCB using the MDK7 and DNDK devices. The MDDB circuit uses a pair of depletion mode, high voltage, DN MOSFETs in the push-pull mode to drive the center-tap wide band ultrasound output transformer. The MOSFETs are in one 8-Lead DFN surface mount package. The sources of the MOSFETs are directly driven by the MD s two outputs, whose maximum peak sinking current is up to.a. These current-source outputs are controlled by the MD s internal current source switch array and the input signals M[:0]. All of the MD s logic control signals are generated by two small CPLD-programmable logic circuits clocked by an onboard 0MHz crystal oscillator. The on-board CPLD circuits not only generate accurate timing for the high-speed PAM level control waveforms, but also the serial data and clock to set and change the waveform amplitude DAC and waveform selection registers. The external clock input can be used if the on-board oscillator is disabled. The external trigger input can be used to synchronize the burst waveforms launch timing. There are five push buttons for enabling and selecting the output waveform selection (PAM), amplitude (DAC) and chip en- Demoboard Block Diagram +.V +.V JTAG +.V +.0V +.0V +.V EXTRG EXCLK 0MHz OSC DIS Wave Freq Phase Ampl A EXTRG CLKIN IO CPLD M M M0 M SDI SDO SCK CS LD Phase DAC PWR VLL PA MD RFB PB +70 to 00V V PP DN C7 DN +.0V +.V T :: JUMP k 0pF LOAD XDCX Doc.# DSDB-MDDB A070

2 MDDB able (). The FREQ button is not being used for this revision of firmware. Four color LEDs indicate the power, chip enable, waveform selection, and DAC states. The MDDB output waveform can be displayed by using an oscilloscope and the high impedance probe at the TP test point. It also can use an SMA to BNC 0Ω coaxial cable connected directly to an oscilloscope, with an attenuation of : if R 0 is 00Ω. A cable can also be used to drive the user s transducer directly. Jumper J can be used to select whether or not to connect the on-board equivalent-load, which is formed by a 0pF capacitor in parallel with a.0kω resistor. Circuit Design & PCB Layout The thermal pad at the bottom of the MD package must be connected to the VSUB pin on the PCB. The VSUB is connected to the IC s substrate. It is important to make sure that the VSUB is well grounded. A proper supply voltage power-up sequence is needed to test the circuit. To prevent any supply voltage polarity reversing, the circuit also has protection Schottky diodes (D7, D8 and D9). Due to the high current and high current slew rate nature of this common gate, source-driven and push-pull circuit topology, the two cascading N-channel MOSFETs need to have very low lead inductance of the connections. The Supertex DNDK is designed for this application and works with the MDK7 seamlessly. In particular, a good PCB layout design needs to shorten the traces between the MDK7 output pins and the DNDK source pins. It is also necessary to connect all three pairs of pins between them for the high current carrying capacity. Furthermore, because of the high di/dt current in MD s outputs, it is also necessary to connect the Schottky diodes D and D from the driver output pins connected to the +.0V power supply line, as the clamping diodes. Note that the diodes must have enough speed and peak current capability. The RC snubber circuits of R8-C and R-C8 at the output pins can dump the current pulse edge ringing effectively. PCB designers need to pay attention to some of the connecting traces as high-voltage and high-speed traces. In particular, low capacitance to the ground plane and more trace spacing needs to be applied in this situation. High-speed PCB trace design practices that are compatible with about 00 to 00 MHz operating speed are used for the demoboard PCB layout. The internal circuitry of the MD can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving even very small inductive loads, ringing and even oscillations are possible. The supply voltage bypass capacitors and the MOSFET gate de-coupling capacitors should be as close to the pins as possible. The capacitor s ground pin pads should have low inductance, feed-through connections that are connected directly to a solid ground plane. The and VPP supplies can draw fast transient currents of up to.a, so they should be provided with a low-impedance bypass capacitor at the chip s pins. A ceramic capacitor of to.0µf may be used. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise and when using multiple MD ICs, insert another ferrite bead between and decouple each chip supply separately. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance not only on the supply pins but also on the CA/B and KA/B compensation pins. Very closely placed surface mount components are highly recommended. Be aware of the parasitic coupling from the high voltage outputs to the input signal terminals of MD. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to.v, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry. This MDDB demoboard should be powered up with multiple DC power supplies with current limiting functions. The power supply voltages and current limits used in the testing are listed on page 7. There are examples of the MDDB demoboard input and output waveform and measurements shown in Figures to 7 below. Output Transformer Design The center tap, wide band, ultrasound transformer for pushpull output circuit serves three functions: a balanced-differential to single-end output transformer; an isolation barrier to the ultrasound probe; and an impedance matching or low-pass network combined with the cable and transducer element. The MD PAM clock may operate at a 80 to 0MHz frequency range, however the wide band transformer needs only to work in the frequency band of the dummy load (0pF//.0k). Besides the bandwidth consideration, the small transformer should be designed using a ferrite magnetic core selected to give high enough saturation current and low leakage inductance. Doc.# DSDB-MDDB A070

3 MDDB M0 8 M 0 M 9 M C7 IN OUT OUT OUT 7 7 WAV FRE PAM AMPL A 9 TMS 0 TDI TDO TCK EXTRG 9 CLKIN NC NC 0 NC0 7 B 7 A R 0 B0 B B B B B B B7 B8 B9 B0 B C D E F G H J K L M N TP U XC97XL_VQ Z Y X V U PWR TP PB VGG R7 0 I Circuit Schematic J7 D PH0 DAC PWR MH MH MH MH TP U LM00 C J JTAG C C 7nF PA DB DB SDI SDO SCK CS LD D YLW R 00 + (+.V) VGG MB DNDK R.0 W C VPP R9 00 W OUTPUT C8.nF J EX = 0 R k VLL C 7nF (+.V) VGG VSUB VLL 8 7 CA KA CA R k M0 M M M SDI SDO SCK CS LD D PA 9 PA 8 PA VSUB VSUB PB PB PB A VREF RFB CB CB KB CB CA 0 TP U MDK7 (+70 to 00V) VPP C 0 V + D8A J XDCR-A C TP J EXCLK J EXTRG R7 0 TP C (+.V) C9 0p 0V R0 00 R7 k PH0 C µ 00V R k W X FXO-HC7-0 OUT SDI SDO SCK CS LD C R 9.9k (+.0V) D7A TP NC9 8 NC8 0 NC7 9 NC SDI SDO SCK CS LD TP TP0 TP TP8 TP DA DA D7B D9 B00- R 0 TP9 7 7 NC NC NC NC NC 9 TMS 0 TDI TDO TCK BB 7 AA EXTRG 9 CLKIN LED LED 0 PWR 7 IO CC DD EE FF GG HH II JJ KK LL MM NN U XC97XL_VQ D YLW D RED D GRN R k R k R k DAC C9 TP7 R8.0 W C D J SW C0 C SW R 00 R 00 R8 k C7 C8 C SW SW SW R 00 R 00 R 00 R9 k R0 k R k B0 B B B B B B B7 B8 B9 B0 B C7 C8 TP0 C9 C0 C TP8 TP9 TP7 TP TP C C 7nF C C 7nF C 7nF C 7nF C 0 V C.nF C C7 MA DNDK C8 µ 00V R 00 W C9 VLL C0 TP T EP0_EP (+.V) R8 VLL U ADP9AKC-.RL7 C 0 V + 0 D8B Doc.# DSDB-MDDB A070

4 MDDB PCB Layout MDDB Demoboard Actual Dimensions: 0.cm x 7.cm (.00 x.00 ) Doc.# DSDB-MDDB A070

5 MDDB +.V +.0V VLL CA CA KA CA +.0V +.V M0 M M M PAM Level Select Level Translator A B Beamform Switch Matrix PA D M DN +70 to 00V V PP (WE ) TP Leakage µh kω 0pF SDI SDO SCK CS LD Data Latch & Control Logic DAC SUB PB D DN +.0V +.V M Test Load D A VREF RFB CB CB KB CB +V REF MDDB Input and Output Waveforms Figure : Output waveform of -sample/cycle f S = 0MHz, V PP = 7V, 0pF//.0kΩ load. LV = (0, -, -, -, -, -, -, 0, 0,,,,,,, 0,...) cycles Doc.# DSDB-MDDB A070

6 MDDB Figure : Output waveform of -sample/cycle of 7.MHz DAC =, V PP = 7V, 0pF//.0kΩ load Figure : Example of Gauss-Sine waveform for LV~LV SPI register values and transmit sequence. The level-registers in MD store 7 positive and 8 negative numbers and control the M[:0] to transmit these levels. Use the sequence below and its reverse order. Including zeros, there are a total of transmitted data samples. LV = (0, 0,,,, 0, 0, -, -, -0, -9, -8, -, -8, -, -, -,,, 7, 0,, 7,.. ) Doc.# DSDB-MDDB A070

7 MDDB Voltage (V) Time (ns) Figure : Output waveform and polarity reversed Gauss-Sine waveform at -sample/cycle of 7.MHz DAC =, V PP = 7V, 0pF//.0kΩ load. Figure : Gauss-Sine waveform at -sample/cycle of 7.MHz DAC =, V PP = 7V, 0pF//.0kΩ load. Doc.# DSDB-MDDB A070 7

8 MDDB Figure : MDDB.MHz Gauss-Sine waveforms and frequency spectrum. Current Level Control Pin Description Input Control Pin Name M M M M0 PAM Current Level Description LV0 PA & PB both off, zero current LV Select LV current magnitude to PA LV Select LV current magnitude to PA. 0 0 LV Select LV current magnitude to PA LV Select LV current magnitude to PA. 0 0 LV Select LV current magnitude to PA. 0 0 LV Select LV current magnitude to PA. 0 LV7 Select LV7 current magnitude to PA LV8 Select LV8 current magnitude to PB. 0 0 LV9 Select LV9 current magnitude to PB. 0 0 LV0 Select LV0 current magnitude to PB. 0 LV Select LV current magnitude to PB. 0 0 LV Select LV current magnitude to PB. 0 LV Select LV current magnitude to PB. 0 LV Select LV current magnitude to PB. LV Select LV current magnitude to PB. Note: Turning on PA & PB simultaneously can cause over-current and permanent damage to the IC, high voltage MOSFETs, or to the transformer. Doc.# DSDB-MDDB A070 8

9 Board Connector and Test Pin Description CPLD Pin # Signal Name Description U, -,, CPLD logic power supply +.V U, - VLL CPLD, IO and MD logic power supply +.V U, -, 7, Logic power ground 0V U - WAV Run or stop demo waveform phase U - FRE Selecting frequency: 8,0 and.mhz U - PHASE Single step phase change, angle stepping:0, 7., 0 U - AMPL Single step amplitude change, DAC stepping:, U - 7 A Control MD pin U - 8 M Output signal to MD M U - 9 M0 Output signal to MD M0 U - 0 M Output signal to MD M U - M Output signal to MD M U - LED Output signal yellow, PH0 LED is on when phase = 0 U - 0 LED Output signal yellow, DAC LED is on when DAC = 7 U - 7 PWR Output signal LED green, indicates +.V power supply on U, - 0 TMS Test mode select of JTAG U, - 9 TDI Test data in of JTAG, two CPLD in daisy chain U, - TDO Test data out of JTAG, two CPLD in daisy chain U, - TCK Test clock of JTAG U, - CLK CPLD clock input U, - 9 EXTRG External trigger signal input to control waveform timing U, - Output signal LED red, indicates MD is enabled U - SDI Output signal to MD SDI U - SDO Input signal from MD SDO U - SCK Output signal to MD SCK U - CS Output signal to MD CS U - LD Output signal to MD LD All remaining pins NC or Reserved MDDB Doc.# DSDB-MDDB A070 9

10 MDDB JTAG Connector Pin # Signal Name Description J- TMS Test Mode Select of CPLD. J- TDI Test Data In of CPLD. J- TDO Test Data Out of CPLD. J- TCK Test Clock of CPLD. J- Logic power supply ground 0V for programming only. J- Logic power supply +.V for programming only. Signal and Jumper Pin # Signal Name Description J EXCLK External clock input when on-board oscillator is disabled, or output of the clock when it is enabled. J OSC_ Jumper for on-board oscillator, short = disabled, open = enabled. J EXTRG External trigger signal input. J Load JP Jumper for on-board RC load to MDDB high voltage output and XDCR connector. J XDCR MDDB waveform output, for SMA-cable to oscilloscope, high voltage! 0 to +/-0V P-P max. Power Supply Connector J7- +.V, MOSFET gate biasing and CPLD supply voltage with current limit from 0 to 0mA. J7- Ground reference, 0V. J7- +.0V MD positive supply voltages with current limit to 0mA J7- Ground reference, 0V. J7- VPP +70 to00v, the high voltage supply with current limit to 0mA. Voltage Supply Power-Up Sequence Step Signal Name Description V DD +.0, MD positive supply voltages V CC +.V, MOSFET gate biasing and CPLD control logic supply voltage V PP +70V to 00V, the high voltage supply Logic Active Enable logic control, active-high signal to MD Voltage Supply Power-Down Sequence Logic Active Disable logic control, active-high signal to MD V PP +70V to 00V, the high voltage supply, off V DD +.0V, MD positive supply voltages with all input signals LOW, off V CC +., CPLD control logic supply voltage with = 0, off Doc.# DSDB-MDDB A070 0

11 MDDB Bill of Materials Reference Description Manufacturer s Part Number MDDB Manufacturer C - C, C, C7, C0, C - C, C7, CAP.µF V CERAMIC X7R 00 ECJ-VBE0K Panasonic C9 - C, C, C7 - C9 C, C8 CAP CER 00PF 0% 00V X7R 00 00CKATA AVX C, C, C, C, C, C CAP.07µF 0V CERAMIC X7R 00 ECJ-VBH7K Panasonic C8,C CAP CER µf 00V X7R 0% 0 CX7RA0M TDK C9 CAP CERAMIC 0PF 00V NP0 080 ECJ-YCDJ Panasonic C, C, C CAP 0µF V ELECT WT SMD UWTC00MCLGB Nichicon D, D LED THIN 8NM YEL DIFF 080 SMD SML-LXT080YW-TR Lumex D LED THIN NM RED DIFF 080 SMD SML-LXT080IW-TR Lumex D LED THIN NM GRN DIFF 080 SMD SML-LXT080GW-TR Lumex D9 Diode Schottky, 00V,.0A, SMA B00- Diodes Inc. D - D8 Diode Schottky, dual, 0V, SOT- BATDW-7 Diodes Inc. M 0V.0A dual depletion N-MOSFET, xmm, DFN-8 DNDK-G Supertex Inc. R RES.00kΩ /W % 00 SMD ERJ-EKF00V Panasonic R, R7 RES 9.9Ω /W % 00 SMD ERJ-EKF9R9V Panasonic R - R, R0, R, R - R RES 00Ω /W % 00 SMD ERJ-EKF000V Panasonic R8,R RES.0Ω W % SMD ERJ-TRQFR0U Panasonic R9,R RES 00Ω W % SMD ERJ-TNF000U Panasonic R,R7 PCB copper short NA NA R RES kω W % SMD ERJ-TYF0U Panasonic R RES 9.9kΩ /W % 00 SMD ERJ-EKF99V Panasonic R7, R8, R9, R0, R RES.kΩ /W % 00 SMD ERJ-EKFV Panasonic R8 PCB copper short NA NA T µh, :: wideband ultrasound pulse transformer Würth Electronics U IC ultrasound beamforming source driver 0-Lead QFN MDK7-G Supertex Inc. U, U IC CPLD, 7 MCELL, C-Temp, -VQFP XC97XL-VQC Xilinx U IC precision reference micropower ref, SOT- LM00DEM-. National U IC voltage regulator,.a,.v, SOT- ADP9AKC-. ADI X Oscillator clock, 0.000MHz,.V, SMD JITO--DCAE-0 FOX Electronics does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 0 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSDB-MDDB A070 Bordeaux Drive, Sunnyvale, CA 9089 Tel:

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