Single Comparator with Known Power-Up State ADCMP391

Transcription

1 FEATURES Single-supply voltage operation:.3 to 5.5 Rail-to-rail common-mode input voltage range Low input offset voltage across CMR: 1 m typical Guarantees comparator output logic low from CC 0.9 to undervoltage lockout (ULO) Operating temperature range: 40 C to +15 C 8-lead, narrow body SOIC APPLICATIONS Battery management/monitoring Power supply detection Window comparators Threshold detectors/discriminators Microprocessor systems Single Comparator with Known Power-Up State FUNCTIONAL BLOCK DIAGRAM CC IN+ OUT IN GND Figure GENERAL DESCRIPTION The is a single, rail-to-rail input, low power comparator ideal for use in general-purpose applications. The device operates from a single supply voltage of.3 to 5.5 and draws a minimal amount of current. The consumes only 18.6 µa of supply current. The low voltage and low current operation of the makes it ideal for battery-powered systems. The features a common-mode input voltage range of 00 m beyond rails, an offset voltage of 1 m typical across the full common-mode range, and a ULO monitor. In addition, the design of the comparator allows a defined output state upon power-up. The comparator generates a logic low output if the supply voltage is less than the ULO threshold. The is available in an 8-lead, narrow body SOIC package. The is specified to operate over the extended temperature range of 40 C to +15 C. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 General Description... 1 Revision History... Specifications... 3 Absolute Maximum Ratings... 4 Thermal Resistance... 4 ESD Caution... 4 Pin Configuration and Function Descriptions... 5 Typical Performance Characteristics... 6 Theory of Operation... 9 Basic Comparator... 9 Rail-to-Rail Input (RRI)... 9 Data Sheet Open-Drain Output...9 Power-Up Behavior...9 Crossover Bias Point...9 Comparator Hysteresis...9 Typical Applications Adding Hysteresis Window Comparator for Positive oltage Monitoring Window Comparator for Negative oltage Monitoring Programmable Sequencing Control Circuit Mirrored oltage Sequencer Example Threshold and Timeout Programmable oltage Supervisor Outline Dimensions Ordering Guide REISION HISTORY 8/14 Revision 0: Initial ersion Rev. 0 Page of 15

3 SPECIFICATIONS CC.3 to 5.5, TA 40 C to +15 C, CMR 00 m to CC + 00 m, unless otherwise noted. Typical values are at TA 5 C. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments 1 POWER SUPPLY Supply oltage CC ULORISE Guarantees comparator output low CC Quiescent Current ICC μa All outputs in high-z state, OD μa All outputs low, OD 0.1 UNDEROLTAGE LOCKOUT CC Rising ULORISE Hysteresis ULOHYS m COMPARATOR INPUT Common-Mode Input Range CMR 00 CC + 00 m Input Offset oltage OS m IN+ IN m IN+ IN 1, TA 40 C to +85 C 1 5 m 1 5 m TA 40 C to +85 C Input Offset Current IOS 10 na CMR 50 m to CC + 50 m Input Bias Current IBIAS ±30 na IN+ IN 1 ±80 na CMR 50 m to CC + 50 m ±10 na CMR 50 m to CC + 50 m, TA 40 C to +85 C Input Hysteresis HYST 3 4 m CM m COMPARATOR OUTPUT Output Low oltage OL CC.3, ISINK.5 ma CC 0.9, ISINK 100 μa Output Leakage Current ILEAK 150 na OUT 0 to 5.5 COMPARATOR CHARACTERISTICS Power Supply Rejection Ratio PSRR db Common-Mode Rejection Ratio CMRR db oltage Gain A 13 db Rise Time tr 1.1 μs OUT 10% to 90% of CC Fall Time tf 0.15 μs OUT 90% to 10% of CC Propagation Delay Input Rising tprop_r 4.7 μs CM 1, CC.3, OD 10 m 4.9 μs CM 1, CC 5, OD 10 m.8 μs CM 1, CC.3, OD 100 m 3. μs CM 1, CC 5, OD 100 m Input Falling tprop_f 4.5 μs CM 1, CC.3, OD 10 m 9.5 μs CM 1, CC 5, OD 10 m μs CM 1, CC.3, OD 100 m 4. μs CM 1, CC 5, OD 100 m 1 OD is overdrive voltage. RPULLUP 10 kω, and CL 50 pf. Rev. 0 Page 3 of 15

4 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating CC Pin 0.3 to +6 IN+ and IN Pins 0.3 to +6 OUT Pin 0.3 to +6 OUT Pin Sink Current (ISINK) 10 ma Storage Temperature Range 65 C to +150 C Operating Temperature Range 40 C to +15 C Lead Temperature (10 sec) 300 C Junction Temperature 150 C THERMAL RESISTANCE Data Sheet Table 3. Thermal Resistance Package Type θja Unit 8-Lead Narrow-Body SOIC 11 C/W ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 Page 4 of 15

5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NIC 1 IN IN+ 3 GND 4 TOP IEW (Not to Scale) NIC CC OUT NIC NOTES 1. NIC NOT INTERNALLY CONNECTED. Figure. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1, 5, 8 NIC Not Internally Connected IN Comparator Inverting Input 3 IN+ Comparator Noninverting Input 4 GND Device Ground 6 OUT Comparator Output, Open-Drain 7 CC Device Supply Input Rev. 0 Page 5 of 15

6 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INPUT OFFSET OLTAGE (m) SAMPLE 1 SAMPLE SAMPLE 3 INPUT OFFSET OLTAGE (m) T A +5 C T A +85 C T A +15 C T A 40 C COMMON-MODE OLTAGE () Figure 3. Input Offset oltage (OS) vs. Common-Mode oltage (CM), CC SUPPLY OLTAGE () Figure 6. Input Offset oltage (OS) vs. Supply oltage (CC), CM 1 for arious Temperatures INPUT OFFSET OLTAGE (m) CC.3 CC 3.3 CC 5.5 OUTPUT OLTAGE () IN+ IN + 10m CM IN TEMPERATURE ( C) Figure 4. Input Offset oltage (OS) vs. Temperature for arious Supply oltages (CC), CM SUPPLY OLTAGE () Figure 7. Output oltage (OUT) vs. Supply oltage (CC), RPULLUP 10 kω SUPPLY CURRENT (µa) T A +5 C T A +85 C T A +15 C T A 40 C SUPPLY CURRENT (µa) T A +5 C T A +85 C T A +15 C T A 40 C SUPPLY OLTAGE () Figure 5. Supply Current vs. Supply oltage (CC) at Output Low oltage for arious Temperatures SUPPLY OLTAGE () Figure 8. Supply Current vs. Supply oltage (CC) at Output High oltage for arious Temperatures Rev. 0 Page 6 of 15

7 SUPPLY CURRENT (µa) SUPPLY CURRENT (µa) TEMPERATURE ( C) TEMPERATURE ( C) Figure 9. Supply Current vs. Temperature at Output High oltage for arious Supply oltages (CC) Figure 1. Supply Current vs. Temperature at Output Low oltage for arious Supply oltages (CC) INPUT HYSTERESIS (m) CC.3 CC 3.3 CC TEMPERATURE ( C) Figure 10. Input Hysteresis vs. Temperature for arious Supply oltages (CC), CM INPUT HYSTERESIS (m) T A +5 C T A +85 C 1.9 T A +15 C T A 40 C SUPPLY OLTAGE () Figure 13. Input Hysteresis vs. Supply oltage (CC) for arious Temperatures, CM CC.3 CC 3.3 CC 5.5 R PULLUP 10kΩ OD 10m C L 50pF CM CC.3 CC 3.3 CC 5.5 R PULLUP 10kΩ OD 10m C L 50pF CM 1 PROPAGATION DELAY (µs) PROPAGATION DELAY (µs) TEMPERATURE ( C) Figure 11. Propagation Delay vs. Temperature, Low to High, OD 10 m TEMPERATURE ( C) Figure 14. Propagation Delay vs. Temperature, High to Low, OD 10 m Rev. 0 Page 7 of 15

8 Data Sheet CC.3 CC 3.3 CC 5.5 R PULLUP 10kΩ C L 50pF CM CC.3 CC 3.3 CC 5.5 PROPAGATION DELAY (µs) PROPAGATION DELAY (µs) INPUT OERDRIE OLTAGE (m) Figure 15. Propagation Delay vs. Input Overdrive oltage, Low to High INPUT OERDRIE OLTAGE (m) Figure 17. Propagation Delay vs. Input Overdrive oltage, High to Low CC 3.3 C L 50pF CC 3.3 C L 50pF OUTPUT OLTAGE RISE TIME (µs) OUTPUT OLTAGE FALL TIME (µs) PULL-UP RESISTANCE (kω) Figure 16. Output oltage Rise Time (tr) vs. Pull-Up Resistance (RPULLUP) PULL-UP RESISTANCE (kω) Figure 18. Output oltage Fall Time (tf) vs. Pull-Up Resistance (RPULLUP) Rev. 0 Page 8 of 15

9 THEORY OF OPERATION BASIC COMPARATOR In its most basic configuration, a comparator can be used to convert an analog input signal to a digital output signal (see Figure 19). The analog signal on IN+ is compared to the voltage on IN, and the voltage at OUT is either high or low, depending on whether IN+ is at a higher or lower potential than IN, respectively. IN + 0 IN+ IN IN CC + OUT OUT Figure 19. Basic Comparator and Input and Output Signals RAIL-TO-RAIL INPUT (RRI) Using a CMOS nonrri stage (that is, a single differential pair) limits the input voltage to approximately one gate-to-source voltage (GS) away from one of the supply lines. Because GS for normal operation is commonly more than 1, a single differential pair input stage comparator greatly restricts the allowable input voltage. This restriction can be quite limiting with low voltage supplies. To resolve this issue, RRI stages allow the input signal range to extend up to the supply voltage range. In the case of the, the inputs continue to operate 00 m beyond the supply rails. OPEN-DRAIN OUTPUT The has an open-drain output stage that requires an external resistor to pull up to the logic high voltage level when the output transistor is switched off. The pull-up resistor must be large enough to avoid excessive power dissipation, but small enough to switch logic levels reasonably quickly when the comparator output is connected to other digital circuitry. The rise time of the open-drain output depends on the pull-up resistor (RPULLUP) and load capacitor (CL) used. The rise time can be calculated by tr.197 RPULLUP CL (1) t POWER-UP BEHAIOR On power-up, when CC reaches 0.9, the is guaranteed to assert an output low logic. When the voltage on the CC pin exceeds ULO, the comparator inputs take control. CROSSOER BIAS POINT Rail-to-rail inputs of this type of architecture, in both op amps and comparators, have a dual front-end design. PMOS devices are inactive near the CC rail, and NMOS devices are inactive near GND. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally 0.8 and CC 0.8, the measured offset voltages change. COMPARATOR HYSTERESIS In noisy environments, or when the differential input amplitudes are relatively small or slow moving, adding hysteresis (HYST) to the comparator is often desirable. The transfer function for a comparator with hysteresis is shown in Figure 0. As the input voltage approaches the threshold (0 in Figure 0) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +HYST/. The new switch threshold becomes HYST/. The comparator remains in the high state until the HYST/ threshold is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on the 0 input cannot cause the comparator to switch states unless it exceeds the region bounded by ±HYST/. HYST OUTPUT OL 0 OH INPUT + HYST Figure 0. Comparator Hysteresis Transfer Function Rev. 0 Page 9 of 15

10 TYPICAL APPLICATIONS ADDING HYSTERESIS To add hysteresis, see Figure 1; two resistors are used to create different switching thresholds, depending on whether the input signal is increasing or decreasing in magnitude. When the input voltage increases, the threshold is above, and when the input voltage decreases, the threshold is below. CC 5 Data Sheet WINDOW COMPARATOR FOR POSITIE OLTAGE MONITORING When monitoring a positive supply, the desired nominal operating voltage for monitoring is denoted by M, IM is the nominal current through the resistor divider, O is the overvoltage trip point, and U is the undervoltage trip point. M.5 IN R1 IN+ IN OUT R PULLUP R LOAD R X PH R Y IN+ IN U1 OUT1 R PL IN+ IN U OUT OUT R Z Figure. Positive Undervoltage/Overvoltage Monitoring Configuration Figure 1. Noninverting Comparator Configuration with Hysteresis The upper input threshold level is given by IN_HI ( R1+ R) () R Assuming RLOAD >> R, RPULLUP. The lower input threshold level is given by IN ( R1+ R + R ) PULLUP CCR1 _ LO (3) R + R PULLUP The hysteresis is the difference between these voltages levels. Δ R1 IN IN_LO IN_HI CC IN (4) R + RPULLUP Figure illustrates the positive voltage monitoring input connection. Three external resistors, RX, RY, and RZ, divide the positive voltage for monitoring, M, into the high-side voltage, PH, and the low-side voltage, PL. The high-side voltage is connected to the IN+ pin of U1 and the low-side voltage is connected to the IN pin of U. To trigger an overvoltage condition, the low-side voltage (in this case, PL) must exceed the threshold on the IN+ pin of U. Calculate the low-side voltage, PL, by the following: R Z PL O RX + RY + RZ (5) In addition, RX + RY + RZ M/IM (6) Therefore, RZ, which sets the desired trip point for the overvoltage monitor, is calculated as ( )( M ) R Z I (7) ( )( ) O M To trigger the undervoltage condition, the high-side voltage, PH, must be less than the threshold on the IN pin of U1. The high-side voltage, PH, is calculated by R Y + RZ PH U (8) RX + RY + RZ Because RZ is already known, RY can be expressed as ( )( M ) RY R (9) I ( )( ) Z U M When RY and RZ are known, RX can be calculated by RX (M/IM) RY RZ (10) If M, IM, O, or U changes, each step must be recalculated. Rev. 0 Page 10 of 15

11 WINDOW COMPARATOR FOR NEGATIE OLTAGE MONITORING Figure 3 shows the circuit configuration for negative supply voltage monitoring. To monitor a negative voltage, a reference voltage is required to connect to the end node of the voltage divider circuit, in this case,. R Z NH R Y NL IN+ IN IN+ IN U1 U OUT1 OUT Because RZ is already known, RY can be expressed as follows: ( M ) RY R (15) I M ( ) Z U When RY and RZ are known, RX is then calculated by ( M ) RX RY RZ (16) I M PROGRAMMABLE SEQUENCING CONTROL CIRCUIT The circuit shown in Figure 4 is used to control the power supply sequencing. The delay is set by the combination of the pull-up resistor (RPULLUP), the load capacitor (CL), and the resistor divider network. / CC Figure 3. Negative Undervoltage/Overvoltage Monitoring Configuration Equation 7, Equation 9, and Equation 10 need some minor modifications for use with negative voltage monitoring. The reference voltage,, is added to the overall voltage drop; therefore, it must be subtracted from M, U, and O before using each of them in Equation 7, Equation 9, and Equation 10. To monitor a negative voltage level, the resistor divider circuit divides the voltage differential level between and the negative supply voltage into the high-side voltage, NH, and the low-side voltage, NL. The high-side voltage, NH, is connected to IN+ of U1, and the low-side voltage, NL, is connected to IN of U. To trigger an overvoltage condition, the monitored voltage must exceed the nominal voltage in terms of magnitude, and the high-side voltage (in this case, NH) on the IN+ pin of U1 must be more negative than ground. Calculate the high-side voltage, NH, with the following formula: RX + R Y NH GND ( O ) + O (11) RX RY R + + Z In addition, ( M ) RX + RY + RZ (1) I M Therefore, RZ, which sets the desired trip point for the overvoltage monitor, is calculated by ( M ) RZ (13) I M R X ( ) O M To trigger an undervoltage condition, the monitored voltage must be less than the nominal voltage in terms of magnitude, and the low-side voltage (in this case, NL) on the IN pin of U must be more positive than ground. Calculate the low-side voltage, NL, by the following: R X NL GND ( U ) + U RX RY R (14) + + Z Rev. 0 Page 11 of 15 SEQ R PULLUP C L OUT4 OUT3 OUT OUT1 Figure 4. Programmable Sequencing Control Circuit Figure 5 shows a simplified block diagram for the programmable sequencing control circuit. The application delays the enable signal, EN, of the external regulators (LDO x) in a linear order when the open-drain signal (SEQ) changes from low to high impedance. The has a defined output state during startup, which prevents any regulator from turning on if CC is still below the ULO threshold. 3.3 / CC t 1 t SEQ t 3 t 4 GND Figure 5. Simplified Block Diagram of a Programmable Sequencing Control Circuit R5 R4 R3 R R1 U4 U3 U U1 IN OUT LDO 1 EN GND IN OUT LDO EN GND IN OUT LDO 3 EN GND IN OUT LDO 4 EN GND

12 Data Sheet SEQ CL OUT4 OUT3 OUT OUT1 Figure 6. Programmable Sequencing Control Circuit Timing Diagram When the SEQ signal changes from low to high impedance, the load capacitor, CL, starts to charge. The time it takes to charge the load capacitor to the pull-up voltage (in this case, or CC) is the maximum delay programmable in the circuit. It is recommended to have the threshold within 10% to 90% of the pull-up voltage. Calculate the maximum allowable delay by tmax tr.197 RPULLUP CL (17) The delay of each output is changed by changing the threshold voltage, 1 to 4, when the comparator changes its output state. To calculate the voltage thresholds for the comparator, use the following formulas: t 1 RPULLUPC 1 L 1 e (18) 3 t 1 1 t t PULLUP R C L 1 e (19) t 3 PULLUP R C L 1 e (0) t 4 t 3 t 4 RPULLUPC 4 L 1 e (1) The threshold voltages can come from a voltage reference or a voltage divider circuit, as shown in Figure First, determine the allowable current, IDI, flowing through the resistor divider. After the value for IDI is determined, calculate R1, R, R3, R4, and R5 using the following formulas: R R1+ R + R3 + R4 R5 () I DI + 1R DI DI R1 (3) R R DI R1 (4) 3RDI R3 R1 R (5) 4RDI R4 R1 R R3 (6) R5 RDI R1 R R3 R4 (7) To create a mirrored voltage sequence, add a resistor, RMIRROR, between the pull-up resistor (RPULLUP) and the load capacitor (CL) as shown in Figure 7. SEQ / CC R PULLUP R MIRROR C L OUT4 OUT3 OUT OUT1 Figure 7. Circuit Configuration for a Mirrored oltage Sequencer Figure 7 shows the circuit configuration for a mirrored voltage sequencer. When SEQ changes from low to high impedance, the response is similar to Figure 6. When SEQ changes from high impedance to low, the load capacitor (CL) starts to discharge at a rate set by RMIRROR. The delay of each comparator is dependent on the threshold voltage previously set for t1 to t4. The result is a mirrored power-down sequence. R5 R4 R3 R R1 U4 U3 U U Rev. 0 Page 1 of 15

13 SEQ CL OUT4 t 4 t 5 OUT3 t 3 t 6 OUT t t 7 OUT1 t 1 t Figure 8. Mirrored oltage Sequencer Timing Diagram The timing diagram for the mirrored voltage sequencer is shown in Figure 8. Equation 18 through Equation 1 must account for the additional resistance, RMIRROR, in the calculations of the voltage thresholds. To calculate these new thresholds, see Equation 8 through Equation 31. t 1 ( RPULLUP + RMIRROR ) CL 1 1 e (8) t ( RPULLUP + RMIRROR ) CL 1 e (9) t 3 ( RPULLUP + RMIRROR ) CL 3 1 e (30) t 4 ( RPULLUP + RMIRROR ) CL 4 1 e (31) RMIRROR provides the mirrored delay by prolonging the discharge time of the capacitor. The mirrored voltage sequencer uses the same threshold in Equation 8 to Equation 31 in a decreasing order. To calculate the exact value of the mirrored delay time, see Equation 3 through Equation 35. t t t R R R MIRROR MIRROR MIRROR 4 C Lln (3) 3 C Lln (33) CLln (34) 1 t 8 RMIRRORCLln (35) MIRRORED OLTAGE SEQUENCER EXAMPLE To illustrate how the mirrored voltage sequencer works, see Figure 5 and then consider a system that uses a of 1 and requires a delay of 50 ms when SEQ changes from low to high impedance, and between each regulator when turning on. These considerations require a rise time of at least 00 ms for the pull-up resistor (RPULLUP) and the load capacitor (CL). The sum of the resistance of RMIRROR and RPULLUP must be large enough to charge the capacitor longer than the minimum required delay. For a symmetrical mirrored power-down sequence, the value of RMIRROR must be much larger than RPULLUP. A 10 kω RPULLUP value limits the pull-down current to 100 µa while giving a reasonable value for RMIRROR. A typical 1 µf capacitor together with a 150 kω RMIRROR value gives a value of tmax.197(( ) ( )) 351 ms (36) The threshold voltage required by each comparator is set by Equation 8 to Equation 31. For example, e where m Therefore, m, m, and m. Next, consider 10 µa as the maximum current (IDI) flowing through the resistor divider network. This current gives the total resistance of the divider network (RDI) and the individual resistor values using Equation to Equation 7, resulting in the following: RDI 100 kω R kω 6.7 kω R kω 19.6 kω R kω 14.3 kω R kω 10.5 kω R kω 8.7 kω Rev. 0 Page 13 of 15

14 Resistor values from the calculation are nonindustry standard, using industry standard resistor values resulted in a new RDI value of 99.8 kω. Due to the discrepancy of the calculated resistor value to the industry standard value, the threshold of each comparator also changed. Calculate the new threshold values by using a simple voltage divider formula: 1 R1/RDI (37) where 1 1 ( 6.7 kω) 99.8 kω m. Therefore, m, m, and m. Because the threshold of each comparator has changed, the time when each comparator changes its output has also changed. Calculate the new delay values for each comparator by using the following equation: ( ) 1 t1 CL RPULLUP + RMIRROR ln 1 (38) m where t1 1 µf(10 kω kω)ln ms. 1 Therefore, t ms, t ms, and t ms. To calculate t5 through t8, use Equation 3 to Equation 35: t 5 R MIRROR C Lln m where t5 150 kω 1 µf ln ms. 1 Therefore, t ms, t ms, and t ms. THRESHOLD AND TIMEOUT PROGRAMMABLE OLTAGE SUPERISOR Figure 9 shows a circuit configuration for a programmable threshold and timeout circuit. The timeout, treset, defines the duration that the input voltage (IN) must be kept above the threshold voltage to toggle the RESET signal, preventing the device from operating when IN is not stable. If IN falls below the threshold voltage, the RESET signal toggles quickly. IN RESET TH t RESET t RESET Data Sheet Figure 30. Threshold and Timeout Programmable oltage Supervisor Timing Diagram During startup, the guarantees a low output state when CC is still below the ULO threshold, preventing the voltage supervisor from toggling. When IN reaches the threshold set by the resistor divider (R1 and R) and, OUT1 changes from low to high and starts to charge the timeout capacitor (CT). If IN is kept above the threshold voltage and the voltage in CT reaches, OUT toggles. If IN falls below the threshold voltage while CT is charging, the timeout capacitor quickly discharges, preventing OUT from toggling while IN is not stable. In the condition that IN is tied to CC, the circuit operates when CC is more than the minimum operating voltage. The threshold voltage (TH) is configured by changing the resistor divider or. Calculate the threshold voltage by R1 TH 1 + (39) R Timeout is adjusted by changing the values of the pull-up resistor or the timeout capacitor. To set the timeout value, determine the allowable current flowing through RPULLUP and IPULLUP. When IPULLUP is known, calculate RPULLUP and CT by the following formulas: RPULLUP CC/IPULLUP (40) treset C (41) T R PULLUPln 1 CC IN CC R1 R PULLUP R U1 OUT1 C T U OUT RESET Figure 9. Programmable Threshold and Timeout Circuit Rev. 0 Page 14 of 15

15 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) (0.441) 5.80 (0.84) 0.5 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.7 (0.0500) BSC 1.75 (0.0688) 1.35 (0.053) 0.51 (0.001) 0.31 (0.01) (0.0098) 0.17 (0.0067) 0.50 (0.0196) 0.5 (0.0099) 1.7 (0.0500) 0.40 (0.0157) 45 COMPLIANT TO JEDEC STANDARDS MS-01-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIALENTS FOR ERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) A ORDERING GUIDE Model 1 Temperature Range Package Description Package Option ARZ 40 C to +15 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ARZ-RL7 40 C to +15 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 Z RoHS Compliant Part. 014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /14(0) Rev. 0 Page 15 of 15