REAL TIME IMPLEMENTATION OF FPGA BASED PULSE CODE MODULATION MULTIPLEXING

Size: px

Start display at page:

Download "REAL TIME IMPLEMENTATION OF FPGA BASED PULSE CODE MODULATION MULTIPLEXING"

Natalie Brown
5 years ago
Views:

Volume 119 No. 15 2018, 1415-1423 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.

1 Volume 119 No , ISSN: (on-line version) url: REAL TIME IMPLEMENTATION OF FPGA BASED PULSE CODE MODULATION MULTIPLEXING 1 Joseph Anthony Prathap, 2 T.S.Anandhi, 3 S.Karunakaran, 4 S.Lavanya 1 Associate Professor, 3 Professor, Vardhaman College of Engineering, Shamshabad, Hyderabad, Telangana. 2 Associate Professor, Annamalai University, Chidambaram,Tamil Nadu 4 Manager, Selvam Enterprises, Puducherry 1 japtuhi1116@gmail.com Abstract:- The Pulse Code Modulation is the vital part of Analog to Digital Converter (ADC). The PCM includes the process of sampling and quantization in order to digitize the analog input along the time scale and amplitude scale respectively. This project aims to design the Pulse Code Modulation Multiplexer (PCMM) in which analog inputs with different frequencies are multiplexed and pulse code modulated. The PCMM is developed using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The proposed Pulse Code Modulated Multiplexer is validated by comparing the design parameters like power and area, implemented in the Xilinx Spartan Field Programmable Gate Array (FPGA). Keywords: Pulse Code Modulation, Multiplexing, Field Programmable Gate Array, Power and Area Analysis I INTRODUCTION Pulse code modulation (PCM) is a digital modulation technique which takes the analog input and generates binary sequences. The PCM is used in many real time applications like mpeg video, speech signals, telemetry, complicated communication systems and virtual reality (VR).Conventionally, the PCM coded signals are not easily disturbed by interferences. PCM involves two major techniques. Sampling- Digitizing along the x-axis. Sampling is defined as converting an analog (continuous) signal into a digital (discrete) signal. Quantization- digitizing along the Y-axis, quantization is the process of matching a set of input values to a definite set. Quantization is involved in almost digital signal processing, as the process of representing a signal in digital form ordinarily involves rounding. The encoding ensures the PCM signals to be within limits. The DPCM based compression technique implemented in FPGA is used for image compression [1]. The PCM decommutator used for satellite data acquisition of ground when implemented using the FPGA reduces the power consumption by 20% [2]. The GSM-SMS based on PCM is advantages in the transfer of voice messages compared to the conventional Huffman Coding method [3]. A flexible microphone array is used with the PCM coded signals and implemented using the FPGA [4]. The PCM signals are sent through single line out by the multiplexing technique is developed using the MATLAB-SIMULINK block [5] In this paper, the Pulse Code Modulation Multiplexing (PCMM) is implemented using the FPGA. The PCMM is a system where multiple analog signals can be encoded as part of transmitting process without interfering between information frequencies. Each signal waveform is quantized and represented to sufficient accuracy by an appropriate code character. Each code character is composed of a specified number of code elements. The code elements can be chosen as two-level, or binary; three-level, or ternary; or n-ary. However, general practice is to use binary, since it is not affected as much by interference introduced by the required increased bandwidth. This binary stream code which represents the multi input information signals is transmitted over signal channel then de-multiplexed at the receiver according to each frequency signal.the motivation behind modern PCM is that improved implementation techniques of solid-state circuitry allow extremely fast quantization of samples and translation to complex codes with reasonable equipment constraints. PCM is an attractive way to trade bandwidth for signal-to- noise and has the additional advantage of transmission through 1415

2 regenerative repeaters with a signal-to-noise ratio that is substantially independent of the number of repeaters. The proposed method is real time implemented using the Spartan FPGA device. The FPGA is advantages for features like parallel computing, flexibility, upgradable and easy debugging. The HDL coded PCM with 24 bit resolution is utilised in the FPGA based Telecommunication Trainer Kit [6]. The ADPCM encoder and decoder is implemented using the Verilog HDL in Simulation [7]. FPGA is utilized for the speech enhancement filtering process [8].The next section explains the architecture of the proposed method. II PROPOSED METHOD The proposed method involves in the FPGA implementation of the four different frequencies for Pulse Code Modulation Multiplexing. The pulse code modulation involves the sampling, quantization and coding process. Here the four different frequencies are 500 Hz, 750 Hz, 1 KHz and 1.5 KHz are used in this work. The block diagram of the proposed work is depicted in the Fig.1. SINE WAVE INPUT 500 Hz SINE WAVE INPUT 750 Hz SINE WAVE INPUT 1 KHz MULTIPLEXER SAMPLING QUANTIZATION ENCODED PCM OUTPUT SINE WAVE INPUT 1.5 KHz SELECT LINES Fig 1. Block diagram of the proposed PCMM circuit The sine wave inputs of four frequencies are generated using the VHDL code in simulation. The sine waves are generated in bit equivalents for the 360 angles. The resolution used for the sine wave generation is 2 8 bits. The four sine waves are fed into the 4:1 multiplexer circuit which selects an output sine wave signal by assigning values to the select lines(s). Depending on the value of the select line(s), the sine wave signals are selected for PCM generation. The select value S=00, prefers the sine wave with frequency of 500Hz, S=01, prefers the sine wave with frequency of 750Hz, S=10 prefers the sine wave with frequency of 1 KHz and S=11, prefers the sine wave with frequency of 1.5 KHz. After the output is selected by the multiplexer, the sine wave is subjected to the following two techniques namely sampling and quantization. The sampling is the process of the digitizing along the x-axis. The digitizing of the time scale is manipulated with the resolution of 2 8 bit values. That is, the 256 values are assigned as equivalent for the time scale, considering 0 value as the start of time axis and 255 as the maximum time scale for one cycle. The sampled signal generated depends on the sine signal selected through the multiplexer. The next process in the PCMM is the quantization. The digitizing of the y axis is referred as quantization. The amplitude of the sampled sine wave is equated to 2 8 bit values. Again the maximum amplitude is equated to the 255 binary value and the minimum value is equated to the -255 binary value. The signed magnitude representation is used for the quantization of the sine signals. The quantized signals are represented with the binary code. The binary coded sequences are transmitted as the PCM coded signal for the selected sine wave in the form of pulses. The frequencies of pulses are unique and different depending on the sine wave selected. The Field Programmable Gate Array (FPGA) is used for the implementation of the proposed 1416

The 2 8 bit resolution is used in the VHDL code of the four sine wave signals. Fig. 3 depicts the binary coded pulses for each of the sine signals depending on the select values.

3 PCMM circuit. The Xilinx Spartan family devices say 3A DSP and 3E are used for the evaluation of the proposed PCMM. III RESULTS AND DISCUSSION The proposed PCMM design is coded with the VHDL code for the four different frequencies and the simulated output from the MODEL SIM software is shown in Fig.2. The 2 8 bit resolution is used in the VHDL code of the four sine wave signals. Fig. 3 depicts the binary coded pulses for each of the sine signals depending on the select values. The select line values are changed for all possible combinations from S=00 to11 and their corresponding Pulse Code modulated binary value are seen in the Fig.3.The proposed PCMM design is real time implemented using the Xilinx Spartan 3A DSP FPGA kit. The four frequencies namely 500 Hz, 750 Hz, 1 KHz and 1.5 KHz of the four input sine waves are plotted using the CSV plots as shown in Fig.4-7. The corresponding PCMM (pulse code) for the above four frequency sine waves are given in Figs Table 1 shows the device utilization chart of the proposed design using the Xilinx Spartan 3A DSP FPGA. The area occupancy of the proposed design is less when real time implemented using the Xilinx Spartan 3E FPGA as proven in Table 2. The power analysis is performed with the two FPGA family devices as presented in Tables 3 & 4. The power consumed by the Xilinx Spartan 3E FPGA device is as low as W. The RTL view of the proposed PCMM design is derived using the Xilinx ISE tool as depicted by the Fig.12. Fig.2 VHDL code generation of sine waves with four frequencies using the MODEL SIM software Fig.3 Simulation of pulse coded output with 2 8 bits reolution for the PCMM using MODEL SIM software. 1417

4 Fig. 4 The CSV plot for the real time 500Hz sine wave input to the FPGA Fig. 5 The CSV plot for the real time 750Hz sine wave input to the FPGA Fig. 6 CSV plot for the real time 1 KHz sine wave input to the FPGA Fig. 7 CSV plot for the real time 1.5 KHz sine wave input to the FPGA 1418

Fig. 10 CSV plot of real time PCM pulses for the sine wave with frequency 1 KHz

5 Fig. 8 CSV plot of real time PCM pulses for the sine wave with frequency 500Hz Fig. 9 CSV plot of real time PCM pulses for the sine wave with frequency 500Hz Fig. 10 CSV plot of real time PCM pulses for the sine wave with frequency 1 KHz Fig. 11 CSV plot of real time PCM pulses for the sine wave with frequency 1.5 KHz 1419

6 Table 1 Device Utilization for the PCMM using the Xilinx Spartan 3A DSP FPGA Device Utilization Summary Logic Utilization Used Available Utilization Number of Slice Flip Flops ,280 1% Number of 4 input LUTs ,280 1% Number of occupied Slices ,640 1% Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs ,280 1% Number used as logic 302 Number used as a route-thru 63 Number of bonded IOBs % Number of BUFGMUXs % Average Fanout of Non-Clock Nets 3.33 Table 2 Device Utilization for the proposed PCMM using the Xilinx Spartan 3E FPGA Device Utilization Summary Logic Utilization Used Available Utilization Number of Slice Flip Flops 102 1,920 5% Number of 4 input LUTs 305 1,920 15% Number of occupied Slices % Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs 368 1,920 19% Number used as logic 305 Number used as a route-thru 63 Number of bonded IOBs % Number of BUFGMUXs % Average Fanout of Non-Clock Nets

7 Table 3 Power Analysis for the proposed PCMM using the Xilinx Spartan 3A DSP FPGA Table 4 Power Analysis for the proposed PCMM using the Xilinx Spartan 3E FPGA Fig. 12 RTL view of the proposed PCMM design using the Xilinx ISE tool. 1421

8 IV CONCLUSION Pulse Code Modulation Multiplexing is developed using the VHDL code and implemented using the FPGA devices successfully. The parameter evaluation of area and power with respect to the Xilinx Spartan 3E FPGA implementation is found to be satisfactory. The power consumed by the proposed method using the Xilinx Spatan 3E FPGA is as low as 0.034W. Further work could be towards the design of the OFDM system. V REFERENCES [1] Yan Wang, Shoushun Chen and Amine Bermak, FPGA Implementation of Image Compression using DPCM and FBAR,IEEE Xplorer, DOI: /ISICIR [2] G.Prasad, N.Vasantha, Design And Implementation Of Pcm Decommutator On A Single FPGA, International Journal of Advanced Research in Computer and Communication Engineering Vol. 1, No 7, Sept 2012, pp: [3] Muhammad Fahad Khan, Saira Beg, Transference& Retrieval of Pulse-code modulation Audio over Short Messaging Service, International Journal of Computer Applications ( ) Volume 32 No.10, October 2011, pp: 7-9 [4] Bruno da Silva, An Braeken, Kris Steenhaut, and Abdellah Touhafi, Design Considerations When Accelerating an FPGA-Based Digital Microphone Array for Sound-Source Localization, Journal of Sensors, Hindawi, Volume 2017, pp:1-20. [5] Fatima Faydhe AL-Azawi, Zainab Faydh AL-Azawi, Rafed shaker AL- Fartosy, Design and Simulation of Pulse Code Modulation Multiplexing (PCMM) and De-Multiplexing Technique in MATLAB, International Journal of Innovative Technology and Exploring Engineering, Vol 3, No 10, March 2014, pp: 5-8. [6] Rosula S.J. Reyes, Carlos M. Oppus, Jose Claro N. Monje, Noel S. Patron, Reynaldo C. Guerrero, Jovilyn Therese B. Fajardo, FPGA Implementation of a Telecommunications Trainer System, INTERNATIONAL JOURNAL OF CIRCUITS, SYSTEMS AND SIGNAL PROCESSING, Issue 2, Volume 2, 2008, pp: [7] Iqbalur Rahman Rokon, Toufiq Rahman, Aniqua Tasnim Rahman and Humaira Mehreen, Hardware Implementation of ADPCM Encoder and Decoder Using Verilog and FPGA, International Conference on Advances in Electrical and Electronics Engineering (ICAEE'2012) Penang, Malaysia, pp: [8] Moumita Acharya, Rumpa Biswas, Design and Implementation of Frequency Modulated Transmission and Reception of Speech Signal and FPGA Based Enhancement, ACCENTS Transactions on Image Processing and Computer Vision, Vol 1,No 1 November-2015, pp:

9 1423

10 1424

FPGA Implementation of Digital Modulation Techniques BPSK and QPSK using HDL Verilog

FPGA Implementation of Digital Techniques BPSK and QPSK using HDL Verilog Neeta Tanawade P. G. Department M.B.E.S. College of Engineering, Ambajogai, India Sagun Sudhansu P. G. Department M.B.E.S. College