ABSTRACT. WANG, LI. Medium Voltage Medium Frequency Isolated DC-DC Converter Based on 15 kv SiC MOSFETs. (Under the direction of Dr. Alex Q. Huang).

Transcription

1 ABSTRACT WANG, LI. Medium Voltage Medium Frequency Isolated DC-DC Converter Based on 15 kv SiC MOSFETs. (Under the direction of Dr. Alex Q. Huang). Medium voltage (MV) medium frequency (MF) isolated DC-DC converter is essentially a device in future DC power distribution systems. It is also a key stage in a MV AC-AC solid state transformer. Newly developed 15 kv silicon carbide (SiC) power MOSFETs with fast switching capability enable the reduction of size, weight, and complexity of MV MF power converters. In MV and MF applications, zero voltage switching (ZVS) is necessary since a significant amount of energy is stored in MOSFETs parasitic output capacitors. Recovering this energy is vital to secure the system conversion efficiency and reliability. In order to achieve an optimized ZVS converter design, it is crucial to accurately characterize the nonlinear output charge (or output capacitance) of power semiconductor devices. A dynamic half-bridge MOSFET output charge measurement method is thoroughly analyzed and experimentally verified up to 6 kv using 15 kv SiC MOSFETs. Output capacitance model is then derived using the measured results. The test circuit not only reflects the realistic ZVS scenario but also achieves a high accuracy (<1% error) without resorting to special equipment or complex configurations which are usually necessary for high voltage capacitance measurement. To secure complete soft switching, a straightforward and effective state-trajectory ZVS analysis method is introduced. It addresses three ZVS related concerns including complete ZVS criteria, duration of the soft-switching interval, and ZVS time window. MOSFET s charge equivalent output capacitor is mathematically identified to conduct the simple constant capacitance statetrajectory ZVS analysis. Take the nonlinearity of the MOSFET s output capacitor into account, a voltage dependent variable capacitance state-trajectory ZVS analysis is also carried out.

2 Comparison of both methods shows that the simplified charge equivalent constant capacitance state-trajectory ZVS analysis has good ZVS transition estimation. Based on the 15 kv SiC MOSFETs, a novel isolated DC-DC converter for medium voltage applications is proposed to combine advantages of the resonant converters and dual active bridge (DAB) converters. In normal load scenario, this converter operates in pure resonant mode with a switching frequency equals to the resonant frequency of the series resonant tank. Thus, zero voltage turn on at primary side and zero current turn off at secondary side are secured from zero to full load. When over-load happens, the resonant capacitors will be bypassed by their paralleled diodes. The proposed converter will automatically switch to resonant and DAB mixed operation mode, therefore resonant current limiting is naturedly achieved. An optimized converter design using 15 kv SiC MOSFET modules to operate between 6 kv and 12 kv is obtained and an experimental prototype operating at 6 kv, 40 khz is tested with a peak efficiency exceeding 98%. To further limit resonant current during overload protection and soft-start up, an advanced variable frequency variable duty cycle control that can realize cycle-by-cycle resonant current limiting and full ZVS at any load condition is proposed. By sensing the output voltage, a digital controller with an off-line lookup table can be easily implemented. Full ZVS together with fast current limiting greatly improves the reliability of MV MF DC-DC converters. This research work also comprehensively investigates the efficiency, power density and overall cost of input series output parallel (ISOP) 12 kv, 20 kw all SiC isolated DC-DC converters. The medium voltage capability can be achieved by using either high voltage devices or multiple low voltage cells in series. The voltage ratings of semiconductor devices, magnetic components, capacitors vary with the number of cells in series. In order to investigate

3 the optimized number of cells, precise components models with different voltage ratings are required, especially for the already complicated semiconductor devices. SiC MOSFETs onresistance, output capacitance and cost models with arbitrary blocking voltages are derived based on physical device scaling laws. Using these mathematical MOSFET models together with transformer and capacitor models, multi-objective optimization of an ISOP DC-DC converter system is conducted. Optimization results show that a higher power density can be achieved by a greater number of cells but single cell converters using ultra high blocking voltage SiC MOSFETs can reach higher efficiency and lower cost.

4 Copyright 2017 Li Wang All Rights Reserve

5 Medium Voltage Medium Frequency Isolated DC-DC Converter Based on 15 kv SiC MOSFETs by Li Wang A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Electrical Engineering Raleigh, North Carolina 2017 APPROVED BY: Dr. Alex Q. Huang Committee Chair Dr. Wensong Yu Dr. Xiangwu Zhang Dr. Iqbal Husain

6 DEDICATION To My Parents, Weizhi Wang and Yinrong Lin. ii

7 BIOGRAPHY Li Wang was born in Guangxi, China. She received her B.S. degree in Electrical Engineering at Zhejiang University, Hangzhou, China, in July, She received her M.S. degree in Electrical Engineering at Zhejiang University, Hangzhou, China, in March, She is currently working towards her Ph.D. degree in the Department of Electrical and Computer Engineering at North Carolina State University. She received research scholarship as a parttime Research Assistant at the Future Renewable Electric Energy Delivery and Management Systems (FREEDM) center at North Carolina State University in the fall of 2012 and has been working there ever since. Her research interests include all SiC medium voltage medium frequency solid state transformer, resonant converter with advanced control, and magnetics design. iii

8 ACKNOWLEDGMENTS First and foremost, I would like to show my deepest gratitude to my Ph.D. advisor, Dr. Alex Q. Huang for his guidance, encouragement and support throughout this work and my studies here at FREEDM systems center, NC state university. I would like to give special recognition to his vast knowledge, profound insight, consistent passion for new technology and great personalities. These all have and will continue benefit me in my future career. I would also like to express my gratitude to Dr. Wensong Yu for his unwavering guidance and support; to Dr. Iqbal Husain and Dr. Xiangwu Zhang, for serving on my committee. I am deeply thankful to the SST(Solid State Transformer) team members including Dr. Gangyao Wang, Dr. Xu She, Mr. Fei Wang, Mr. Qianlai Zhu, Mr.Yang Lei, Mrs. Kristen Booth, Dr. Dong Chen, Mr. Zhiping Chen, Mr. Liqi Zhang, Dr. Sheng Zong, Ms. Lan Ma, Dr. Linjun Zheng, Dr. Xijun Ni, Mr. Soumik Sen and many others who have been worked on the SST projects. The help from faculties and staffs in the FREEDM system center are appreciated. I would especially thank Dr. Pam Carpenter, Ms. Karen Autry, Mr. Ken Dulaney, Mr. Rogelio Sullivan, Ms. Colleen Reid and many more without whom I would not have been able to accomplish all that I have done during my stay here. I also appreciate the help from my friends in FREEDM Systems Center, for their help and support both in life and research. I'd like to thank Dr. Ruiyang Yu, Dr. Xiaomin Li, Mr. Yifan Jiang, Mr. Yizhe Xu, Dr. Yenmo (Morris) Chen, Ms. Huan Hu, Dr. Mengqi Wang, Mr. Kai Tan, Mr. Xiaoqing Song, Mr. Fei Xue, Dr. Chang Peng, Mr. Yang Xu, Dr. Xunwei Yu, Dr. iv

9 Xing Huang, Dr. Jianhua Zhang, Ms. Xiangqi Zhu, Ms. Liao Mang, Mr. Nan Xue, Mr, Ms. Yuling Zhao, Ms. Lisa Sun, Ms. Yue Shi, Mr. Haotao Ke, Mr. Sizhen Wang, Mr. Qingyun Huang, and many other that I cannot list the name here. I give my special thanks to Prof. Dr. Johann Walter Kolar for hosting my academic visiting to Power Electronic Systems Laboratory at ETH Zurich from Sep Dec, I also appreciate the help from Dr. Jonas Huber, Ms. Monica Kohn-Müller and all the other Colleagues at PES. My heartfelt gratitude goes to my parents for their everlasting love and support, for raising me up in a happy family with a wonderful childhood. Thanks, my sister for supporting me during the past years. Many thanks to my boyfriend Fang Chen for his constant support and encouragement during this intense phase of my life. v

10 TABLE OF CONTENTS Chapter 1. Introduction Solid State Transformer Application Medium Voltage DC System Application MV MF Isolated DC-DC Converters Thesis Outline Chapter 2. Study of Dynamic High Voltage Output Charge Measurement for 15 kv SiC MOSFET Introduction Review of High Voltage Capacitance Measurement Techniques Output Charge (Output Capacitance) Measurement Measurement Principle Measurement System Consideration Error Analysis and Certification Measurement Results and Output Capacitance Model Derivation Conclusion Chapter 3. A New Zero Voltage Switching Analysis Method of Power MOSFET Based on State-Trajectory Introduction vi

11 3.2 State-Trajectory for Zero-Voltage Switching Analysis Nonlinear Behavior of the Parasitic Output Capacitance Conclusion Chapter 4. A Medium Voltage Medium Frequency Isolated DC-DC Converter Based on 15 kv SiC MOSFETs Introduction Operation Principle Normal Load Operation Over-load Operation Power Stage Design Considerations Magnetizing Inductance and Dead Time Design to Best Utilize the 15 kv SiC MOSFET Module Resonant Tank Design Experimental Results Conclusion Chapter 5. Over-Load Protection and Soft-Start of the Proposed Medium-Voltage Medium- Frequency Isolated DC-DC Converter Introduction vii

12 5.2 Constant Frequency Variable Duty Cycle (CFVD) Control for Over-Load Protection and Soft-Start Variable Duty Cycle for Current Limiting Experimental Results using CFVD Control Incomplete-ZVS Using CFVD Control Variable Frequency Variable Duty Cycle (VFVD) Start-up Variable On-time for Current Limiting Variable Off-time for ZVS ZVS Considerations ZVS process at stage S1 and S ZVS process at stage S ZVS process at stage S VFVD Control Implementation Experimental Verification Conclusion Chapter 6. Multi-Objective Optimization of Medium Voltage SiC DC-DC Converter Based on Modular Input-Series-Output-Parallel (ISOP) Architecture Introduction System Specifications viii

13 6.3 MOSFET Models Conduction Resistance Model Output Capacitance Model Cost Model Circuit and Other Components Models Circuit Model Transformer Model Capacitor Model Cooling System and Other Components System Optimization Conclusion Chapter 7. Conclusions and Future Work Conclusions Future Work REFERENCES ix

14 LIST OF TABLES Table 2-1 Curve fitted SiC MOSFET parameters Table 4-1 MV DC-DC Prototype Design Specifications Table 4-2 MV DC-DC Prototype Components and Specifications Table 5-1 Peak Current Calculation Specifications Table 5-2 Series Resonant Converter Specifications Table 6-1 System Optimization Specifications ii

15 LIST OF FIGURES Fig. 1-1 SST enabled hybrid DC/AC microgrid system [5] Fig. 1-2 Three-stage SST structure Fig. 1-3 Two-stage SST structure Fig. 1-4 Single-stage SST structure Fig. 1-5 Future medium voltage DC grid system [10]... 6 Fig. 1-6 Neutral point clamping (NPC) half-bridge DC-DC converter [3] Fig. 1-7 Modular multilevel DC-DC converter proposed by [22] Fig kv 1 kv, 1 MW resonant isolated DC-DC converter for MVDC ship power networks [25] Fig kv SiC MOSFET and JBS module developed by Cree, packaged by Powerex [29] Fig SiC MOSFET Capacitive Switching Loss [29] Fig kv 400 V, 10 kw dual active bridge (DAB) isolated DC-DC converter for FREEDM Gen II MV SST [29] Fig kv AC 120 V AC, 10 kva Gen II SST of FREEDM [29] Fig kv 1.5 kv, 150 kw LLC resonant DC-DC converter for power electronic traction transformer (PETT) [32] Fig ABB s PETT prototype (1.2-MVA) for the 15-kV 16.7-Hz railway grid [32] Fig. 2-1 (a) Cross section of a MOSFET cell. (b) Equivalent capacitances between terminals of MOSFET. [38] iii

16 Fig. 2-2 Overview of high voltage capacitance measurement techniques in power electronics Fig. 2-3 Half-bridge output charge measurement system Fig. 2-4 Key waveforms of the half-bridge out-put charge measurement system Fig. 2-5 Equivalent circuit of half-bridge out-put charge measurement system: t0 t Fig. 2-6 Equivalent circuit of half-bridge out-put charge measurement system: t1 t Fig. 2-7 Equivalent circuit of half-bridge out-put charge measurement system: t4 t Fig. 2-8 Error caused by non-floated gate driver power supply Fig. 2-9 Error caused by voltage monitor Fig Recommended voltage monitor circuit for the half-bridge output charge measurement Fig Measured output charge of 1.2 kv SiC MOSFET using different gate resistor and switching frequency Fig Error verification using certification caps Fig Waveforms of half-bridge testbed using -5V turn-off gate to source voltage Fig Half-bridge out-put charge measurement system using negative turn-off gate to source voltage: (a) equivalent circuit of t0-t1; (b) simplified equivalent circuit of t0-t1, Fig High voltage output charge measurement setup Fig Half-bridge out-put charge measurement experimental waveforms of 15 kv SiC module (MOSFET and JBS paralleled) under 6 kv Fig Experimental output charge measurement results of 15kV SiC Module (MOSFETJBS) iv

17 Fig Measured parasitic capacitance of isolated differential voltage probe Fig Output charge curve fitting of 1.2 kv 100 A SiC MOSFET module (CAS100H12AM1) Fig Output capacitance for 1.2 kv 100 A SiC MOSFET module (CAS100H12AM1) Fig Output charge curve fitting of 15 kv SiC module (MOSFET and JBS paralleled) Fig Output capacitance model for 15 kv SiC module (MOSFET and JBS paralleled) Fig. 3-1 ZVS resonant tank and converter resonant tank Fig. 3-2 Equivalent circuit of series resonant converter s ZVS switching interval Fig. 3-3 Simplified equivalent circuit of series resonant converter s ZVS switching interval Fig. 3-4 (a) Half-bridge DAB converter. (b) Equivalent circuit of half-bridge DAB converter during soft-switching Fig. 3-5 (a) Full-bridge DAB converter. (b) Equivalent circuit of full-bridge DAB converter during soft-switching Fig. 3-6 (a) Synchronous Boost converter. (b) Equivalent circuit of synchronous Boost converter during soft-switching Fig. 3-7 (a) Synchronous Buck converter. (b) Equivalent circuit of synchronous Buck converter during soft-switching v

18 Fig. 3-8 Synchronous Buck converter - Q2 s ZVS switching interval: (a) Time-domain waveforms; (b) State-trajectories Fig. 3-9 Synchronous Buck converter state-trajectories of Q1 s ZVS switching interval. 50 Fig Voltage dependent output capacitance of MOSFET Fig Voltage dependent variable capacitance ZVS state-trajectories Fig variable capacitance ZVS state-trajectories and charge equivalent constant capacitance ZVS state-trajectories Fig variable capacitance and charge equivalent constant capacitance ZVS time-domain waveforms Fig Error of ZVS transition duration - TZVS between charge equivalent constant capacitance based and voltage-dependent variable capacitance based state-trajectory analysis Fig Error of inductor s remaining current at the end of ZVS - IL_rem between charge equivalent constant capacitance based and voltage-dependent variable capacitance based statetrajectory analysis, color mapped by inductor s initial current IL_ Fig Error of inductor s remaining current between charge equivalent constant capacitance based and voltage-dependent variable capacitance based state-trajectory analysis, color mapped by IL_rem Fig ZVS measurement circuit Fig ZVS measurement setup Fig ZVS measurement waveforms vi

19 Fig Discrepancy between measured and charge equivalent constant capacitance statetrajectory calculated ZVS duration - TZVS Fig Discrepancy between measured and charge equivalent constant capacitance statetrajectory calculated ZVS remaining current IL_rem Fig Measured and charge equivalent constant capacitance state-trajectory calculated ZVS remaining current IL_rem Fig. 4-1 Proposed novel resonant and DAB hybrid DC-DC converter Fig. 4-2 Equivalent circuit of the proposed converter under normal load operation Fig. 4-3 Steady-state trajectory under normal load condition Fig. 4-4 Operation modes and equivalent circuits under over-load operation Fig. 4-5 Steady-state waveforms under over load operation (VLV<VMV/2n) Fig. 4-6 Steady-state trajectory under over-load operation Fig. 4-7 Measured and modeled output charge of the 15 kv SiC MOSFET module Fig. 4-8 Measured and modeled conduction resistance of the 15 kv SiC MOSFET module Fig kv SiC MOSFET module power loss and junction temperature calculation flow chart Fig Minimum 15 kv SiC MOSFET junction temperature versus processed power with different switching frequency and VMV Fig Experimental waveforms, VMV = 6 kv, Po = 10 kw Fig Experimental waveforms, VMV = 6 kv, Po = 0 W Fig Measured prototype efficiency, VMV = 6 kv, Po from 2 to 12 kw; vii

20 Fig Converter loss break down, VMV = 6 kv, Po = 10 kw Fig. 5-1 Current limiting strategies for resonant converters during start-up or over-load operation Fig. 5-2 Proposed constant frequency variable duty cycle (CFVD) control for resonant current limiting Fig. 5-3 Peak resonant current versus duty-cycle and VLV (VMV = 6 kv) Fig. 5-4 VLV versus peak resonant current (VMV = 3 kv) Fig. 5-5 Experimental short circuit protection waveforms, VMV = 3 kv Fig. 5-6 Experimental short circuit protection waveforms, VMV = 3 kv, VLV = 0 V Fig. 5-7 Key waveforms of the proposed DC-DC converter during startup process Fig. 5-8 Operation modes and equivalent circuits during switching intervals using CFVD control Fig. 5-9 Predictive variable frequency variable duty cycle (VFVD) control Fig Four stages of the soft-start process Fig Stage S1 - resonant tank state-trajectory Fig Stage S2 - resonant tank state-trajectory Fig Stage S3 - resonant tank state-trajectory Fig Stage S4 - resonant tank state-trajectory Fig Equivalent circuits for the turn-on period of Q Fig Equivalent circuits for the turn-off period of Q Fig Operation modes and equivalent circuits during ZVS process Fig Stage S1 - ZVS state-trajectories viii

21 Fig Stage S2 - ZVS state-trajectories Fig Stage S3 - ZVS state-trajectories, VM1>VMV/ Fig Stage S3 - ZVS state-trajectories, VM1<VMV/ Fig Stage S4 - ZVS state-trajectories Fig On-time, off-time and half of switching period versus VLV/VLV_R (normalized VLV) using VFVD control Fig Switching frequency versus VLV/VLV_R (normalized VLV ) using VFVD control Fig Duty cycle versus VLV/VLV_R (normalized VLV ) using VFVD control Fig Implementation flow chart of VFVD soft-start Fig Starting up experimental waveforms using VFVD control Fig Zoomed in startup experimental waveforms using VFVD control at stage S Fig Zoomed in startup experimental waveforms using VFVD control at stage S Fig Zoomed in startup experimental waveforms using VFVD control at stage S Fig Zoomed in startup experimental waveforms using VFVD control at stage S Fig. 6-1 Input series output parallel (ISOP) medium voltage series resonant DC-DC Converter Fig. 6-2 Specific on resistance model for SiC MOSFETs and specific on resistance of Wolfspeed Gen 3 SiC MOSFETs from k V Fig. 6-3 Active chip area and over all chip area considering edge termination Fig. 6-4 Output capacitance model for SiC MOSFETs and output capacitance of Wolfspeed 1.7 kv (CPM B), 15 kv SiC MOSFETs ix

22 Fig. 6-5 SiC MOSFET s cost versus active chip area with different voltage level Fig. 6-6 Film capacitors volume versus capacitance with different voltage level Fig. 6-7 Flow chart of ISOP series resonant DC-DC converter design using proposed SiC MOSFET models Fig. 6-8 Optimization results system efficiency versus power density Fig. 6-9 Optimization results system cost versus power density Fig Optimization results system efficiency versus cost x

23 Chapter 1. Introduction 1.1 Solid State Transformer Application Distribution transformer is a crucial device in traditional distribution alternating current (AC) grid system [1]. It provides medium voltage (MV) AC to low voltage (LV) AC transformation at the user end for industrial, commercial, and residential use. It also plays a critical role in renewable energy resources integration systems by interfacing between different voltage levels [2]. In [3], the product of core cross-section area and winding window area of a transformer had been derived as: A core A winding 2 PT (1.1) f k J B winding rms,max max Where, P T is the power rating of the transformer; f is the operation frequency; k winding is the winding window filling factor; J rms,max is the maximum current density and B max is the maximum flux density. Obviously, transformer s area product inversely proportional to its operation frequency. Pushing the operation frequency to a higher level would result in a reduction of the transformer volume and weight. Targeting at replacing the traditional line frequency (50/60Hz) transformer (LFT), solid state transformer (SST) was proposed in 1968 by William McMurry [4]. Using semiconductor devices, medium-frequency (MF) to high-frequency transformation is achieved, and hence, the volume and weight of the magnetic component can be reduced. 1

24 Because of the greatly improved operation frequency ( > 10 khz ), SST has great potential of having higher power density compared with the LFT. Driven by the needs to create a more resilient power grid suitable for integrating high penetration of distributed energy resources (DERs), SST has been regarded as one of the 10 most emerging technologies by Massachusetts Institute of Technology (MIT) Technology Review in 2010 [2]. In addition to interface different voltage levels and provide galvanic isolation, smart features of the SST such as advanced power management, energy management and fault isolation are of great interests [5][6][7]. As presented in Fig. 1-1, with direct current (DC) output capability, SST functioning as an energy router, interfaces DC and AC in future micro-grids systems. SST technology is also being adopted in the area of railway applications known as power electronic traction transformer (PETT). It replaces the 15 kv, 16 2 Hz transformer and realized a more than 50% 3 weight reduction [8]. Three SST architectures are presented in Fig. 1-2, Fig. 1-3 and Fig. 1-4 [5]. Due to the least number of stage, single-stage SST achieves the most efficient AC-AC transformation. Because of the least number of MV MF semiconductor devices being used, it is also the most cost effective solution. However, it sacrifices some of the smart features of the original SST concept such as no constant 400 V DC port that can directly connect to DC grid systems; hard to realize power factor control etc. 2

25 Distribution grid Fault Isolation device SST 120V ac bus 400V dc bus Storage EV charger PV Fig. 1-1 SST enabled hybrid DC/AC microgrid system [5]. Distribution grid MVDC Link capacitor LVDC Link capacitor Vg AC/DC Isolated ZVS DC/DC Converter DC/AC LV ac feeder Medium voltage Low voltage Fig. 1-2 Three-stage SST structure. 3

26 Distribution grid DC Link bus capacitor Vg Isolated ZVS AC/DC Converter DC/AC LV ac feeder Medium voltage Low voltage Fig. 1-3 Two-stage SST structure. Distribution grid Vg Isolated ZVS AC/AC Converter LV ac feeder Medium voltage Low voltage Fig. 1-4 Single-stage SST structure. Among all the above-mentioned SST solutions, three-stage SST is the most promising one that can fulfill all the above mentioned smart transformer features. The MV and LV DC buses enable not only the directly tied of renewable energy plants but the capability of reactive power regulation as well. To achieve high efficient power conversion such that it is comparable to traditional line frequency distribution transformers, whose overall efficiency is required to be 4

27 above 97% and have approached to 99.5% [2]. MV MF isolated DC-DC converter as a key stage in the three-stage SST, its conversion efficiency is crucial to the overall system power efficiency. In addition, it needs to step down the MV DC to LV DC and provides system galvanic insulation. Its operation frequency directly related to the MF transformer s size. 1.2 Medium Voltage DC System Application AC has been dominated the power transmission systems globally over the past hundred years. With the increasing demand for electricity, the limitations of AC transmission listed below become significant: 1) due to the reactive power flow induced by the large cable capacitance, AC transmission has limit capacity and distance; 2) unable to exchange energy between two AC networks of different frequencies; 3) difficult to combine renewable energy into the grid [9]. High Voltage Direct Current (HVDC) has been proved of having bulk electricity transport capability over long distances. Due to the lower losses, compared with AC systems, HVDC systems can transmit up to 3 times more power [9]. Smaller cable size and simpler cable structure make it more economical a solution for long distance power transmission. This enables the utilization of renewable energy like wind, solar and hydro whose generations are normally located far away from the user end. Besides, as shown in Fig. 1-5[10], a future DC grid system [11] [12][13][14] is versatile and flexible for effectively integrating renewable energy plants and energy storage devices. MV DC system is also a key enabling technology of all-electric shipboard power systems [15][16]. In the DC network, there are DC buses at different voltage levels [13][14] [17][18][19][20][21]. Therefore, DC-DC converters are 5

28 essential devices in the DC distribution system, as highlighted in Fig They re regarded as DC transformers that interface between HV, MV and LV grids. Taking advantages of advanced semiconductor power devices, MF DC transformers can achieve lower volume and weight compared with conventional 50/60 Hz AC distribution transformers in AC network. Existing AC Infrastructure AC Transmission Supply Fuel Cells Photovoltaic Generation Non-Synchronous Generation (Wind) Future HVDC Intertie HVDC System MVDC Distribution DC Load Circuits Future DC Industrial Facility Future DC Data Centers Variable Frequency Drives Electric Vehicle Distribution Level Storage Sensitive Load Electronic and AC Loads Control Algorithm Fig. 1-5 Future medium voltage DC grid system [10]. 6

29 1.3 MV MF Isolated DC-DC Converters As discussed before, MV isolated DC-DC converter not only plays a crucial role in future MV DC grid but also is a key stage in SST system. The following basic features are required by the above-mentioned applications: 1) MV MF capability. In order to connect to the MV DC grid or the MV DC bus of SST, the DC-DC converter has to be able to deal with MV level. MF switching is a key point of reducing the converter s volume and weight. The combination of MV and MF bring in grant challenges to the system design, because of the limit voltage blocking capability of commercial available power semiconductor devices. 2) Galvanic isolation. A MV MF transformer is required to provide LV to MV galvanic isolation for safety reason. 3) High voltage ratio. The voltage ratio of MV to LV level is normally very high. It can be either realized by using transformer with high turns ratio or by breaking down the voltage ratio into lower ones using input-series-output-parallel (ISOP) structure. 4) High efficiency and reliability. The DC-DC conversion efficiency and reliability are critical to the overall system performance. Low voltage isolated DC-DC converters connected in an ISOP configuration is a very popular approach to achieve the MV level. This approach has downsides including knotty MF transformers design and weak fault tolerance capability [22]. To realize overall system MV to LV galvanic insulation, the MF transformers in each LV DC-DC converter have to achieve the 7

30 same MV insulation level, resulting in low winding factor and large leakage inductance [22]. System design redundancy are required to improve the operation reliability. To support the medium voltage, multilevel arrangements are favored at the MV side[23]. Fig. 1-6 presents a neutral point clamped multi-level converter from PES ETH. Input voltage level is limited to twice of the IGBTs operating voltage in the circuit. It is therefore necessary to have several modules in Fig. 1-6 series-connected to achieve higher input voltage level. Fig. 1-6 Neutral point clamping (NPC) half-bridge DC-DC converter [3]. As shown by Fig. 1-7, modular multilevel DC-DC converters are proposed in [22] to deal with the MV. Due to the discrepancies between devices, capacitors and gating signals etc., capacitor voltage balancing algorithm is vital to avoid the system failure. 8

31 Fig. 1-7 Modular multilevel DC-DC converter proposed by [22]. A series string of several devices is able to support higher voltage than any single device could do alone. The key challenges in a series connection of devices are the static and dynamic sharing of the voltage across the devices. Snubber capacitors are connected across each device to clamp the voltage in a safe operating area [24]. A MV MF DC-DC converter was presented in [25] for MVDC ship power networks, in which, six 1.7 kv IGBTs are series connected to handle the 5 kv MV bus as shown by Fig

32 2C r*(n s/n p) 2 L r/2*(n p/n s) 2 Lr/2 2C r 5 kv L m 1 kv N p N s 1MW,5kHz,5kV:1kV transformer with 15kV dc insulation Fig kv 1 kv, 1 MW resonant isolated DC-DC converter for MVDC ship power networks [25]. In recently years, the fast development of wide bandgap devices provides an opportunity to use two-level converters to handle the MV power conversion, which are usually more reliable and efficient. e.g. 15 kv silicon carbide (SiC) power MOSFETs (shown in Fig. 1-9) with high voltage capability and fast switching speed is promising in reducing the size, weight, and complexity of medium and high voltage converters [26], [27]. However, a considerable amount of energy stored in the parasitic output capacitance leads to high capacitive switching losses as given in Fig Although the switching loss is much lower than the Si IGBT s switching loss with similar voltage level, it become significant when operating the device at MF, and hence, limit the SiC MOSFET s switching frequency at lower than 10 khz [28]. 10

33 Fig kv SiC MOSFET and JBS module developed by Cree, packaged by Powerex [29]. Fig SiC MOSFET Capacitive Switching Loss [29]. Switching frequency of the DC-DC converter is critical to determine the size of the MF transformer. To improve the switching frequency to a higher level without resorting to a bulky cooling system, zero-voltage switching (ZVS) is required. With ZVS, the switching losses are greatly improved compared with hard switching. In addition, ZVS reduces the dv/dt during the 11

34 switching transient. This ensures: 1) low EMI noise and reduces the probability of any false trigger at the gate of MV devices; 2) lower the dielectric losses, which might cause premature aging of the insulation materials of the MF transformer and of the semiconductor devices substrate [30]. In a word, ZVS of MV MF DC-DC converter using ultra high blocking voltage SiC MOSFETs is vital for both overall conversion efficiency and reliability. Dual active bridge (DAB) is a classical solution for MV isolated DC-DC converter with ZVS capability. It has simple and symmetrical structure; easy to start up and protect. With the 15 kv SiC MOSFETs, a 6 kv 400 V, 10 kw DAB DC-DC converter (Fig. 1-11) running at 20 khz was built for Gen II SST of FREEDM as shown in Fig However, it may lose ZVS on light load occasion and its high turn-off current results in high reverse energy that deteriorates the overall efficiency [31][5]. P 1 C h1 n:1 S 1 S 3 C h2 P 2 v p L f 6 kv 400V 20 khz 10 kw v s S 2 S 4 C o Fig kv 400 V, 10 kw dual active bridge (DAB) isolated DC-DC converter for FREEDM Gen II MV SST [29]. 12

35 Fig kv AC 120 V AC, 10 kva Gen II SST of FREEDM [29]. Resonant converters are attractive options for MV isolated DC-DC converter. Fig presents a LLC resonant DC-DC converter for the power electronics traction transformer developed by ABB (as shown in Fig ) using 6.5 kv Si IGBTs [32]. It can achieve ZVS from zero to full load. The turn-off current is much lower compared with the DAB converter. However, it is very complex to start-up or conducts over-load protection to a resonant converter [33]. A MV isolated resonant DC-DC converter is proposed in [34]. It combines the advantages of both DAB and resonant converter including: 1) intrinsic current limiting capability for soft start-up and overload protection; 2) ZVS from zero to full load range; 3) low turn-off current. These features make it a more efficiency and reliable alternative to DAB and LLC resonant converters. 13

36 C r L r 3.6 kv L m 1.5kV - 2.2kHz 150kW Fig kv 1.5 kv, 150 kw LLC resonant DC-DC converter for power electronic traction transformer (PETT) [32]. Fig ABB s PETT prototype (1.2-MVA) for the 15-kV 16.7-Hz railway grid [32]. 14

37 1.4 Thesis Outline This dissertation focuses on proposing high efficiency and reliable solution for MV MF isolated DC-DC converter based on lately developed 15 kv SiC MOSFET. It has been organized as follows: In chapter 2 : A dynamic half-bridge output charge measurement method for 15 kv SiC MOSFET s is discussed. Characterizing MOSFET s voltage dependent parasitic output capacitor is critical to ZVS converter design but is of grand challenges especially for high voltage devices. No commercial equipment is ready for measuring capacitance with greater than 40 V DC bias. A high voltage output charge measurement setup is shown in chapter 2. Without resorting to complex networks or special equipment, it can provide measurement results up to 6 kv with < 1% error. Applying least square curve fitting to measured output charge results, output capacitance model for 15 kv SiC MOSFET module can be obtained. The setup can also test other voltage dependent capacitors. In chapter 3: A straightforward and effective state-trajectory ZVS analysis method is proposed. It can be universally adopted by converters with ZVS capabilities including synchronous Buck converter, synchronous Boost converters, half-bridge converters, full bridge converters etc. Nonlinearity of the MOSFET s output capacitor is considered and charge equivalent output capacitor is identified for the state-trajectory analysis. Analyzing results provide complete and reliable guidance for ZVS converter design. In chapter 4: An isolated DC-DC converter combining resonant converter and DAB is proposed to provide a robust and rugged MV MF DC-DC transformation. The proposed 15

38 converter operates like a conventional series resonant converter for a normal load operation. When over-load happens, split resonant capacitors will be shorted by paralleled LV diodes across them. The impedance of the resonant tank is naturally increased, and hence cycle-bycycle over-load protection can be realized. Hardware design considerations are given. With well-characterized output capacitance and on resistance, converter optimization was conducted to best utilize the MV devices. Based on the optimized designs, a half-bridge 15 kv SiC MOSFETs is shown to have a capability of delivering greater than 30 kw power using the proposed converter. In chapter 5: Two start-up methods: constant frequency variable duty cycle (CFVD), variable frequency variable duty cycle (VFVD) are studied. Both can realize soft-start and cycle-by-cycle over-load protection to the converter. Based on the state-trajectory ZVS analysis method given in chapter 3, advanced VFVD control scheme that can secure full ZVS of the MV devices at any operation point is fulfilled, which further improved the reliability of the system. In chapter 6: A comprehensive comparison of a single-cell DC-DC converter using ultra high voltage SiC MOSFETs versus multi-cells using low voltage SiC MOSFETs is conducted. The medium voltage capability can be achieved by using either high voltage devices or multiple low voltage cells in series. Voltage rating of semiconductor devices, magnetic components, capacitors vary with the number of cells in series. In order to investigate the optimized number of cells, components models with different voltage ratings are derived including SiC MOSFET s on-resistance, output capacitance, and cost models. Using these mathematical MOSFET models together with transformer and capacitor models, multi- 16

39 objective optimization of an ISOP DC-DC converter system is realized. Optimization results show that a higher power density can be achieved by a greater number of cells but single stage converter can reach higher efficiency and lower overall system cost. In chapter 7: Future works and conclusion are discussed. 17

40 Chapter 2. Study of Dynamic High Voltage Output Charge Measurement for 15 kv SiC MOSFET 2.1 Introduction With very high voltage capability and fast switching speed, 15 kv/10a silicon carbide (SiC) power MOSFETs provide the capability to significantly reduce the size, weight and complexity of medium and high voltage converters [26], [27]. However, turn-on losses of 15 kv/10a SiC MOSFET is still too high when it operates at >10 khz, as a significant amount of energy stored in the parasitic output capacitance is discharged during each turn-on event [35][28]. Zero voltage turn on is therefore extremely useful to eliminate these losses and increase the switching frequency. Dual active bridge (DAB) and series resonant converters are good candidates for medium voltage DC-DC applications [28], [36] and have recently been demonstrated by the authors in a 40 khz medium voltage DC-DC converter. The load current during the switching interval is oriented from source to drain, which discharges the MOSFET s output capacitor, thereby eliminating turn-on losses. Output charge of a MOSFET becomes important in the aim of converter optimization [37]. Besides output charge, output capacitance is also frequently used in MOSFET s model for better circuit analysis, but they are fundamentally from the same physical mechanism. Fig. 2-1(a) shows the cross-section of half a cell in a MOSFET chip. The capacitance arising from the depletion layer changes with the applied voltage across it. Equivalent output capacitance Cgd Cds as shown in Fig. 2-1(b) is 18

41 highly voltage dependent. So is the corresponding output charge. Finite-element device simulation can help characterize those capacitances. But it requires detailed device structure, dimension and process parameters [38]. Conventional LCR meter or impedance analyzer usually can only generate 40 V bias which is much below the device rated voltage[29]. Therefore, an easy and accurate method to measure the output charge and capacitance of high voltage MOSFET is necessary. Here, a review of high voltage capacitance measurement techniques is given. A half-bridge output charge measurement method is thoroughly analyzed. Detailed high voltage system configuration and considerations to reach high measurement accuracy are discussed. Experimental tests are carried out for 15 kv SiC MOSFET up to 6 kv. Measurement certification confirms an error of <1% can be reached at high voltage level. Based on the test output charge, derived output capacitance model well fitted to the datasheet. Source (S) C m Gate (G) D n P Depletion region n- Epitaxial layer n Drain (D) C oxs C oxc C oxd C c C gdj C dsj G C gd C gs S C ds (a) (b) Fig. 2-1 (a) Cross section of a MOSFET cell. (b) Equivalent capacitances between terminals of MOSFET. [38] 19

42 High Voltage Capacitances Measurement Techniques in Power Electronics Frequency Domain Impedance Analyser or LCR Meter Based Multiple-Current-Probe (MCP) Capacitance versus Voltage Static Time Domain Time-Domain Reflectometry (TDR) Dynamic Double-Pulse Tester Based Dynamic, Charge Equivalent Double-Pulse Tester Based Full-Bridge Half-Bridge Fig. 2-2 Overview of high voltage capacitance measurement techniques in power electronics. 2.2 Review of High Voltage Capacitance Measurement Techniques As shown in Fig. 2-2, high voltage capacitance measurement techniques can be divided into two groups: capacitance versus voltage measurement and charge equivalent measurement. Capacitance versus voltage measurement provides the capacitance of device under test (DUT) at a certain voltage. While charge equivalent measurement gives equivalent capacitance based on the DUT s accumulated charge at a certain voltage. For the static methods, a DC bias voltage is first applied to the DUT, then a small signal is injected into the test circuit. In [38][29], the device characteristics capacitance is indirectly measured with the impedance analyzer or LCR meter. Passive components are used to isolate the applied high DC voltages from the impedance or LCR meter. Carefully design of those passive components with consideration of the DUT s characteristics at the measurement frequency is needed not only to avoid the hazard to the measurement apparatus and the user if there is a failure but also to 20

43 ensure the accuracy of the measurement[29]. [39][40] discussed a multiple-current-probe measurement method. By using one current injection probe and two current receiving probe, the network analyzer can measure the impedance of the test setup. Then the capacitance of DUT can be derived based on the tested impedance. Current probes enable an easier way to reach high voltage isolation compared with the impedance analyzer or LCR meter based methods. But all these aforementioned methods can only measure capacitance at a fixed frequency at one time, which is not sufficient for analysis and exact modeling [41]. A timedomain reflectometry method using an oscilloscope together with a 50Ω coaxial cable to measure the reflected signals of the measurement circuit is proposed by [41]. Extra fast rising time and stable pulse generator are needed. The accuracy of test results depends on the rising time of the pulse, bandwidth, and waveform acquisition time of the oscilloscope. In [42], a dynamic measurement method is proposed for directly obtain the realistic values of the parasitic capacitances from corresponding voltage and current waveforms. But even small phase discrepancy between the voltage and current waveform will lead to great error. According to[29], double pulse tester can measure the charge in the equivalent output capacitance of the power device by integrating the charging current at the turn-on interval[43]. A wide bandwidth current probe is needed to capture the transient current. Full bridge test setup in [44] lower the bandwidth requirement of current probe. Output charge is calculated by integrating the inductor current over a time interval during which zero-voltage-switching of the bridge is just achieved. Accurate results are hard to achieve for two reasons using this method. Firstly, the starting and ending points of soft switching are hard to detect from the voltage waveform across the DUT. Secondly, the voltage probe brings in its parasitic 21

44 capacitance to the measurement system. Another half-bridge output charge test set-up is also carried out to determine the output charge of 300V GaN-based half-bridge in [44]. But no actual configuration, detailed analysis, and accuracy information were provided. And without these, no trustable results can be got. This study will conduct a thorough analysis and careful certify the measurement system. Detailed system design consideration to assure safety, high accuracy and simplicity for the high voltage (kilo volts) test are discussed. A test setup is built for 15 kv SiC MOSFET s test. Experimental results up to 6 kv are also given. 2.3 Output Charge (Output Capacitance) Measurement Measurement Principle Fig. 2-3 shows the configuration of half-bridge output charge measurement system. In order to measure a high voltage using a general low voltage meter, high accuracy voltage divider resistors Rd and Rs are used. Zi together with DC bus capacitor Cdc are designed to form a low pass filter, such that only low-frequency current pass through the DC current meter, which improves the accuracy of Idc s measurement. Enough safety distance between highlighted high voltage area in Fig. 2-3 and tester has to be ensured during the test. 22

45 High Voltage Z i R d Q 1 V in V dc C dc DUT - R s V V s Q 2 A I dc i Q Fig. 2-3 Half-bridge output charge measurement system V m V gs2 V gs1 V gs2 V dc V ds2 V ds1 T s i Q Q oss Q oss Q oss t 5 t 6 t 0 t 1 t 2 t 3 t 4 t Fig. 2-4 Key waveforms of the half-bridge out-put charge measurement system The top and bottom switches in the half-bridge are driven complementary at a fixed frequency. Fig. 2-4 shows the key waveforms of the system. Q2 was on before t0, thus the drain to source voltage of Q1 - Vds1 equals to Vdc, while Vds2 is zero. When Q2 turns off at t0, Vds2 stays at zero, since there s no current loop for the charging of Coss2. Notice that, leakage current of MOSFETs are so small that can be ignored here. The equivalent circuit is given in 23

46 Fig The gate to source voltage of Q1 - Vgs1 reaches its miller voltage Vm at t1. As shown in Fig. 2-6, the channel of Q1 starts carrying current. Coss1 discharges through Q1 s channel. In the meantime, Coss2 is charged by iq, which also runs through the channel of Q1. Vds2 reaches Vdc at t2. The integration of iq over t1 to t2 is the output charge of Q2. Similar operation principle applies to t4 to t5. During which, Coss1 is charged by iq, as shown by the equivalent circuit in Fig Obviously, both Coss1 and Coss2 are charged once by iq within a switching period. Assuming the output charge of both Q1 and Q2 under Vdc are equal, the average iq is therefor: t6 t Q i dt i Q Q f Q f (2.1) 0 Q oss1 V 2 2 dc oss Vdc s oss Vdc s Ts Where, Ts is the switching period, and fs is the switching frequency. According to Kirchhoff s Current Law, one obtains: Average (2.2) at both sides yields iq icap Idc (2.2) iq icap Idc (2.3) In steady state, the net charge in capacitor Cdc. The average value of icap must be zero in equilibrium, thus: I i 2Q f (2.4) dc Q oss Vdc s The output charge of the DUT can now be derived as: Q I 2 f (2.5) oss Vdc dc s 24

47 Z i R d Q1 C oss1 V in V dc - C dc R s V V s Q2 C oss2 A I dc Fig. 2-5 Equivalent circuit of half-bridge out-put charge measurement system: t 0 t 1. Z i R d r on1 i cn1 C oss1 V in R s V V s V dc - C dc i cap Q2 C oss2 A I dc i Q Fig. 2-6 Equivalent circuit of half-bridge out-put charge measurement system: t 1 t 2. Z i R d Q 1 C oss1 V in V dc - C dc i cap R s V V s r on2 i cn2 C oss2 A I dc i Q Fig. 2-7 Equivalent circuit of half-bridge out-put charge measurement system: t 4 t 5. 25

48 Z i R d r on1 i cn1 C oss1 V in R s V dc - V V s C dc i cap C gd2 - Cds2 A I dc i Q Fig. 2-8 Error caused by non-floated gate driver power supply. Z i R d r on1 i cn1 C oss1 V in R s V dc - V V s C dc i cap Q2 C oss2 C pro Voltage Monitor A I dc i Q Fig. 2-9 Error caused by voltage monitor. Z i R d Q 1 V in R s V dc V V s - C dc Q 2 R 3 R 4 C 2 V ds Monitor A I dc R 1 R 2 C 1 V gs Monitor Fig Recommended voltage monitor circuit for the half-bridge output charge measurement. 26

49 Measurement System Consideration Output charge measurement mentioned above can be very accurate. The frequency and current accuracy is ± % and 0.25% respectively for a Fluke 189 multi-meter [45]. However, the system implementation has to be carefully looked into. The precondition of (2.4) is that, all the charging current of both C oss1 and C oss2 go through the dc bus cap and the dc current meter branches. The existing of any other current splitting branch will lead to measurement error. Floating gate driver power supply is therefore required not only for the top device Q 1 but also for the bottom device Q 2. Otherwise, partial charging current of C oss2 could be bypassed from the grounding node of the non-isolated gate driver power supply, as can be seen from Fig Same thing happens when a grounded voltage monitor is connected to the circuit. Fig. 2-9 gives an example of how the voltage monitor diverting the charging current. In the meantime, it brings in additional self-capacitance that influences the test results. If voltage monitors have to be applied to the system, additional impassive components which can greatly increase the impedance of the related branch have to be applied. As shown in Fig. 2-10, R 1 -R 4, can help decreasing the splitting current to acceptable value. As a unipolar device, MOSFET does not have carrier recombination process. Thus, the output capacitor s charging rate does not affect the test results. The loop parasitic resistors won t affect the test accuracy neither. These can be approved by using different gate driving resistors in the later on certification. Switching frequency is chosen based on: firstly, the dc current meter s measurement range, resolution and accuracy; secondly, the power dissipated 27

50 in the devices 2E oss f s won t cause device failure. Interlock time of the gate signal doesn t affect the test result, as long as it is long enough to turn off the device. Error Analysis and Certification According to (2.5), the error of measured output charge depends on the accuracy of DC current and switching frequency s measurement. (2.6) shows the derived error. Given by [45], a Fluke 189 multi-meter has a frequency measured accuracy of ± ( %1) from 500-5k Hz with 0.1 Hz s resolution. It can also provide a ± (0.25%2) current measured accuracy from ma with a resolution of 0.1uA. Ignoring the small differences between measured and exact output charged, replacing Q oss_ex in (2.6) using (2.5) yields (2.7). It shows that, greater output charge and higher switching frequency leads to lower error. If Q oss is larger than 100 nc, and f s is higher than 500 Hz, an error of less than 0.465% can be got using (2.7). err 1 I didc 2fs 2 Q oss _ex dc 2 fs df s (2.6) Where, Q oss_ex is the exact output charge. err ( Idc 0.25% 0.2 ua) ( fs 0.005% 0.1Hz) Idc 2 2fs 2fs Q oss _ex 0.2uA 0.1Hz (0.25% ) (0.005% ) 2Q f f oss s s (2.7) Measurement set-up certification is carried out using Fluke 189 as DC voltage and DC current meter. Commercial available half bridge SiC MOSFET module CAS100H12AM1 is 28

51 Qoss / nc tested at 1.25 khz, 2.5 khz with 20.3 Ω and kω turn on gate resistor for both case. As shown in Fig. 2-11, even with 200 time s different turn on resistor, the measurement still matches very well. To further verify the test setup, an additional high accuracy capacitor C cer (47 pf) is paralleled to the drain to source terminal of Q 2 and Q 1. Because of the additional charge, the DC current is now given by (2.8). Combining (2.8) and (2.4), a solution can be found as (2.9). Compared with the real C cer, the measurement errors given in Fig were confirmed as less than 1%. ' ' dc Q oss Vdc cer dc s I i 2 Q C V f (2.8) C cer ' I dc Idc (2.9) 2V f dc s 1000 Cree 1.2 kv 100A SiC MOSFETs Module Output Charge vs Voltage Rg=20.3, fs=1.25k Rg=20.3, fs=2.5k Rg=2.427k, fs=2.5k Rg=2.427k, fs=1.25k Vdc / V Fig Measured output charge of 1.2 kv SiC MOSFET using different gate resistor and switching frequency 29

52 Error % khz 2.5 khz Vdc/V Fig Error verification using certification caps 10us/div V ds2 : 2V/div V ds2_t1 V gs2 : 10V/div V gs1 : 10V/div Fig Waveforms of half-bridge testbed using -5V turn-off gate to source voltage. 30

53 Z i R d C gd1 Cds1 - V in R s V dc - V V s C dc V gs2 C gd2 Cds2 A I dc (a) C gd2/ 0 V gs2 Cdc C oss1/vdc C ds2/ 0 (b) Fig Half-bridge out-put charge measurement system using negative turn-off gate to source voltage: (a) equivalent circuit of t 0 -t 1 ; (b) simplified equivalent circuit of t 0 -t 1, Due to the fast switching and low turn-on threshold of SiC MOSFETs, a negative V gs level V N (normally from -2V to -5V) during turn-off is recommended to prevent false trigger. This negative V gs will lead to a non-zero starting voltage V ds2_t1. As shown in Fig. 2-13, a negative V ds2_t1 can be observed. From Fig. 2-13, one can see that, the negative V gs2 will cause voltage re-distribution among the parasitic capacitances of Q 1 and Q 2 at the turn-off moment. Using the equivalent circuit in Fig. 2-14, V ds2_t1 can be obtained as (2.10). It is worth of point out that the voltage-dependent capacitances will make V ds2_t1 varies with V dc. i Q, as shown in Fig. 31

54 2-4 during t 0 -t 1 interval now have a positive current pulse. In addition, the highlighted area during t 1 -t 2 is now the output charge from V ds2_t1 to V dc instead of from 0 to V dc. Applying charge balance to C dc yields (2.11). Substitute (2.10) into (2.11), it can then be simplified into (2.12). From (2.12), it can be found that, using a negative turn-off gate voltage V N lead to an additional charge C gd V N in each switching process. Compared with the static methods, this measurement method provides a closer to real application results. But for high voltage devices, where Q oss is much greater than C gd V N after certain voltage level, the additional charge shows a low percentage of the overall measured charge. C Vds 2_ t1 VN C C gd 2/ 0 oss1/ Vdc oss2/ 0 (2.10) " Idc 2 ( Coss/ Vdc Coss/ 0) Vds 2_ t1 Qoss V dc fs (2.11) " Idc 2 Cgd / 0 VN Qoss V dc fs (2.12) 2.4 Measurement Results and Output Capacitance Model Derivation High voltage output charge measurement setup is shown in Fig Switching frequency is chosen to be khz and 1.25 khz, such that Idc ranges from ma and 0-3 ma respectively. The 30 kv, 10 ma maximum output DC power supply can thus guaranty a constant voltage for the measurement. In the meantime, Fluke 189 can measure these current very accurately. 32

55 Isolated Gate Power Supply 15kV SiC Module Voltage and Current Meter Voltage Divider DC Bus Cap Fig High voltage output charge measurement setup The max power losses dissipated in the under test 15 kv SiC module are around 9W (0.625 khz) and 18W (1.25 khz) in all, which won t lead to thermal failure of the devices. Gate signals are delivered from the controller by fiber optical, thus the whole setup can be kept far away from the tester for safety. Experimental waveforms shown in Fig at 6 kv verified the former theoretical analysis. 33

56 V ds2 : 2kV/div 1us/div V gs2 : 20V/div i Q : 1A/div V g1 : 1V/div Fig Half-bridge out-put charge measurement experimental waveforms of 15 kv SiC module (MOSFET and JBS paralleled) under 6 kv. Tested output charge of 15 kv SiC module - MOSFET paralleled with junction barrier Schottky (JBS) from 0 V to 6 kv are given in Fig The tested output charge shows very little differences for different frequency hence validate the measurement method at 6 kv. Another group of measurements were carried out with a DP10-10K-16kV-C high-voltage differential probe paralleled to the drain to source terminal of Q 2. Tested parasitic capacitance of the probe is closely around 6 pf as shown in Fig. 2-18, which indirectly proved the measurement accuracy. 34

57 Probe Cap / pf Qoss / nc Output Charge of 15kV SiC Module fs=0.625k fs=1.25k Vdc / V Fig Experimental output charge measurement results of 15kV SiC Module (MOSFETJBS). 7 Measured Capacitance of Probe Vdc / V Fig Measured parasitic capacitance of isolated differential voltage probe. 35

58 As given in [42], the output capacitance can be expressed as (2.13), where, k is the determined by: 1) the dimensions of the device; 2) the dielectric constant 4H-SiC material; 3) the depletion region doping concentration and 4) the elementary charge. C (V ) oss ds pk V ds k V bi C (2.13) V ds is the drain-source voltage across the SiC device and V bi is the built-in voltage of its PN junction. C pk is the package related parasitic capacitance. The integral of C oss (2.13) over [0-V dc ] yields the output charge model (2.14). V dc k Q (V ) C d V oss dc 0 pk ds Vds Vbi 2 k( V V V ) C V dc bi bi pk dc (2.14) Applying least square curve fitting to the measured output charge as shown in Fig. 2-19, we can now get the parameters k, V bi and C pk as listed in Table 2-1. Substituting these into (2.13), the output capacitance model for 1.2kV 100A SiC MOSFET module (CAS100H12AM1) is given by the solid line shown in Fig The derived model well fitted to the C oss provided by Cree s datasheet, especially when V dc is high. Since Q oss gets larger along with the increasing of V dc, as discussed before the error caused by the current meter discrepancy will be smaller. Similarly, for 15 kv SiC MOSFET module, the least square curve fitted output charge model is presented in Fig Using the fitted parameters listed in Table 2-1, relative output capacitance model is shown in Fig

59 Table 2-1 Curve fitted SiC MOSFET parameters Device Parameter Value 1.2 kv 100 A SiC MOSFET module k Vbi Cpk kv SiC module k Vbi Cpk Fig Output charge curve fitting of 1.2 kv 100 A SiC MOSFET module (CAS100H12AM1) 37

60 Fig Output capacitance for 1.2 kv 100 A SiC MOSFET module (CAS100H12AM1) Fig Output charge curve fitting of 15 kv SiC module (MOSFET and JBS paralleled). 38

61 Fig Output capacitance model for 15 kv SiC module (MOSFET and JBS paralleled). 2.5 Conclusion In this chapter, output charge (output capacitance) measurement methods for high voltage MOSFETs were reviewed. A dynamic half-bridge test setup which can provide measurement results highly close to ZVS operation is thoroughly analyzed. Detailed system configuration and design consideration to reach high measurement accuracy, especially for measurement at kilo volts range were given. Certification methods were provided and verified an < 1% error at high voltage measurements. A test setup was built for 15 kv SiC MOSFET s output charge test. It facilitates the high voltage measurement without a need for any special equipment or complex configuration but still keeps a very high accuracy. Experimental results up to 6 kv verified the theoretical analysis. This setup can also test other voltage dependent capacitors. 39

62 Chapter 3. A New Zero Voltage Switching Analysis Method of Power MOSFET Based on State- Trajectory 3.1 Introduction Based on wide-bandgap materials such as SiC and GaN, power MOSFETs are capable of operating at higher switching frequencies and higher power levels due to their improved figureof-merit (FOM) compared with Si devices [46]. The impressive switching performance enables the development of higher switching frequency converter systems that have greater power density, for the size reduction of magnetic components and capacitors in the system [47]. When the switching frequency increases to a certain level, hard switching losses become significant. These deteriorate both the power efficiency and the power density of a converter, for a bulky cooling system is required to prevent the MOSFETs from being overheated [34]. Soft switching, especially zero voltage switching (ZVS) is therefore important to maintain the privilege of using wide bandgap MOSFETs. Topologies with intrinsic ZVS capability such as half-bridge, full-bridge[48], discontinuous conduction mode (DCM) synchronous buck and DCM synchronous boost converters [49] are preferred. In order to secure ZVS operation in the meantime avoid system over design, the following three major concerns need to be addressed for ZVS analysis: 1) ZVS conditions; 40

63 2) Duration of the soft-switching interval; 3) ZVS time window. An analytical approach was proposed to determine the accurate zero-voltage switching (ZVS) criteria for full-bridge LLC converter, where the magnetic inductor s current was considered as constant [50]. In [47], ZVS boundary equations are provided in terms of the required energy stored in corresponding inductors. Later on, in [46], LI 2 2Q oss V DC has been identified as a requirement for complete ZVS. Nonlinear behavior of MOSFET s parasitic output capacitor was considered. However, all the above ZVS analysis methods are either for special cases only, or can not address all the listed three ZVS concerns. This chapter introduces a straightforward state trajectory analysis approach that can be universally applied to any ZVS study. It provides analytical formulas associated with the ZVS criteria, soft switching commutation time, and remaining inductance current after ZVS transition, and hence, addresses all the aforementioned three ZVS concerns at once. Last but not the least, the nonlinearity of MOSFET s output capacitance is also discussed. 3.2 State-Trajectory for Zero-Voltage Switching Analysis Graphical state-trajectory analysis is very clear and useful to analyze the resonant converters such as series resonant converter (SRC), series paralleled resonant converter (LLC) etc. [51][52][53]. Compared with mathematical analysis, it provides a much simpler and more direct approach to monitor the inductor current and capacitor voltage of a resonant tank. When it comes to ZVS analysis, the resonant tank becomes to be MOSFETs output capacitors and relative inductance. Fig. 3-1 shows an example of different resonant tanks being considered: 41

64 in resonant converter operation analysis, the converter s resonant tank includes L r and C r is of interest; during soft switching interval, the resonance between L r, C oss1 and C oss2 is of importance. The resonant frequency of the ZVS resonant tank is much higher than the resonant frequency of the converter resonant tank, thus, C r can be equivalent to a voltage source - V Cr during the switching interval as shown in Fig It can be further simplified as Fig V i Q 1 C oss1 L r ZVS resonant C r Converter resonant Q 2 C oss2 V o Fig. 3-1 ZVS resonant tank and converter resonant tank Q 1 C oss1 ZVS resonant V i L r V Cr Q 2 C oss2 V o Fig. 3-2 Equivalent circuit of series resonant converter s ZVS switching interval. 42

65 C oss1 v ds1 V i L r C oss2 v ds2 V Cr V o Fig. 3-3 Simplified equivalent circuit of series resonant converter s ZVS switching interval. Q 1 Q 3 L s n:1 Q 5 V i V o Q 2 Q 4 Q 6 (a) V i /2 C oss1 v ds1 V i L s ± nv o V i /2 C oss2 v ds2 (b) Fig. 3-4 (a) Half-bridge DAB converter. (b) Equivalent circuit of half-bridge DAB converter during soft-switching. Similarly, in Fig. 3-4 (a), the half-bridge dual active bridge (DAB) converter s ZVS equivalent circuit is given in Fig. 3-4(b). Here, the DC bus capacitors have much greater 43

66 capacitance compared with the MOSFET s parasitic output capacitance. Their voltages barely change during the switching interval, thus, can be consider as DC sources. Output voltage is reflected to the primary side of the transformer. Its polarity can be decided by the switching status of Q 3 -Q 6. Q 1 Q 3 Q 5 L s n:1 Q 7 V i V o Q 2 Q 4 Q 6 Q 8 (a) C oss1 v ds1 C oss3 v ds3 V i L s ± nv o C oss2 v ds2 C oss4 v ds4 (b) Fig. 3-5 (a) Full-bridge DAB converter. (b) Equivalent circuit of full-bridge DAB converter during soft-switching Fig. 3-5 (a) is an example of full-bridge DAB converter. Equivalent circuit during softswitching interval for non-phase shift full-bridge is given in Fig. 3-5(b), where all parasitic output capacitors of Q 1 -Q 4 are involved. If phase shift modulation is adopted, only three of the parasitic output capacitors are to be involved. 44

67 For DCM synchronous Boost and Buck converters (Fig. 3-6 (a) and Fig. 3-7(a)), equivalent circuits for ZVS switching transient are shown in Fig. 3-6(b) and Fig. 3-7(b). Q 1 C oss1 v ds1 C oss1 L V o L V o V i Q 2 C oss2 V i v ds2 C oss2 (a) (b) Fig. 3-6 (a) Synchronous Boost converter. (b) Equivalent circuit of synchronous Boost converter during soft-switching Q 1 C oss1 C oss1 v ds1 V i L V i i Q1 i L L Q 2 C oss2 V o C oss2 i Q2 v ds2 V o (a) (b) Fig. 3-7 (a) Synchronous Buck converter. (b) Equivalent circuit of synchronous Buck converter during soft-switching 45

68 To further demonstrate how to use state-trajectory for ZVS analysis, DCM synchronous Buck converter will be discussed in detail. Time domain waveforms are presented in Fig. 3-8(a). According to the equivalent circuit given by Fig. 3-7(b), buck inductor L resonant with C oss1 and C oss2 within the switching interval. Resonant frequency and angular velocity can be written as: f r_ s 1 2 L( C C ) oss1 oss2 (3.1) 2 f (3.2) r _ s r _ s Graphical state-trajectory is shown in Fig. 3-8(b). The horizontal axis represents the voltage of C oss1 and C oss2, while the vertical axis stands for the inductor current i L multiplied by the resonant tank s characteristic impedance Z (3.3). Before the switching interval, Q 1 is on. Q 1 turns off at the beginning of the switching transient t 0, where the inductance current is I L_0. According to the equivalent circuit shown in Fig. 3-7(b), center of the state-trajectories v ds1 - i L Z and v ds2 -i L Z are (V i V o, 0 )and (V o, 0 ) respectively. Both state-trajectories share the same inductor current but have complementary drain to source voltage - v ds1 and v ds2. Z C L C oss1 oss2 (3.3) 46

69 V i Q gs1 T ZVS T w Q gs2 v ds1 t 0 I L_0 v ds2 t i L Q oss1 Q oss2 I L_rem dil /dt=v o /L 0 t 0 t 1 t 2 t (a) i L Z v ds1 v ds2 I L_0 Z I L_rem Z 0 r s α γ β V i -V o V o V i v ds (b) Fig. 3-8 Synchronous Buck converter - Q 2 s ZVS switching interval: (a) Time-domain waveforms; (b) State-trajectories. 47

70 After Q 1 turns off at t 0, voltage across C oss1 - v ds1 starts rising from 0 towards V i, in the meantime, voltage across C oss2 v ds2 begins decreasing from V i towards 0. The radius of both state-trajectories r s is given by (3.4). 2 2 _0 ( ) r I Z V V (3.4) s L i o To secure complete ZVS of Q 2, inductor current at the end of the ZVS transient t 1 has to be greater or equal to zero, meaning I L_rem 0. According to the state-plane, it also means that the radius r s should be greater or equal to V o as shown in (3.5). Replacing r s in (3.5) with (3.4), Q 2 s ZVS criteria can then be obtained as (3.6). r s V o (3.5) 2 2 IL _0Z 2VV i o Vi It is easy to find the state-plane angle γ as given in (3.7). (3.6) (3.7) where, I Z L _0 a sin rs V o a cos rs. Converting the state-plane angle γ to the time-domain, ZVS transition time can be estimated as: T ZVS (3.8) r_ s Inductor current at the end of ZVS transient I L_rem is derived in (3.9). 48

71 I L_ rem rs sin( ) (3.9) Z If I L_rem is greater than zero, Q 2 s body diode starts conducting current after v ds2 drops below 0 and then to its threshold voltage. ZVS can now be fulfilled by turn on Q 2. In real implementation, Q 2 is turned on after t 1 to give proper margin that can compensate the parameters discrepancy between calculation and the prototype. Starting from t 1, i L decreases from I L_rem and reaches zero at t 2. If Q 2 is not turned on before t 2, it will lose ZVS. Full ZVS can only be achieved within the time interval t 1 - t 2, therefore, ZVS window can be written as: T t t LI L _ rem w 2 1 (3.10) Vo If ZVS window T w is too short, fulfilling Q 2 s ZVS will be difficult. The above discussion focused on Q 2 s ZVS process. For the ZVS analysis of Q 1, the statetrajectories are shown in Fig State-trajectory center of v ds1 -i L Z and v ds2 -i L Z are kept at the same points - (V i V o, 0 ) and (V o, 0 ) respectively. v ds1 decreases from V i towards 0, and v ds2 rises up from 0 towards V i. Trajectory radius r s can be obtained by (3.11). 2 2 ' _0 r ' I Z V (3.11) s L o To ensure Q 1 s full ZVS, inductor current I L_rem has to be negative at the end of the ZVS transition, meaning (3.12) has to be satisfied. r ' V V (3.12) s i o Combining (3.11) and (3.12), Q 1 s ZVS criterion can then be derived as (3.13). 2 2 _0 I ' Z V 2VV (3.13) L i i o 49

72 ZVS transition time and ZVS window can be calculated similarly as before. i L Z 0 V i -V o V o V i v ds I L_0 Z r s I L_rem Z v ds1 v ds2 Fig. 3-9 Synchronous Buck converter state-trajectories of Q 1 s ZVS switching interval. 3.3 Nonlinear Behavior of the Parasitic Output Capacitance To conduct state-trajectory analysis, it is important to figure out the capacitance and inductance of the resonant tank. In the former discussion, the resonant capacitors C oss1 and C oss2 have been considered to be constant. However, MOSFETs parasitic output capacitors are widely known as highly voltage dependent[38][46]. If resonant capacitor varies a lot with its voltage, the state-trajectory becomes very complicate. It is then very difficult to derive the analytical formulas listed in the above section. Voltage independent equivalent resonant capacitors are therefore needed. 50

73 Applying Kirchhoff's current law (KCL) to the midpoint of the half-bridge in Fig. 3-7(b). The inductance current i L equals to the sum of the charging current of C oss1 and the discharging current of C oss2 : i i i (3.14) L Q1 Q2 The integration of i L over t 0 -t 1 can be written as: t1 t1 i dt L i Q1 i Q2 dt Q oss1 V i Q oss2 V i t (3.15) t 0 0 According to the state-plane in Fig. 3-8(b), from t 0 to t 1, the inductance current can be given as: i r sin t (3.16) Z s L r _ s Taking (3.16) back to (3.15), replacing r s with (3.4) and Z with (3.3), yields: C Q V Q V oss1 i oss2 i oss1coss 2 (3.17) Vi Charge equivalent output capacitance of Q 1 and Q 2 are now identified as the equivalent resonant capacitance in the state-trajectory ZVS analysis. 51

74 C oss(v ds_i-1) C oss(v ds_i) v ds_i-1 v ds_i Fig Voltage dependent output capacitance of MOSFET i L Z(v ds ) s i1 s i1 s i-1 s i rs i-1 r si s i s i-1 r si r s i-1 I L_0 Z 0 s 0 0 r s0 v ds1_i γ i s 0 r s0 V i -V o V o dv V i v ds Fig Voltage dependent variable capacitance ZVS state-trajectories In order to evaluate how the output capacitance s nonlinearity will affect the ZVS transition time - T ZVS as well as the inductor s remaining current I L_rem. State-trajectory ZVS analysis 52

75 based on variable output capacitance is carried out using Matlab. Fig presents the relationship between output capacitance and V ds (drain to source voltage), which is provided by the datasheet of MOSFET (CMF20120D). Within a very small voltage interval [ v ds_i-1, v ds_i ), the output capacitance is assumed constant at C oss (v ds_i-1 ). The finer the voltage interval is, the better a C oss estimation will be. Fig shows the ZVS state-trajectories with voltage depend output capacitors. The variable capacitance ZVS state-trajectories have the same centers as the constant capacitance ZVS state-trajectories do. The trajectories begin with v ds1 = 0, v ds2 = V i, i L = I L_0. For Q 2 s ZVS, the resonant characteristic impedance at the very beginning can be written as: The first section radius is therefore: Z 0 L C C V 0 oss1 oss2 i (3.18) 2 2 r I Z V V (3.19) s0 L _ 0 0 i o For an arbitrary section of the trajectory, the characteristic impedance is : Z i L C v C v oss1 ds1_ i oss 2 ds2_ i (3.20) v i dv, v V v. Where, ds1_ i ds2_ i i ds1_ i The corresponding trajectory radius is : _ 1_ 2 2 r I Z v V V si L i i ds i i o (3.21) In (3.21), I L_i is obtained from the last step: 53

76 I L_ i r si1 v sin acos r Z i1 ds1_ i si1 (3.22) The state-plane angle γ i can be computed using: vds 1_ i1 Vi Vo vds 1_ i Vi Vo i acos acos rsi rsi (3.23) Transforming the state-plane angle into time domain: T ZVS _ i i (3.24) r _ si r where, _ si 1 L C v C v oss1 ds1_ i oss2 ds2 _ i. Assuming L is 50 uh, I L_0 is 2 A, V i is 600V and V o is 500V the variable capacitance ZVS state-trajectories are depicted in Fig by the solid curves, where the dash curves are the ZVS state-trajectories with output charge equivalent constant capacitors. The characteristic impedance varies along with the variable capacitance. At the beginning of the ZVS transient, v ds1 is close to zero, while v ds2 is around V i, the overall output capacitance of Q 1 and Q 2 is therefore higher than the charge equivalent capacitance. This is also true at the end of the ZVS transient, where, v ds1 is close to V i, v ds2 is around 0. In the middle of the transient, the overall output capacitance of Q 1 and Q 2 is lower than the charging equivalent capacitance. These explain why the trajectories have larger radius in the middle, but smaller radius in by both sides. For the state-trajectories with equivalent constant capacitors, the characteristic impedance is then constant during the ZVS process, the radius is therefore constant at r s. 54

77 Converting the state-plane trajectories into time domain waveforms shown in Fig The solid waveforms reflect the voltage and current with voltage dependent MOSFET output capacitance. The dash waveforms are the voltage and current with charge equivalent constant MOSFET output capacitance. The ZVS transient shows some differences, but the ending points coincides. V ds2 V ds2_eq r si r s r sn r s r s0 V o Fig variable capacitance ZVS state-trajectories and charge equivalent constant capacitance ZVS state-trajectories. 55

78 V ds2_eq V ds2 i L i L_eq Fig variable capacitance and charge equivalent constant capacitance ZVS timedomain waveforms. To further verify that ZVS transient analysis using charge equivalent capacitance is valid, with V i fixed at 600V, V o from 0 to 600V, L equals to uh, initial inductor current I L_0 from 0 to 5 A, the ZVS transients are calculated. ZVS transient time - T ZVS using both variable and constant capacitance state-trajectory analysis show a less than 12% differences according to Fig For the inductor current at the end of the ZVS transition I L_rem, the error become as high as 270% according to Fig However, if Fig is reprinted using I L_rem to color map the data points. As shown in Fig. 3-16, it is obvious that the large error happens when 56

79 I L_rem is close to zero, where the absolute current difference is still small enough for circuit design. A measurement setup given in Fig is built to verify the ZVS analysis method. CAS100H12AM1 is adopted as the half-bridge MOSFETs. If upper MOSFET is driven by a gate pulse, the inductor current becomes positive. After the upper MOSFET is turned off, this positive inductor current charge C oss1 and discharge C oss2, achieving ZVS of Q 2. Test waveforms are shown in Fig More measurements are carried out with L equals to uh, V o from V. According to the measurement results shown in Fig. 3-20, using charge equivalent constant capacitance based state-trajectory ZVS analysis has less than 10% error regarding the ZVS duration T ZVS. According to Fig. 3-21, the remaining current has greater relative errors between the calculated and the measured results, but the absolute current discrepancies are small as shown in Fig Fig Error of ZVS transition duration - T ZVS between charge equivalent constant capacitance based and voltage-dependent variable capacitance based state-trajectory analysis. 57

80 Fig Error of inductor s remaining current at the end of ZVS - I L_rem between charge equivalent constant capacitance based and voltage-dependent variable capacitance based state-trajectory analysis, color mapped by inductor s initial current I L_0. Fig Error of inductor s remaining current between charge equivalent constant capacitance based and voltage-dependent variable capacitance based state-trajectory analysis, color mapped by I L_rem. 58

81 V i Q 1 v gs1 C oss1 v ds1 i L - L Q 2 C oss2 v ds2 - C o V o Fig ZVS measurement circuit. Driver C o C i L 1.2kV 100A SiC MOS Fig ZVS measurement setup. 59

82 Error (%) time: 1 us/div v gs1 : 20 V/div i L : 1 A/div v ds1 : 200 V/div v ds2 : 200 V/div Fig ZVS measurement waveforms. 5% 4% 3% 2% 1% 0% -1% -2% -3% -4% -5% Inductance Initial Current (A) Vo=100V Vo=200V Vo=300V Vo=400V Vo=500V Fig Discrepancy between measured and charge equivalent constant capacitance statetrajectory calculated ZVS duration - T ZVS. 60

83 Inductor Current at the End of ZVS (A) Error (%) 2% 0% -2% -4% -6% -8% -10% -12% -14% -16% -18% Vo=100V Vo=200V Vo=300V Vo=400V Vo=500V Inductor Current at the End of ZVS (A) 6 Fig Discrepancy between measured and charge equivalent constant capacitance statetrajectory calculated ZVS remaining current I L_rem Vo=100V Vo=200V Vo=300V Vo=400V Vo=500V Inductance Initial Current (A) Fig Measured and charge equivalent constant capacitance state-trajectory calculated ZVS remaining current I L_rem. 61

84 3.4 Conclusion In this chapter, a state-trajectory ZVS analysis method was proposed that can be easily and effectively applied in a large number of topologies with ZVS capability. Using the proposed ZVS analysis method, three ZVS related questions: 1) the circuit ZVS criteria; 2) duration of the full soft-switching interval; 3) inductor current at the end of ZVS process (related to the ZVS window in real implementation), can all be answered at once. According to mathematical derivation, MOSFET output charge equivalent capacitance was chosen to simplify the analysis. Nonlinearity of MOSFET s output capacitance was discussed. Variable capacitance statetrajectory ZVS analysis was carried out. Comparison of the variable capacitance based and output charge equivalent constant capacitance based state-trajectory ZVS analysis shows little difference in terms of ZVS duration and remaining inductor current. This proved that using output charge equivalent constant capacitance based state-trajectory ZVS analysis is not only simple but also accurate enough. 62

85 Chapter 4. A Medium Voltage Medium Frequency Isolated DC-DC Converter Based on 15 kv SiC MOSFETs 4.1 Introduction Due to its numerous advantages over traditional AC system, the medium voltage (MV) DC is considered an enabling and promising technique in future power distribution grid, microgrids and all-electric ship power systems [15][16]. In such applications, an isolated MV DC-DC converter plays a critical role to connect different DC systems and energy resources. Isolated MV DC-DC converter is also a key stage in traction and solid state transformers [5]. Because of the limited voltage capability of power semiconductor devices, multi-level topologies are usually used in MV applications, such as neutral point clamped multi-level converters, cascaded H-bridge and modular multi-level converters [54][22][32]. In recent years, the development of high voltage wide band gap devices provides an opportunity to use simple and reliable two-level converters for MV power conversions. Specifically, the 15 kv silicon carbide (SiC) power MOSFETs with fast switching speed are promising device technology for reducing the size, weight and complexity of medium voltage converters [27][55]. However, due to the high operation voltages, potentially from 6 kv to 12 kv, a significant amount of energy stored in the parasitic output capacitance is discharged during each turn-on event [29], leading to a high turn-on loss. This high turn-on loss limits its 63

86 operating frequency to less than 10 khz [35]. Zero voltage turn on is therefore extremely useful to eliminate this loss and increase the switching frequency. Among numerous two-level topologies [8] [25][50] [56], resonant converters and dual active bridge (DAB) converters are attractive for isolated power conversions because of their high efficiency resulting from excellent soft switching capability. DAB DC-DC converters have advantages like simple structure, zero voltage switching (ZVS) capability, and most importantly, easy to achieve a reliable start-up and over-load protection [2][29]. But it loses ZVS at light load operation. Together with its high turn-off current, the overall efficiency is deteriorated [56]. On the other hand, the series resonant converter can realize ZVS turn-on from zero to full load range. It is widely adopted by many for fixed voltage gain applications such as the DCX (DC transformer) in power supplies. It is also utilized in a medium voltage IGBT based power electronic traction transformer by ABB [32]. It has lower turn-off current compared with the DAB [8]. The series resonant converter is normally designed to operate at its resonant frequency to obtain the highest efficiency. However, during over-load and startup, extreme high current and voltage stress appear in the resonant tank due to its close to zero impedance characteristic [53]. This can cause fatal failure of the converter. The resonant tank s impedance and the voltage across it are the two determinants of its over-load current. Reducing the duty cycle during over-load can reduce the voltage across the resonant tank [52]. In [33], the impedance of the resonant tank is effectively increased by making the switching frequency much higher than the resonant frequency. However, neither methods can secure cycle-by-cycle protection.[33] [57] can realize fast over-load protection by clamping the voltage across the resonant capacitor using additional diode or auxiliary circuit. Resonant capacitor is bypassed 64

87 under over-load operations, thus, the impedance of the converter increases. However, for MV application, using fast MV diodes for only the abnormal protection is not cost effective while the added transformer in the auxiliary circuit in [57] leads to galvanic isolation challenge. To solve the start-up and over-load protection issues of the resonant converter such that it can be used for robust and rugged MV DC applications, an isolated DC-DC bus converter combining resonant converter and DAB is proposed [34]. By utilizing two splitting resonant capacitors at the low voltage (LV) side, it is possible to bypass them with paralleled LV diodes when over-load happens. The impedance of the resonant tank is then naturally increased. Cycle-by-cycle over-load protection can therefore be realized. The proposed converter has the advantages of high efficiency and high reliability for MV applications. 4.2 Operation Principle Fig. 4-1 shows the proposed resonant and DAB hybrid DC-DC converter [34]. On the MV side, a half-bridge configuration is used because of the relatively small MV side current. This also minimizes the number of MV devices and associated gate driver circuits. Hence, this topology can be considered the simplest MV DC-DC converter from MV switch count point of view. C dc1 and C dc2 are DC bus capacitors on the MV side. L m and n are the magnetizing inductance and turns ratio of the transformer respectively. L s is the resonant inductor which can be integrated into the transformer as the leakage inductance. On the LV side, C r1 and C r2 are the resonant capacitors with D 3 and D 4 in parallel for over-load current limiting. Q 1 and Q 2 are the main active switches on the MV side, while Q r1 and Q r2 are the synchronous rectifier switches on the LV side. To simplify the analysis, the following assumptions are made: 65

88 1) Parasitic capacitors of semiconductors and transformer are ignored; 2 ) C dc1 and C dc2 have large capacitance and evenly share the total MV side voltage; 3) C LV_dc is much larger than C r1, C r2 and keeps V LV constant within one switching period; 4 )The capacitance of C r1 equals to that of C r2. Q 1 V MV C dc1 n:1 L s Q r1 C r1 D 3 V LV L m C LV_dc R - C dc2 Q 2 Q r2 C r2 D 4 - Fig. 4-1 Proposed novel resonant and DAB hybrid DC-DC converter. Normal Load Operation Under normal load condition, the proposed converter operates like a conventional series resonant converter with open loop control. D 3 and D 4 do not conduct in this scenario. Equivalent circuit of the converter is given in Fig In order to achieve the best efficiency, the series resonant DC-DC converter is designed to operate at its series resonant frequency f r as shown in (4.1). Q 1 and Q 2 are symmetrically switched in each switching period with duty cycle close to 0.5. The converter voltage gain V MV /V LV equals to the transformer s turns ratio - n. f r 1 r (4.1) 2 L (C C ) 2 s r1 r 2 66

89 Where, r 1 L ( C C ) s r1 r 2 Q 1 V MV C dc1 n:1 L s Q r1 C r1 D 3 V LV L m C LV_dc R - C dc2 Q 2 Q r2 C r2 D 4 - Fig. 4-2 Equivalent circuit of the proposed converter under normal load operation. Z r i Ls Maximum load without voltage clamping r max Q 1, Q r1 on r nor Noramal load 0 No load V MV /2n V LV v Cr1 Q 2, Q r2 on Fig. 4-3 Steady-state trajectory under normal load condition. 67

90 Graphical state-trajectory [51] [52] is an effective tool for analyzing resonant converters. Under normal load condition, the steady-state trajectory of the proposed converter is presented in Fig The x-axis is the voltage across C r1, while the y-axis is the current of resonant inductor L s multiplied by the impedance of the resonant tank Z r (4.2): Z r Ls (4.2) C C r1 r 2 As can be seen from Fig. 4-3, the trajectory has a center of (V MV /2n, 0), while its radius depends on the load. In steady state, the net change of V LV over a complete switching cycle is zero. Considering the charge balance of C LV_dc, equation (4.3) can be found. Replacing i Ls in (4.3) with r nor sinω r t/z r, the relationship between r nor (radius under normal load operation) and load current can be given by (4.4). When there is no load, the radius will be zero. Heavier load leads to a larger radius. r nor is designed to be less than V MV /2n for normal load operation as shown in (4.5). This implies that the voltage across C r1 and C r2 should not be over V LV or under 0 V. Combine (4.4) and (4.5), the critical load R cri is derived as (4.6). When load is heavier than R cri, D 3 and D 4 will start clamping the voltage across C r1 and C r2. T r i 2 0 Ls I (4.3) o Tr where, T 1 f. r r r Z I (4.4) nor r o rnor rmax V 2n V 2 (4.5) R Crit MV LV 2 Z (4.6) r 68

91 V MV - C dc1 Q 1 C dc2 Q 2 v tp - L m n:1 L s Q r1 Q r2 C r1 C r2 D 3 C LV_dc D 4 V LV (a) Mode 1: t 0 -t 1 (resonant mode) - V MV /2n L s C r1 C r2 V LV V MV C dc1 Q 1 v tp - L m n:1 L s Q r1 C r1 D 3 C LV_dc V LV V MV /2n L s V LV - C dc2 Q 2 Q r2 C r2 D 4 (b) Mode 2: t 1 -t 2 (DAB mode) - V MV C dc1 Q 1 v tp - L m n:1 L s Q r1 C r1 D 3 C LV_dc V LV V MV /2n L s V LV - C dc2 Q 2 Q r2 C r2 D 4 (c) Mode 3: t 2 -t 3 (DAB mode) - - V MV C dc1 Q 1 C dc2 Q 2 v tp - L m n:1 L s Q r1 Q r2 C r1 C r2 D 3 C LV_dc D 4 V LV - V MV /2n L s C r1 C r2 V LV (d) Mode t 3 -t 4 Fig. 4-4 Operation modes and equivalent circuits under over-load operation. 69

92 Over-load Operation In over-load scenario (R < R cri ), both the resonant current and the voltages across C r1 and C r2 increase. This is especially critical when short circuit occur (R =0). Once V Cr1 or V Cr2 reaches V LV, D 4 or D 3 starts conducting. C r1 and C r2 will therefore be bypassed. The proposed converter then switches from the pure resonant mode to a resonant and DAB mixed mode. The operation modes and equivalent circuits under over-load condition are given in Fig Corresponding key waveforms are presented in Fig Steady-state trajectories are shown in Fig During over load or short circuit condition, the DC bus voltage V LV will decrease, hence there are two very different cases to consider in Fig. 4-6: V LV < V MV /2n and V LV V MV /2n. There are eight possible operation modes within each switching period, where four modes in each half cycle are typical. Thus, only four modes will be discussed in this paper. Q 1 and Q 2 are complementary switched with the same on- and off-time. 70

93 V gsq1 V gsq2 V gsq1 t on t off V tp /n I Ls ni Lm I D4 I D3 I Cr1 I Cr2 V Cr1 t 0 t 1 t 2 t 3 t 4 V Cr2 t Fig. 4-5 Steady-state waveforms under over load operation (V LV <V MV /2n) Z r i Ls Z r i Ls V LV V MV /n V LV V MV /2n C Mode 2 B Mode 1 Mode 3 Mode 1 B Mode 2 C Mode 3 V MV /2n r max O 2 θ O A D 1 A 0 V LV V MV /2n v Cr1 0 V LV -V MV /2n r max r max O 2 O 1 V LV -V MV /2n V MV /2n V LV v Cr1 r max θ D V LV <V MV /2n 0 t (a) V LV <V MV /2n (b) V LV V MV /2n Fig. 4-6 Steady-state trajectory under over-load operation 71

94 Mode 1 [t0-t1]: A-B At t 0, both the current of L s and the voltage across C r1 are zero (ignoring the magnetizing current). When Q 1 and Q r1 are turned on, V MV /2n is applied to the resonant tank; L s resonates with C r1 and C r2. Equivalent circuit is given by Fig. 4-4(a). Half of the resonant current i Ls charges C r1, while the other half goes through C LV_dc and discharges C r2. The operating point moves along the trajectory curve in Fig. 4-6 from point A towards point B. The center of the trajectory from A to B is (V MV /2n, 0). The radius equal to r max, which is V MV /2n. This operation mode is the same as the conventional series resonant converter and will be called resonant mode in this paper. The resonant current and the voltage across C r1 during this resonant period can be expressed as: Mode 2 [t1-t2]: B-C r i t t t (4.7) max Ls ( ) sin( r ( 0)) Zr V ( t) r r cos( ( t t )) (4.8) Cr1 max max r 0 Mode 1 ends when V Cr1 increases to V LV and V Cr2 reaches zero. The inductor current will transfer from the resonant capacitors to D 4 at t 1. C r1 and C r2 are then bypassed, meaning the converter enters the DAB mode. Fig. 4-4(b) gives the equivalent circuit of this mode. The voltage across L s is V MV /2n - V LV. The resonant current is given as (4.9): V 2nV (t t ) (4.9) 2nL MV LV () t I Ls Ls _ t1 1 i s 72

95 where, t 1 I Ls _ t1 VMV 2nVLV arccos( ) V MV V ( V 2 nv ) 2nZ 2 2 MV MV LV r r, If V LV is smaller than V MV /2n, voltage across L s will be positive, leading to a linearly increasing of i Ls. As shown in Fig. 4-6(a), the trajectory path will go upwards from point B to C. Otherwise, when V LV is greater than V MV /2n, there will be a negative voltage across L s that causes a linear decreasing of i Ls. Correspondingly, the trajectory path moves downward from point B to C as given in Fig. 4-6(b). Fig. 4-5 gives the example waveforms when V LV is much lower than V MV /2n and i Ls ramps up. Mode 3 [t2-t3]: C-D By ignoring the switching transient when Q 1 turns off at t 2, the primary current transfers from Q 1 to the anti-paralleled diode of Q 2 as shown in Fig. 4-4(c). i Ls (4.10) decreases linearly due to the negative voltage across L s. The trajectory in Fig. 4-6 for both cases are moving downward from point C to D. V 2nV (t t ) (4.10) 2nL MV LV () t I Ls Ls _ t 2 2 i s where, t DT, I 2 s V 2nV MV LV I (t t ) 2nL Ls _ t 2 Ls _ t1 2 1 s Mode 4 [t3-t4]: D 73

96 i Ls decreases to zero at t 3, and the converter will stay at this mode until Q 2 is turned on. To simplify the analysis, we assume V Cr1, V Cr2 stay at zero or V LV, ignoring the resonant between the parasitic inductance and capacitance of the transformer and semiconductor devices. Under this condition, the operating point stays at D in Fig Power Stage Design Considerations Magnetizing Inductance and Dead Time Design to Best Utilize the 15 kv SiC MOSFET Module The proposed hybrid DC-DC converter is designed for MV DC-DC applications by using the recently developed 15 kv/10 A SiC MOSFET. The SiC MOSFET is co-packaged with a 15 kv JBS diode. In order to secure full ZVS, magnetizing inductance has to be carefully designed, such that the output charge Q oss of the SiC modules Q 1 and Q 2 can be fully charged and discharged within the dead time t d as shown in (4.11). 2 Q ( V ) V T t 8L (4.11) oss MV MV r d m It has been discussed in [50] that there is a trade-off between the magnetizing inductance and the dead time. For larger L m, longer dead time is needed for ZVS, thus the effective duty cycle decreases. This will lead to the increasing of RMS resonant current [50] to deliver the same amount of power. If the L m is smaller, the dead time can be shorter, but the RMS resonant current may still be high because of the higher magnetizing current. To optimize the design, the output charge and the conducting resistance of the power MOSFET need to be accurately characterized first. 74

97 I r _ RMS 2 2 TP s o VMV T r 2TV r MV 8 2L m (4.12) Where, the switching period T s = T r 2t d. To obtain the output charge characteristic of the 15 kv SiC MOSFET module, a dynamic half-bridge test setup that can provide high accuracy measurement results was built [58]. Fig. 4-7 gives the measured results up to 6 kv. Then, the relationship between output charge and the drain to source voltage is derived by curve fitting. The result is shown in Fig. 4-7 and (4.13). Qoss (V ds ) Vds (nc) (4.13) where, V ds is the drain to source voltage of the MOSFET. With a 20 V gate to source voltage, the measured on-resistance of the 15 kv SiC MOSFET is given in Fig Based on the measured data, a R on model can then be obtained as (4.14). T j Ron R0 T (4.14) where, R 0 = 0.875Ω, T 0 = K. 75

98 1.6 Qoss / uc Q oss_measure Q oss_model V ds / kv Fig. 4-7 Measured and modeled output charge of the 15 kv SiC MOSFET module. 6 Ron of 15kV SiC Mosfet [ohm] Ron [ohm] / Ω R on_measure R on_model T j [oc] / C Fig. 4-8 Measured and modeled conduction resistance of the 15 kv SiC MOSFET module. Using the derived Q oss and R on models, we are now able to find the maximum power handling capability of the hybrid DC-DC converter based on the 15 kv SiC MOSFET/JBS 76

99 module by sweeping all possible designs using the flowchart in Fig. 4-9 with parameters listed in Table 4-1.For a fixed output power, MV voltage and switching frequency, there is always an optimized design that minimizes the losses and temperature of the 15 kv SiC MOSFET/JBS modules. A series of optimized designs are presented in Fig with V MV from 6 kv to 12 kv and switching frequency f s from 20 khz to 100 khz. Natural convection is used to cool the MV SiC module by placing the module on a heatsink without fan (see Fig. 4-7). Since L m and t d are well chosen such that ZVS can be secured, conduction loss dominates the total power loss of the MV SiC modules. For certain power level and V MV, higher switching frequency means larger portion of each switching period is used for ZVS and less effective time for power delivering, resulting in a higher conduction loss. To reach the same rated power, a higher V MV is necessary to reduce the current and thus the conduction loss. If a 12 kv V MV is used, 30 kw (at 100 khz) to 40 kw (at 20 khz) power can be delivered using the proposed topology with only two 15 kv SiC modules. If a better cooling system such as forced air or forced water is used, where the thermal resistance is much lower than 1.5 o C/W, higher power capability can be further obtained. The 6 kv 10 kw prototype with 40 khz switching frequency discussed below is also marked in Fig For the real prototype, dead time margin is applied to secure full ZVS of MV MOSFETs considering: 1) the parasitic capacitances of the transformer that are equivalently paralleled to the output capacitances of MV side MOSFETs; 2) extent the full ZVS voltage range and enlarge ZVS window to ensure higher system reliability. 77

100 Table 4-1 MV DC-DC Prototype Design Specifications Symbol Description Value Ts Switching period us VMV MV voltage 6-12 kv Lm Magnetizing inductor 3 70 mh td Dead time us Po Power rating kw Rthj-a Thermal resistance from junction to air, natural convection 1.5 o C/W Troom Room temperature 50 o C Converter Specifications V MV (i), P o (j), f s (k) L m (m), t d (n) Switching loss P sw base on Q oss (V MV ) Conduction loss P con (0)= 0.5I 2 r_rms R on (T j (0)= T room ) No T j (l)= (P sw P con (l-1))r th T room P con (l)= 0.5I 2 r_rms R on (T j (l) ) dt j =T j (l)-t j (l-1) dt j 0 No Yes Min (P sw P con ) Yes Save the design Fig kv SiC MOSFET module power loss and junction temperature calculation flow chart. 78

101 T room = 50 o C Junction Temperature vs Output Power V MV = 6 kv 20kHz V MV = 8 kv V MV = 10 kv V MV = 12 kv Jumction Temperature [oc] Prototype Design 100kHz 60kHz 80kHz 40kHz 20kHz 100kHz 80kHz 60kHz 40kHz 100kHz 60kHz 80kHz 20kHz 40kHz 100kHz 60kHz 40kHz 20kHz 80kHz Po [kw] Fig Minimum 15 kv SiC MOSFET junction temperature versus processed power with different switching frequency and V MV. Resonant Tank Design Switching frequency f s is chosen based on the semiconductors performance, overall system volume and efficiency requirements. As mentioned before, the resonant tank is then designed to have a resonant frequency f r approximately equal to f s. As can be seen from equation (4.9), larger L s leads to a i Ls with slower increasing rate. From impedance point of view, larger L s provides higher impedance for the converter during the DAB mode, which is helpful to limit i Ls. For a fix resonant frequency, large L s and small C r1, C r2 are preferred for better over-load protection. However, C r1 and C r2 should be large enough that their voltage ripple is smaller 79

102 than V LV /2 under normal load operation. Therefore, criteria (4.15) and (4.16) need to be met while designing the resonant tank. C PT o s C (4.15) 2V r1 r2 2 LV L s 2 2 T TV s s LV (4.16) C 4 P r1 o If a proper winding structure and core dimension are considered in the transformer design, the resonant inductor L s can be integrated into the transformer as its leakage inductor to further improve the power density. Table 4-2 MV DC-DC Prototype Components and Specifications Symbol Description Value fs Switching frequency 40 khz td Dead time 2 us VMV MV voltage 6 kv VLV LV voltage 400 V Core R type ferrite 2*EE100 LV winding 12 AWG 5*5*28/40 6 MV winding 16 AWG 5*32/38 1 n Transformer turns ratio 14.6 Lm Magnetizing Inductor 8.69 mh Ls Resonant Inductor 6.57 uh (leakage inductance) Cr1,Cr2 Resonant capacitor 1.15 uf Qr1, Qr2 LV side MOSFETs 1.2kV 100A SiC MOSFET CAS100H12AM1 D3, D4 Voltage clamping diode 600V 80A Fast Diode RURG8060_F085 80

103 4.4 Experimental Results With the 15 kv SiC MOSFET module, a 6 kv to 400 V, 10 kw isolated DC-DC converter prototype is constructed. Switching frequency is chosen to be 40 khz. Table 4-2 summarizes the key components and specifications. Fig shows the 6 kv to 400 V steady-state waveforms under 10 kw full-load condition. The resonant current is close to sinusoidal, for the converter operates at the resonant frequency with a duty ratio of Judging from the waveform of V ds_q2, ZVS is fully realized. Although the DC link voltage is high, the dv/dt is only 3.75 kv/us which is much lower than the hard switching dv/dt. This ensures low EMI noise and reduces the probability of any false trigger at the gate of Q 1 and Q 2. Waveforms given in Fig demonstrate that ZVS of Q 1 and Q 2 can still be secured under no load condition. Efficiency from 20% to 120% load condition are measured and provided in Fig The efficiency is greater than 97% over a wide load range. The peak efficiency is above 98%. A calculated loss breakdown is shown in Fig at 10 kw output power. Calculated total loss is 211.9W, showing a 16.9% difference compared to the measured 255 W power loss. The loss breakdown indicates the need to decrease LV side losses. This can be achieved by parallel additional LV side devices to reduce the conduction loss. The calculated MV MOSFET loss is only 6% of the total power loss. This implies that there is a large potential to increase the device utilization of the 15 kv SiC MOSFET modules by increasing the power level, input voltage or both. This is clearly shown in Fig

104 Time: 4us/div V ds_qr2 : 200V/div I Ls : 50A/div V ds_q2 : 2 kv/div Fig Experimental waveforms, V MV = 6 kv, P o = 10 kw. Time: 4us/div V ds_q2 : 5 kv/div V ds_qr2 : 200V/div I Tp : 2A/div I Ls : 5A/div Fig Experimental waveforms, V MV = 6 kv, P o = 0 W. 82

105 Efficiency 98.5% 98.0% 97.5% 97.0% 96.5% Po / kw Fig Measured prototype efficiency, V MV = 6 kv, P o from 2 to 12 kw; 7.2 W, Resonant Cap 13.3 W, MV MOS 83.6 W, Transformer W, LV MOS W Calculated Overall 10 kw Fig Converter loss break down, V MV = 6 kv, P o = 10 kw. 83

106 4.5 Conclusion In this paper, a novel isolated MV DC-DC converter was proposed by combining the resonant converter and DAB. Under normal load condition, it works as a pure resonant converter operating at its resonant frequency. So the soft switching and highest efficiency are achieved. When over-load happens or during the star-up process, the converter operates in resonant and DAB hybrid modes. Because of the resonant capacitors are bypassed by the paralleled diodes, the impedance of resonant tank is greatly increased and the transient current in the resonant tank is naturally limited. The full load range soft switching capability and cycleby-cycle over-load protection guarantees the ruggedness of the converter. Operation principle and design considerations were given for the proposed converter. A 6 kv, 40 khz prototype based on 15 kv SiC MOSFET modules was developed. Test waveforms at no load and 10 kw full load validated the zero to full load range soft switching capability. Measured efficiency is higher than 97% from light load to full load. The power handling capability of the 15 kv SiC MOSFET in the proposed soft switching DC-DC is also analyzed, indicating a large potential to improve the power level of the DC-DC converter to kw level without MV device parallel. The overall chip size of the MV SiC devices is less than 2 cm 2 hence overall system cost is minimized. 84

107 Chapter 5. Over-Load Protection and Soft-Start of the Proposed Medium-Voltage Medium- Frequency Isolated DC-DC Converter 5.1 Introduction The proposed series resonant converter by [34] had been successfully applied in medium voltage (MV) solid state transformer system. It provides galvanic isolation and steps down the medium voltage. It can also be adopted in future MV DC grid systems as a DC bus transformer. For both cases, high power conversion efficiency and high power density are considered as key performance indexes. To achieve the best efficiency, the resonant converter is designed to work around the resonant frequency, where the resonant tanks have very low impedance. Under steady state operation, there is a very low voltage differences (depending on the load and the power losses of the converter) across the resonant tank. When the converter starts up, however, the output voltage builds up from zero to the rated value. Before the output voltage reaches the rated value, large voltage differences across the resonant tank will lead to great current and voltage stress that might destroy the system. As summarized in Fig. 5-1, existing soft-start and over-load protection strategies for resonant converter can be classified into three categories resonant capacitors voltage clamping, linear control, non-linear control. Voltage clamping methods were adopted in [33][57][59]. By clamping the voltage across the resonant capacitor either to the input or to the output voltage, the impedance of the resonant tank can be 85

108 automatically increased, which effectively limits the resonant current. Linear control methods [60][61] improve the transient response of the converter, but need high bandwidth and accurate current sensing [62] to realize fast enough current control. Soft start-up can also be effectively realized by non-linear control [53], [63][64][65][66]. In [34], a series resonant converter with split resonance capacitors that can be clamped to the output voltage can intrinsically limit the resonant current when over-load happens or during the start-up process. Together with non-linear control methods given in this chapter, it can further limit the resonant tank current to be below the desired level. Soft-Start / Over-load Protection Strategies for Resonant Converter Resonant Capacitance Voltage Clamping Clamp to Input Voltage Clamp to Output Voltage Voltage Clamping Nonlinear Control Constant Frequency Variable Duty Proposed Variable Frequency Variable Duty Cycle Control Linear Control Average Current Control Charge Control Nonlinear Control PWM / Phase / Frequency Control Trajectory Control Fig. 5-1 Current limiting strategies for resonant converters during start-up or over-load operation. 86

109 5.2 Constant Frequency Variable Duty Cycle (CFVD) Control for Over- Load Protection and Soft-Start In the proposed converter, if the load is heavier than R Crit, the converter will automatically enter resonant and DAB mixed operation. When the voltages across the resonant capacitors are clamped to 0 or V LV by their paralleled diode, C r1 and C r2 are bypassed. This naturally transfers the resonant converter into a DAB converter. The impedance of the converter dramatically increases from near zero to jω r L s, which is quite helpful in limiting i Ls under over-load condition. This improvement, from the circuit perspective, limits the over-load transient current. Control approaches to limit the transient current are further considered. As shown in Fig. 5-2, with fixed switching frequency, the duty cycle is predicted according to the output voltage V LV based on the peak resonant current model or average output current model of the converter, such that the correspond current can be controlled. Q 1 V MV C dc1 n:1 L s Q r1 C r1 D 3 V LV L m C LV_dc - C dc2 Q 2 Q r2 C r2 D 4 - V gsq1 V gsq2 D Driver Predictive Controller ADC V LV Fig. 5-2 Proposed constant frequency variable duty cycle (CFVD) control for resonant current limiting. 87

110 Variable Duty Cycle for Current Limiting When over-load operation is triggered, the duty cycle of Q 1 and Q 2 can be decreased to limit the the peak value of i Ls. From the former analysis, it is easy to find out that the peak value of i Ls appears within t 0 -t 2 interval. If V LV is lower than V MV /2n, i Ls increases before and after the resonant capacitors are being clamped. It reaches the maximum value at the end of the on-time of the corresponding active switch. If V LV is higher than V MV /2n and the duty cycle is smaller than 0.25, the resonant capacitors will not be clamped; i Ls keeps increasing to the peak value until Q 1 or Q 2 turns off. If V LV is higher than V MV /2n and the duty cycle is larger than 0.25, i Ls will decrease after resonant to the peak current point at t 0 T r /4, as shown in Fig. 4-6(b). From the aforementioned cases, the peak current through L s can be expressed as (5.1): I pk V MV 2nZ r I if V V 2 n, Ls _ t 2 LV MV V MV 2nZ V MV r 2nZ r sin( DT ) if V V 2 n, DT sin( DT ) if V V 2n, D 0.25 OW.. r r LV MV s DT r r LV s t 1 MV t 1 (5.1) where, the switching period T s = T r 2t d. The plots of (5.1), using the parameters in Table 5-1 are shown in Fig. 5-3 and Fig Fig. 5-3 shows I pk versus V LV and duty cycle in a 3D plot where V MV equals to 6 kv. Fig. 5-4 gives the relationship between I pk and the duty cycle with V LV from 0-200V and V MV equals to 3 kv. It can be seen that, I pk increases with a decreasing V LV and reaches the maximum when V LV is zero. When the duty cycle is samller than 0.25, a smaller duty cycle leads to a 88

111 lower I pk. The worst case for I pk is when short circuit happens and the duty cycle is 0.5. Fig. 5-3 and Fig. 5-4 give the models that can be used for predictive peak resonant current control shown in Fig V LV is sensed to be the input of the predictive controller. Based on the predefined target function I pk (V LV ), the duty cycle can then be found as the output of the controller. Take V MV =3 kv as an example, if a current limit of 38 A is needed when V LV = 0, a corresponding duty cycle 0.1 can be found using Fig Notice when V LV V MV /2n, the peak current is intrinsically limited to V MV /2nZ r by the converter without resorting to duty cycle control. Table 5-1 Peak Current Calculation Specifications Symbol Quantity Value fs Switching frequency 40 khz VMV MV voltage 6 kv / 3 kv VLV LV voltage V Ls Resonant Inductor 6.57 uh Cr1,Cr2 Resonant capacitor 1.15 uf n Transformer turns ratio

112 I pk / A D Fig. 5-3 Peak resonant current versus duty-cycle and V LV (V MV = 6 kv) I pk / A I pk (V LV =0)=38A -> D=0.1 D D Fig. 5-4 V LV versus peak resonant current (V MV = 3 kv) 90

113 Experimental Results using CFVD Control Short circuit is the worst case of over-load scenarios. Fig. 5-5 shows the waveforms when short circuit happens at t OCP. The decreasing of V LV triggers the over-load protection, duty ratio decreases from 0.42 to 0.1 based on the proposed predictive duty cycle control. Short circuit protection is realized within one switching period (25 us). The zoom in of Fig. 5-5 is shown in Fig It can be seen that i Ls is well controlled to be below 40 A when V LV equals to zero. According to Fig. 5-6, there are resonances between the parasitic inductance and capacitances of the transformer and semiconductor devices when Q 1 and Q 2 are both turned off. This causes the starting point of i Ls to be 4 A instead of 0 A at t 0. In the former analysis, the resonance was ignored in order to simplify the theoretical calculation. Thus the resonant current i Ls has a higher maximum value than the calculated value given in Fig Other than this, the experimental results agree with the previous analysis. 91

114 Time: 100us/div V gs_q2 : 20V/div V LV : 200V/div I Ls : 50A/div V ds_q2 : 2 kv/div t OCP Fig. 5-5 Experimental short circuit protection waveforms, V MV = 3 kv. V gs_q2 : 20V/div Time: 10us/div V LV : 200V/div I Ls : 50A/div I Ls_t0 V ds_q2 : 2 kv/div t 0- t 0 Fig. 5-6 Experimental short circuit protection waveforms, V MV = 3 kv, V LV = 0 V. 92

115 Incomplete-ZVS Using CFVD Control The constant frequency variable duty cycle control discussed above provides an effective way to protect the converter. Under normal load operation, the resonant converter is designed to have on-time equal to half of the resonant period to achieve the best efficiency. Thus, the resonant current at the MV side - ILp equals to the magnetizing current - ILm at the turn-off moment. Here, Lp is the equivalent resonant inductor at the MV side of the transformer (Lp = n 2 Ls). Magnetizing current ILm helps with realizing complete ZVS of Q1 and Q2 during the offtime. During the start-up process or when over-load happens, switching period is fixed, to maintain fixed switching frequency. On-time ton of the active switches varies with the duty cycle. ILp does not equal to ILm at the turn off moment. Soft switching of Q1 and Q2 is quite different from normal load operation. The off period is worth of being studied. Mode t2-t3 : As shown in Fig. 5-7, Q1 is turned off at t2, with ILp much higher than ILm. Output capacitor of Q1 will be discharged. Vds_Q2 drops dramatically and reaches zero at t3. This interval is much shorter than the one of normal load operation where the output capacitors are charged or discharged by ILm. Mode t3-t4 : The anti-paralleled diode of Q2 starts conducting from t3 as shown in Fig According to the equivalent circuit in Fig. 5-8(a), ILp keeps decreasing and reaches ILm at t4. Mode t4-t5 : 93

116 Qr1 and Qr2 s equivalent output capacitors at the MV side are so small compared with those of Q1 and Q2 that their switching transient can be ignored. Equivalent circuit of t4-t5 is given by Fig. 5-8(b). The voltage across Lp within this interval is -VMV/2nVCr2. Before t4, Cr2 is clamped by its paralleled diode, hence, the voltage across Cr2 is approximately to zero during this interval. The voltage across Lp is thus around -VMV/2n, which forces ILp continue decreasing and reaches 0 at t5. Mode t5-t6 : After ILp decreases to 0, the current through Q2 starts changing its direction. Equivalent circuit can be found in Fig. 5-8(c). With much greater capacitance than Coss, Cr1 and Cr2 can be considered as voltage sources. Similarly, Lm is much larger than Lp, thus, can be treated as an open circuit. The resonant frequency is dominated by the output capacitors of Q1, Q2 and Lp. Q2 is turned on at t6, where the drain to source voltage Vds_Q2 is greater than zero. Complete ZVS is lost at this operation points. Fig. 5-6 presents the tested short-circuit waveforms of the series resonant DC-DC converter at 3 kv using the CFVD control [34]. With a 0.1 duty cycle, the resonant current is limited to be below 40 A during the short-circuit operation. After Q1 turns off, ILs starts decreasing and reaches zero at ton-. After ton-, output capacitors start resonant with the inductors in the circuit. In order to keep the switching frequency fixed at 40 khz, Q2 is not turned on until ton, where its drain to source voltage becomes positive again. Full ZVS is lost. If the switching frequency can be adjusted accordingly, such that Q2 is turned on before ton-, ZVS can be maintained. Thus, a VFVD control to realize current limiting and full ZVS is introduced. 94

117 t on t off V gsq1 V gsq2 V gsq1 ` V ds_q2 I Lp I Lm V Cr1 t 3 t 0 t 1 t 2 t 4 t 5 t 6 V Cr2 t Fig. 5-7 Key waveforms of the proposed DC-DC converter during startup process. V MV - C dc1 Q 1 C dc2 Q 2 v tp - L p L m n:1 Q r1 Q r2 C r1 C r2 D 3 C LV_dc D 4 V LV - V MV/2 L p nv LV (a) t 3-t 4 V MV - C dc1 Q 1 C dc2 Q 2 v tp - L p L m n:1 Q r1 Q r2 C r1 C r2 D 3 C LV_dc V LV V MV/2 L C r2/n 2 m D 4 - L p C r1/n 2 nv LV (b) t 4-t 5 V MV - C dc1 Q 1 C dc2 Q 2 v tp - L p L m n:1 Q r1 Q r2 C r1 C r2 D 3 C LV_dc D 4 V LV - V MV/2 V MV/2 nv Cr2 L p C oss1 C oss2 v ds1 v ds2 (c) t 5-t 6 Fig. 5-8 Operation modes and equivalent circuits during switching intervals using CFVD control. 95

118 5.3 Variable Frequency Variable Duty Cycle (VFVD) Start-up ZVS may be lost at some operation points using the CFVD control. Due to the significant amount of energy stored in their output capacitances, SiC MOSFETs switching at 40 khz under 6 kv without ZVS will result in large thermal stress on the device or cause premature failure due to high dv/dt. In order to realize full ZVS and keep the resonant current limited under any load condition, this chapter proposes an improved variable frequency variable duty cycle (VFVD) control scheme. Q 1 V MV C dc1 L p L m n:1 Q r1 C r1 D 3 C LV_dc V LV - C dc2 Q 2 Q r2 C r2 D 4 - V gsq1 V gsq2 Driver f s D Predictive Controller ADC V LV Fig. 5-9 Predictive variable frequency variable duty cycle (VFVD) control. As shown in Fig. 5-9, by measuring the output voltage VLV, variable frequency and variable duty cycle control is proposed. By using this control scheme, adaptive on-time keeps the resonant tank current under limit; meanwhile, variable off-time secures the ZVS of Q1 and Q2. With VLV building up from 0 to VMV/n, the starting up process can be divided into four stages 96

119 S1 to S4, as presented in Fig States trajectories of Lp and Cr1 for all these four stages are given by Fig. 5-11, Fig. 5-12, Fig and Fig ID denotes the resonant current at point D on the states planes; IM denotes the magnetizing current ilm during the ZVS process (C-D or B-D). Since Lm is much larger than Lp, IM can be considered as constant during the ZVS interval. At stage S1 and S2, relatively low VLV and short on-time lead to very small voltsecond across Lm. As a result, IM is close to zero. Therefore, it is neglected in corresponding trajectories shown in Fig and Fig nv LV V MV V MV /2 0 S 1 S 2 S 3 S 4 nv LV < V MV /2 nv LV V MV /2 I D >I M I D <I M t t on t off Fig Four stages of the soft-start process. 97

120 Z p i Lp C Mode 1 t on O 2 A nv LV -V MV /2 Mode 2 B 0 r 1 ZVS D t off Mode 3 r 1 E O 1 nv LV V MV /2 nv Cr1 Fig Stage S 1 - resonant tank state-trajectory. Z p i Lp t on Mode 1 B ZVS A 0 r 1 O 2 nvlv -V MV /2 O 1 V MV /2 D t off Mode 3 E nv nv Cr1 LV r 1 Fig Stage S 2 - resonant tank state-trajectory. 98

121 Z p i Lp Mode 1 t on A 0 r 2 nv LV -V MV /2 O 2 O 1 V MV /2 r 2 B M D E ZVS t off nv Cr1 nv LV Fig Stage S 3 - resonant tank state-trajectory. Z p i Lp Mode 1 t on 0 A r 3 nv LV -V MV /2 O 2 O 1 V MV /2 r 3 ZVS M D E t off nv Cr1 Fig Stage S 4 - resonant tank state-trajectory. 99

122 Variable On-time for Current Limiting During the start-up process, the voltage of Cr1 is always clamped to zero before Q1 s turning on. After Q1 is turned on at point A, Cr1, Cr2 resonant with Lp till vcr1 is clamped to VLV by the paralleled diode at the end of Mode 1 (point B) as shown in Fig to Fig The equivalent circuit of Mode 1 is given by Fig. 5-15(a). The resonant current at point B is I B 2 2 V ( V 2 nv ) MV MV LV (5.2) 2Z p where, Z p L p 2 C C n r1 r 2. From point A to point B, the time interval can be expressed as: t AB 2nVLV arccos(1 ) VMV r (5.3) When nvlv is lower than VMV/2 as shown in Fig After point B, the resonant capacitors are bypassed by D4. As shown in Fig. 5-15(b), the voltage across Lp (VMV/2-nVLV) is positive. ILp continues rising up. In order to keep ilp under Ip_pk, Q1 has to be turned off at point C. The duration of Mode 2 is t BC I V MV p _ pk I B 2 nv LV L p (5.4) If nvlv is higher than VMV/2 as shown in Fig. 4 (b). After point B, if Q1 is kept on, the voltage across Lp (VMV/2- n VLV ) will be negative. ilp will not increase anymore. Peak resonant current (5.5) is reached when θ equals to π/2, which is before the trajectory reaches point B. 100

123 I VMV I ' (5.5) 2Z C p _ pk p To simplify the calculation, Mode 2 is eliminated when nvlv is higher than VMV/2. Q1 is turned off at point B. On-time is therefor: tab tbc, nvlv VMV 2 ton tab, VMV nvlv VMV 2 tam, nvlv VMV (5.6) V MV - C dc1 Q 1 C dc2 Q 2 v tp - L p L m n:1 Q r1 Q r2 C r1 C r2 (a) Mode 1 D 3 C LV_dc D 4 V LV - V MV /2 L p C r1 /n 2 C r2/n 2 nv LV V MV - C dc1 Q 1 C dc2 Q 2 v tp - L p L m n:1 Q r1 Q r2 C r1 C r2 (b) Mode 2 D 3 C LV_dc D 4 V LV - V MV /2 L p nv LV Fig Equivalent circuits for the turn-on period of Q

124 V MV - C dc1 Q 1 C dc2 Q 2 v tp - L p L m n:1 Q r1 Q r2 C r1 C r2 (a) Mode 3 D 3 C LV_dc D 4 V LV - V MV /2 L p nv LV V MV - C dc1 Q 1 C dc2 Q 2 v tp - L p L m n:1 Q r1 Q r2 C r1 C r2 D 3 (b) Mode 4 C LV_dc V LV V C r2 /n 2 MV /2 L m D 4 C r1/n 2 - L p nv LV Fig Equivalent circuits for the turn-off period of Q 1. Variable Off-time for ZVS After Q1 is turned off, ilp charges and discharges the output capacitors of Q1 and Q2 respectively. The drain to source voltage of Q1 vds1 rises up from zero to VMV, while Q2 s drain to source voltage vds2 decreases from VMV to zero. Trajectories of this process - C-D (in Fig. 5-11) or B-D (in Fig. 5-12, Fig. 5-13, and Fig. 5-14) are marked as ZVS and will be discussed in detail later on. In the state-trajectories, vds2 reaches zero at point D. Ignoring the threshold voltage, Q2 s anti-paralleled diode starts carrying the current. At stage S1 and S2, the resonant current at the turn-off moment (at point B when nvlv>vmv/2, or at point C when nvlv<vmv/2) is very high. After fully discharging Q2 s output capacitor at point D, the 102

125 resonant tank current - ID is higher than the magnetizing current at the moment. Equivalent circuit is given by Fig. 5-17(a), where Qr1 at the secondary side carries the current. According to Fig. 5-16(a), voltage across Lp is now -(VMV/2 nvlv), forcing ilp decreasing in Mode 3. When VLV is getting closer or equal to its rated voltage, ilp at the turn-off moment becomes lower, so is the remaining ZVS current - ID at stages S3 and S4, Since ID is now lower than the magnetizing current, Qr2 at the secondary side conducts. Equivalent circuit given in Fig. 5-16(b), shows that Lp starts resonating with Cr1 and Cr2 again in Mode 4. ilp reaches zero at point E and goes negative afterward. Complete ZVS can be achieved by turn on Q2 between point D and E on the states-planes. In order to have the narrowest switching frequency range, Q2 is chosen to be turned on at point E. The turn-off time can be given by: ID TZVS Lp, ID IM VMV 2 nvlv toff TZVS tde I T L, I I D ZVS p D M VMV 2 nvcr2_ B (5.7) In (5.7), TZVS, ID and IM will be given in the next section. At stages S3 and S4, off-time becomes very short that vcr2 from point B to E can be considered as constant. Before the output voltage reaches VMV/n, vcr2 is clamped to zero by D4 (ignoring the forward voltage drop of D4) at point D. When VLV equals to VMV/n, Cr1 and Cr2 will not be bypassed anymore, vcr2 at point D is related to the load current Io. All in all, vcr2_d can be written as: v Cr 2_ D VMV 0, VLV n V 2 Z I V, VLV 2n n MV p o MV (5.8) 103

126 V MV - C dc1 Q 1 C dc2 Q 2 Q C r1 D 3 L r1 p n:1 V LV V MV /2 v tp L m vts C LV_dc - - V MV /2 Q r2 C r2 D 4 - nv LV L p C oss1 C oss2 v ds1 v ds2 (a) ZVS : i Lp > i Lm V MV - C dc1 Q 1 C dc2 Q 2 - v tp L p L m n:1 vts - Q r1 Q r2 C r1 C r2 D 3 C LV_dc D 4 V LV - V MV /2 V MV /2 L m L p C oss1 C oss2 v ds1 v ds2 (b) ZVS : i Lp = i Lm V MV - C dc1 Q 1 C dc2 Q 2 Q L r1 C r1 D 3 p n:1 V LV V MV /2 v tp L m vts C LV_dc - - Q r2 C r2 D 4 - V MV /2 nv Cr2_D L p C oss1 C oss2 v ds1 v ds2 (c) ZVS : 0 < i Lp < i Lm Fig Operation modes and equivalent circuits during ZVS process. 5.4 ZVS Considerations According to chapter 3, state-trajectory ZVS analysis method has been proved to be effective and accurate. In chapter 2, the output charge of 15 kv SiC MOSFETs have been tested up to 6 kv with less than 1% error. To conduct state-trajectory ZVS analysis on this series resonant circuit, the charge equivalent output capacitors - C oss1 and C oss2 are used in the 104

127 equivalent circuits shown in Fig For the ZVS of Q 2, there are basically three scenarios: 1) When i Lp is greater than the magnetizing current i Lm, equivalent circuit is shown in Fig. 5-17(a), where Q r1 and D 4 are conducting current. 2) If i Lp equals to i Lm, no current flows in the transformer s secondary winding, the equivalent circuit is given by Fig. 5-17(b). 3) When i Lp is greater than zero but less than i Lm, it continues discharging C oss2 and charging C oss1. As shown in Fig. 5-17(c), Q r2 carries the current at the secondary side of the transformer. At different start-up stage, the ZVS process consists of one or several of the abovementioned scenarios depending on the relationship between I D and I M. I M is defined as the magnetizing current i Lm during the ZVS process. At stages S 1 and S 2, compared with the large I D, I M can be neglected. With the increasing of V LV, at stages S 3 and S 4, the resonant current at point B gets lower. After charging and discharging the output capacitors of Q 1 and Q 2, the resonant current at the end of the ZVS process - point D gets closer to I M. On this occasion, the switching period is very close to the resonant period, I M can therefore be approximated as: I M VMVT 8L r (5.9) m ZVS process at stage S 1 and S 2 At stage S 1, state-trajectories of the ZVS process marked in Fig is shown by Fig When Q 1 is turned off at point C, the resonant current is at the highest level I C. While v ds2 drops from V MV to zero, the resonant current is kept higher than I M. According to the equivalent circuit given in Fig. 5-17(a), the centers of the state-trajectories in Fig are 105

128 (V MV /2-nV LV, 0) and (V MV /2nV LV, 0). Initial voltage and current of C oss1, C oss2 and L p are 0, V MV and I C respectively. The trajectories radius can be obtained using (5.10). VMV r nv I Z 2 s LV C o 2 2 (5.10) where, Z o C L p C oss1 oss1. The ZVS process ended when v ds2 decreases to zero while v ds1 increases to V MV. The duration of this process can be calculated by: T ZVS o (5.11) where, o 1 L C C p oss1 oss1 ; VMV VMV nvlv nvlv acos 2 acos 2. rs rs The remaining current at the end of the ZVS process can be also get according to the stateplane: I D r 2 s VMV 2 Z o nv LV 2 (5.12) ZVS process state-trajectories at stage S 2 are given in Fig They are similar to the ones at stage S 1. The only difference is the initial current of L p is now I B instead of I C. The radius of the trajectories becomes: 106

129 VMV r nv I Z 2 s LV B o 2 2 (5.13) T ZVS and I D can then be calculated using (5.11) and (5.12). S 2 ends when I D equals to I M. Z o i Lp Z o I C Z o I D v ds1 v ds2 r s α γ β 0 V MV v ds V MV /2-nV LV V MV /2nV LV Fig Stage S1 - ZVS state-trajectories. 107

130 Z o i Lp Z o I B v ds1 v ds2 Z o I D Z o I M r s α γ β V MV /2-nV LV 0 V MV V MV /2nV LV v ds Fig Stage S2 - ZVS state-trajectories. ZVS process at stage S3 With V LV keeps increasing, the resonant current at the beginning of the ZVS process gets closer to I M. After C oss2 is completely discharged, the remaining resonant current I D at stage S 3 becomes lower than I M. Based on state-planes in Fig and Fig. 5-21, when i Lp equals to I M, v ds1 can be derived as: 2 V V r Z I nv 2 2 MV M1 s o M LV (5.14) At the same time, the drain to source voltage of Q r2 is given by (5.15). v V 2 MV V M 1 v ds _ Qr 2 Cr 2_ D n (5.15) According to (5.8), v Cr2_D at stage S 3 is zero. When V M1 is higher than V MV /2, V ds_qr2 is negative. Ignoring Q r1 and Q r2 s output capacitors, Q r2 s anti-paralleled diode starts 108

131 conducting. Equivalent circuit is presented in Fig. 5-17(c). The trajectories now both have centers at (V MV /2, 0). Radius r s1 is obtained using: V r V Z I 2 MV s1 M 1 o M 2 2 (5.16) The ZVS duration can then written as: T ZVS (5.17) o where, ZoI B ZoI M asin asin rs rs ZoI M V MV asin acos r 2 r s1 s1 (5.18) (5.19) At the end of the ZVS process, the resonant current becomes: I D r 2 s1 V 2 Z o MV (5.20) 109

132 Z o i Lp Z o I B v ds1 v ds2 Z o I M V M2 V M1 r s α γ V MV /2-nV LV Z o I D β r s1 σ λ 0 V M2 V MV /2 V M1 V MV V MV /2nV LV v ds Fig Stage S3 - ZVS state-trajectories, V M1 >V MV /2. If V M1 is lower than the V MV /2, v ds_qr2 is positive at the moment when i Lp equals to I M. In this case, magnetizing current continues charging C oss1 and discharging C oss2, till v ds1 rises up to V MV /2. Equivalent circuit is given in Fig. 5-17(b). Much greater than L p, L m can be consider as a current source. Thus, i Lp is merely constant on state-plane shown in Fig After v ds1 gets higher than V MV /2, Q r2 starts carrying current. L m is therefore bypassed by the resonant capacitors C r1 and C r2 as shown in Fig. 5-17(c). According to the state-plane, the trajectories now have radius as: r s2 ZoIM (5.21) The ZVS process consists all the three scenarios given by Fig The transient time can be estimated by: T ZVS V V C C 2 I o MV M 1 oss1 oss2 M (5.22) 110

133 where, V MV a sin 2 rs 2 (5.23) When the ZVS transient is complete, the resonant current can be get by: I D r 2 s2 V 2 Z o MV 2 (5.24) Z o i Lp Z o I B v ds1 v ds2 Z o I M α γ β Z o I D r s2 σ λ r s V MV /2-nV LV 0 V M1 V MV /2 V M2 V MV V MV /2nV LV v ds Fig Stage S3 - ZVS state-trajectories, V M1 <V MV /2. ZVS process at stage S 4 At the end of the soft-start, the output voltage reaches its rated level. Switching frequency is around the resonant frequency to achieve the best efficiency. In this case, the on-time is about half of the resonant period. The resonant current at the turn off moment equals to I M. Magnetizing current charges C oss1 and discharges C oss2 as shown in Fig. 5-17(b). This 111

134 operation mode ends when v ds1 reaches V MV /2, and Q r2 s body diode start conducting current. Equivalent circuit is given by Fig. 5-17(c), in which, v Cr2_D (5.8) is load dependent. Based on the state-trajectories presented in Fig Duration of the ZVS process is estimated as: T ZVS V 2 o MV nv C C I Cr 2_ D oss1 oss2 M (5.25) where, VMV nvcr 2_ D asin 2 rs 2 (5.26) Based on the state-plane in Fig. 5-22, at the end of the ZVS process, the resonant current is: I D r V nv 2 Z 2 MV s2 Cr 2_ D o 2 (5.27) Z o i Lp Z o I M Z o I D v ds1 v ds2 r s2 σ λ 0 V MV /2 V MV v ds V MV /2-nv Cr2_D V MV /2nv Cr2_D Fig Stage S4 - ZVS state-trajectories. 112

135 5.5 VFVD Control Implementation As discussed in the former sections, in VFVD control, the current limiting is realized by the variable on-time of the switches and the ZVS is ensured by the variable off-time. Using the parameters shown in Table 5-2, ton and toff for constant peak resonant current control can be plotted in Fig Based on the state-trajectories in Fig to Fig. 5-14, soft-switching can be secured as long as the turn on moment is after point D and before point E. In this research work, turn-on moment is chosen to be at point E to reach narrowest switching range. In a real application, a ZVS window margin is needed to compensate the circuit and model mismatch. Thus, the turn-on moment should be ahead of point D by t. Thus, the off-time is shortened by t; the on-time is therefore increased by t; overall switching period stays the same. Switching frequency and duty cycle are then given in Fig (solid line) and Fig The switching frequency is in the range of khz. The duty cycle is from A lookup table can be compiled based on the calculated duty cycle and switching frequency. It can then be simply implemented by a digital controller as shown in Fig It is worth noting that the switching frequency and duty cycle are loaded into the digital controller s corresponding shadow registers instead of immediate affect the PWM generator. This ensures the proper PWM generation. But it also brings in control delay up to a switching period. However, this delay is acceptable since the semiconductor devices as well as the transformer have large enough thermal capacitance to keep themselves from being overheated by a single current pulse. 113

136 Table 5-2 Series Resonant Converter Specifications Quantity Value VMV MV voltage 3k / 6k V VLV LV voltage V Lm Magnetizing Inductor 9.85 mh Lp Resonant Inductor mh Cr1,Cr2 Resonant capacitor 1.15 uf n Transformer turns ratio 15 Fig On-time, off-time and half of switching period versus V LV /V LV_R (normalized V LV ) using VFVD control 114

137 Fig Switching frequency versus V LV /V LV_R (normalized V LV ) using VFVD control. Fig Duty cycle versus V LV /V LV_R (normalized V LV ) using VFVD control. 115

138 Start Initial System ADC Get V LV Lookup D(V LV ) Lookup fs(v LV ) Load D, fs to EPWM Shadow Register Gate Driving Fig Implementation flow chart of VFVD soft-start. 5.6 Experimental Verification A 6 kv 400 V DC-DC converter is built and tested at 2.9 kv to verify the proposed VFVD control. Specifications are listed in Table 5-2. TMS320F28377D is chosen as the digital controller. Fig shows the key waveforms of the converter s soft-start. The resonant tank current - ILp is well controlled to be below 4.5 A during the whole starting up process. The peak current for full load operation is 3 A. Within the starting up process, the voltages across the resonant capacitor Cr1 is clamped either to zero or to VLV, thus VCr1 s upper envelope represents instantaneous VLV. According to the waveform of VCr1, it is obvious that VLV rises 116

139 up from 0 V towards the rated voltage. After VLV reaches VLV_R, the voltage across the resonant capacitors are no longer clamped by their paralleled diodes to zero or to VLV. Therefore, VCr1 s peak value becomes lower than VLV_R, while its lower envelope becomes higher than zero. Fig. 5-28, Fig. 5-29, Fig. 5-30, and Fig are the zoomed in waveforms of the starting-up process. It can be seen that ZVS is secured for both Q1 and Q2 during all the starting up stages S1 to S4. V gs_q2 : 50V/div t: 2ms/div I Lp : 5A/div I Lp_pk V ds_q2 : 2kV/div V Cr1 : 100V/div V LV_R V LV /V LV_R =1 Fig Starting up experimental waveforms using VFVD control. 117

140 V gs_q2 : 50V/div t: 4us/div i Lp_on I Lp : 5A/div i Lp_off V ds_q2 : 2kV/div V Cr1 : 50V/div Turn on Q 2 Turn off Q 2 Fig Zoomed in startup experimental waveforms using VFVD control at stage S1. V gs_q2 : 50V/div t: 2us/div I Lp : 5A/div i Lp_on i Lp_off V ds_q2 : 2kV/div V Cr1 : 100V/div Turn off Q 2 Turn on Q 2 Fig Zoomed in startup experimental waveforms using VFVD control at stage S2. 118

141 V gs_q2 : 50V/div t: 4us/div i Lp_on I Lp : 2A/div i Lp_off V ds_q2 : 2kV/div V Cr1 : 100V/div Turn on Q 2 Turn off Q 2 Fig Zoomed in startup experimental waveforms using VFVD control at stage S3. V gs_q2 : 50V/div t: 10us/div i Lp_on I Lp : 2A/div i Lp_off V ds_q2 : 2kV/div Turn on Q 2 Turn off Q 2 V Cr1 : 100V/div Fig Zoomed in startup experimental waveforms using VFVD control at stage S4. 119

142 5.7 Conclusion In this chapter, two over-load protection and soft-start control schemes - constant frequency variable duty cycle (CFVD) and variable frequency variable duty cycle (VFVD) are proposed to achieve over-load protection, and soft-start of the resonant and DAB hybrid converter. Short circuit protection test results demonstrated a 25 us (one switching period) over-load protection speed using CFVD control. A variable frequency variable duty cycle control scheme (VFVD) that can be simply implemented in a digital controller with off-line lookup table was then proposed. Only output voltage sensing is needed. Under all load conditions, it not only provides cycle-by-cycle current limiting but secures full ZVS as well. High voltage SiC MOSFET modules are now able to operate at medium frequency without concer of being overheated by the significant amount of hard switching losses. Based on the state trajectory analysis, the VFVD control that realizes peak resonant current limiting and full ZVS was derived. Smooth soft-start at 2.9 kv verified the fast current limiting and soft switching capabilities. Theoretical analysis matches the experimental results. 120

143 Chapter 6. Multi-Objective Optimization of Medium Voltage SiC DC-DC Converter Based on Modular Input-Series-Output-Parallel (ISOP) Architecture 6.1 Introduction Targeting at replacing traditional bulky line frequency (50 Hz or 60 Hz) transformer, the solid state transformer (SST) is a key enabling technology for smart grid [7]. By stepping down the MVDC to LVDC with galvanic isolation, the MV isolated DC-DC converter is a critical part of a typical SST with three power conversion stages. It can also interface mediumto low-voltage networks as a DC transformer in future MVDC power distribution systems. Because of the limited voltage capability of commercially available semiconductor devices, low voltage isolated DC-DC converters connected in a ISOP configuration is a very popular approach to achieve higher input voltage [67][68]. Modular multilevel converter (MMC) and neutral point clamping topologies [69][70] have also been proposed to achieve higher input voltage. A string of series connected low voltage devices is another approach capable of supporting high voltage. In this case, the key challenges are the static and dynamic voltage sharing among the devices [24]. 121

144 In recently years, SiC MOSFETs have demonstrated superior performance over silicon power devices, enabling higher power density and efficiency in power electronics converters [69]. The voltage range can also significantly increase to beyond 10 kv. Based on 15 kv SiC MOSFETs, a 6 kv V DC-DC converter operating at 40 khz has successfully demonstrated the ultra-high voltage and fast switching capability of SiC MOSFETs [34]. The converter in [34] can be used as a building block in an ISOP architecture to reach even higher input voltages. On the other hand, lower voltage modular DC-DC converters can also be used to reach the 6 kv input voltage using the ISOP. Therefore, a comprehensive comparison of a single-cell DC-DC converter using ultra high voltage SiC MOSFET versus multi-cells using low voltage SiC MOSFET is meaningful. Multi-objective system optimization that takes into account the power density, efficiency and cost is necessary to reach a useful conclusion [71]. 6.2 System Specifications A 12 kv to 400 V isolated DC-DC converter is needed for a 7.2 kv AC to 280 V AC SST system. To reach the 12 kv voltage level, one solution is to build a single DC-DC converter using lately developed 15 kv SiC MOSFET. Another option is to use several lower voltage modular DC-DC converters in series at the input to support the 12 kv input voltage, as shown in Fig

145 C dc1 Q 1 n:1 L s Q r1 C r1 D 3 V LV V MV V 1 L m - C dc2 Q 2 DC-DC (1) Q r2 C r2 D 4 - V 2 DC-DC (2) - V N DC-DC (N) Fig. 6-1 Input series output parallel (ISOP) medium voltage series resonant DC-DC Converter. In Fig. 6-1, there are N cells of identical DC-DC converters connected using ISOP architecture. Each module is a series resonant converter with split resonant capacitors Cr1 and Cr2. Running at the resonant frequency of its resonant tank, both zero voltage switching (ZVS) for Q1, Q2 and zero current switching (ZCS) for Qr1, Qr2 are realized. It maintains the highest efficiency of series resonant converter at normal load condition. In the meantime, D3 and D4 are designed to bypass the resonant capacitors when over load happens. By doing so, resonant current can be limited by Ls when over load happen. Reliability is then greatly improved compare with traditional series resonant converter. Detailed analysis was given by [34]. Operating at the resonant frequency, the voltage ratio of each module is determined by the transformer turns ratio n, as shown in (6.1). 123

146 V V V 1 2 N n V V V (6.1) LV LV LV All modules share the same output voltage VLV. Ignoring the transformers variations, (6.2) can be obtained using Kirchhoff s Voltage Law. Input voltage sharing is achieved by having uniform transformers turns ratio. While input current sharing between the modules are automatically secured by their series connection at MV side. Current sharing at low voltage side will then be realized by transformers that having the same magnetizing inductances. Both the turn s ratio and magnetizing inductance mismatch of the transformers can be well controlled in transformer fabrication process. Voltage and current sharing between the cells can therefore be controlled to an acceptable level. With intrinsic voltage clamping and current sharing capability, for the given 12 kv input voltage, either a few cells of ISOP converters with low-voltage semiconductor devices or a single-cell DC-DC converter using 15 kv SiC MOSFETs can be used. V V V V N nv (6.2) MV 1 2 N LV where, N is the number of cells. 6.3 MOSFET Models The cells number is a crucial parameter in the above proposed medium voltage ISOP converter system. Voltage and power rating of the semiconductor devices, magnetic components, capacitors vary with the cells number. To obtain the optimized number of cells, components models with wide voltage range are required, especially for the already complicated semiconductor devices. 124

147 Conduction Resistance Model Mathematical Ron model for SiC MOSFET is derived in (6.3): k t Tj R (BV, A, T ) R (BV, A ) on a j 0 a T0 (6.3) In (6.3), BV is the breakdown voltage of MOSFET, which is chosen to be 1.2 times of the voltage stress; Aa is the active chip area of a semiconductor device; Tj is the junction temperature; using curve fitting to measured data, kt of 1.2 kv and 15 kv SiC MOSFET is 1.54 and 3.5 respectively. kt is then linearly scaled from for kv SiC MOSFETs; R0 is the on resistance at room temperature T0 ( K) [72]: 2 4 BV R R ch sub R (BV, A ) 0 a (6.4) 3 ue A A c a a Where, Rch is the channel resistance, Rsub is the remaining SiC substrate resistance, Rch and Rsub together is around 1mΩ cm 2 [26]; ε, µ and Ec are the permittivity, electron mobility and critical electric field of 4H-SiC. Based on (6.4), the specific on resistance of SiC MOSFET is presented in Fig. 6-2, where, the doted data is the actual Gen-3 SiC MOSFETs data from Wolfspeed [73]. 125

148 SiC MOSFET R on-sp Model Wolfspeed-Gen 3 SiC MOSFETs Fig. 6-2 Specific on resistance model for SiC MOSFETs and specific on resistance of Wolfspeed Gen 3 SiC MOSFETs from k V. Output Capacitance Model To achieve high efficiency as well as high power density, zero voltage turn on (ZVS) is preferred. Series resonant converter can secure ZVS from zero to full load. In order to achieve ZVS, MOSFETs output capacitances are discharged by the magnetizing current during the dead time. MOSFET s output capacitance or output charge model is therefore important for choosing optimized magnetizing inductance and dead time that lead to minimum conduction loss of the system. MOSFET s output capacitor is nonlinear and strongly depends on its drain to source voltage - Vds as shown in (6.5) [58]. In (6.5), ka is decided by die size and BV of the MOSFET that can be written as (6.6). 126

149 C k (BV, A ) A a ( Vds ) C (A ) V V oss pk a ds bi (6.5) 2 2 Ec k (BV, A ) A ( BV, A ) A a c a (6.6) 4BV Sqrt(A a ) A a Edge Fig. 6-3 Active chip area and over all chip area considering edge termination. 15kV SiC MOSFET Measured C oss 1.7kV SiC MOSFET C oss from Datasheet 1.7kV SiC MOSFET C oss Model 15kV SiC MOSFET C oss Model Fig. 6-4 Output capacitance model for SiC MOSFETs and output capacitance of Wolfspeed 1.7 kv (CPM B), 15 kv SiC MOSFETs. 127

150 In practical MOSFETs, the edge termination greatly affect the blocking voltage. Typically, P type floating rings are used for edge termination. For higher break down voltage, greater edge distance will be needed. The overall die size Ac in (6.6) is the effective chip area plus the edge terminal area. As shown in Fig. 6-3, assuming square active chip, Aa can be given by (6.7). Fig. 6-4 gives a comparison between real measured and modeled output capacitance using (6.5). The Coss data of 1.7 kv is from CPM B s datasheet, and the measured Coss of 15 kv SiC MOSFET is from [58]. A (, ) 6BV 2 BV A ( A 2 ) c a a (6.7) E c Cost Model Cost of the SiC MOSFET can be divided into two parts bare die cost and packaging cost: Cost MOS k k wafer fab k (6.8) pack GDPW In (8), wafer cost kwafer is assumed to be linearly related to the break down voltage as well as the area of the wafer; good die per wafer GDPW is given by: GDPW DPW Yeild (6.9) Where, DPW - die per wafer, is the number of dies that can be placed on a wafer with certain diameter normally from mm; Yield is the fraction (or percentage) of good chips produced in a manufacturing process. A chip with no manufacturing defect is called a good chip. (6.10) Shows the relationship between the chip area and the yield. 128

151 Yeild e da c (6.10) where, d is the manufacturing defect density. The packaging cost includes the substrate and the case cost. Fig. 6-5 shows the calculated cost of SiC MOSFET. Both higher blocking voltage and larger chip area lead to greater cost. Due to the very limit information from the manufacturers, the cost coefficients in (6.8) are not based on bulk purchasing price, however, they can be easily modified once more references from industry are available. Fig. 6-5 SiC MOSFET s cost versus active chip area with different voltage level. 129

152 6.4 Circuit and Other Components Models By now the SiC MOSFET models have been obtained with wide break down voltage range and effective chip area. Models of series resonant circuit, transformer, heat sink and capacitors are also developed as below. Circuit Model Series resonant converter can realize ZVS at full load range. Switching loss is therefore neglected in this paper. It is the RMS current, average current and ripple current that are required by the power loss calculation of MOSFET, transformer and capacitor. These current models are well studied by [34][50]. Transformer Model Inspired by [74], a generic transformer model is developed based on given box volume, operation frequency and voltage level. Only ferrite core material is considered in this paper. Transformer local optimization is conducted by sweeping through: 1) possible core shapes with the fixed box volume; 2) large number of litz wires with realizable single strand diameter; 3) wide range of peak flux density level that keeps the magnetic core from saturation. Transformer core losses are calculated using Steinmetz equation, where the Steinmetz parameters are extracted from the datasheets that are provided by magnetic manufacture. Window area of the transformer is assumed to be fully utilized, and the litz wire is consider as well twisted. Skin effect losses and proximity effect losses are both included in the winding 130

153 loss model that is derived based on the work in [75]. Transformer temperature is estimated by assuming its surface cooling coefficient is 15 W/m 2 K. Transformer cost consisting core and winding cost are computed using the cost model presented in [71]. Transformer s reluctance models are developed based on the number of turns, core shape and winding structure. Capacitor Model Film capacitors are chosen to be both the resonant and the DC bus capacitors. Capacitors losses depend on their ripple current and equivalent series resistance (ESR). The ripple currents can be obtained from the circuit model. It is worth noting that if the number of cells - N is greater than 1, interleaving operation of all the cells are adopted to lower the input and output current ripple. Capacitor manufacture provides dissipation factor (tan δ) on their datasheet, which is defined as the ratio of the ESR and capacitive resistance. The volume of film capacitor is given in (6.11). According to the TDK - MKP - B32656S datasheet, the coefficients in (6.11) are obtained by curve fitting. Fig. 6-6 presents the volume of film capacitors versus capacitance from V, the dotted numbers are from datasheet, while the solid lines are based on the model shown in (6.11). V ( C, V ) k C V k V (6.11) 2 film cap R e cap R v R where, C cap is the capacitance and V R is the voltage rating. 131

154 Fig. 6-6 Film capacitors volume versus capacitance with different voltage level. Cooling System and Other Components Using the cooling system performance index (CSPI) [76], the heat sink volume can be estimated. Cooling system cost model presented in [71] is adopted to compute the cost of heat sink in this paper. Other components such as gate driver, PCBs, controller and auxiliary power supply are considered with fixed cost in this paper. 132

155 Transformer: Volume - V T (Wire diameter, dimension) Magnetizing Inductance - L m Leakage Inductance - L s Loss Model: Winding Loss Core Loss L m_range L s DC-DC Resonant Converter Specifications V in, V o, P o Number of cell- N Switching frequency- f s Electric Power Circuit Model V cell, f s, I rms, I avg, I ripple Semiconductor: Voltage Rating - BV Chip Area - A ch Thermal Resistor - R th R on (BV,A ch,t j ) C oss (BV, A ch ) Cost(BV,A ch ) Loss Model: Switching Loss Conduction Loss L m_opt t d_opt Film Capacitor Voltage Ripple Capacitance Model Loss Model T w, T c Thermal Model Transformer losses, cost and volume T j R th Thermal Model Device losses, cost Heat sink volume Over all Volumes, Cost and Losses Capacitor losses, cost and volume Save the design Fig. 6-7 Flow chart of ISOP series resonant DC-DC converter design using proposed SiC MOSFET models. 6.5 System Optimization Referring the optimization algorithm introduced by [77], the flow chart of the ISOP system optimization is presented in Fig System specifications are given at the very beginning of 133

156 the design. Switching frequency ranges from khz. Number of ISOP cells is from 1-5. For given number of cells - N, the equivalent input voltage VMV/N and power rating Po/N of each cell can be obtained. Series resonant circuit model is then applied to generate voltage and current that are required in the components level design. For a given box size of transformer, optimized core shape and litz wire are chosen based on local optimization. The derived MOSFET models can fit into the semiconductor design branch. Here, the break down voltage depends on the voltage stress, while the effective chip area is considered as a system design variable. For the capacitor design branch, film capacitors are chosen for both resonant and DC bus capacitors. When the number of cells - N is greater than 1, interleaving operation of all the cells is considered to lower both the input and output current ripple. Table 6-1 System Optimization Specifications Symbol Description Value fs Switching frequency khz N Number of cells 1-5 VMV MV voltage 12 kv VLV LV voltage 400 V Po Power rating 20 kw Ac Active chip area for both MV, LV MOSFETs mm 2 Rth Thermal resistance for heat sink of MV, LV o C/W MOSFETs VT Transformer box volume L Core R type ferrite 134

157 Detailed system optimization specifications are given in Table 6-1. Where the active chip area Ac, thermal resistance Rth and transformer box volume are scaled corresponding to the number of cells - N. Fig. 6-8 presents the optimization results of system power density versus overall efficiency. System cost versus power density is given by Fig The relationship between cost and efficiency is shown in Fig According to the optimization results, greater number of cells leads to higher power density (greater than 2 kw/l using 5 cells ISOP). But compared with multi cells ISOP, single stage converter can reach higher efficiency and lower cost. Fig. 6-8 Optimization results system efficiency versus power density. 135

158 Fig. 6-9 Optimization results system cost versus power density. Fig Optimization results system efficiency versus cost. 136