University of Southern C alifornia School Of Engineering Department Of Electrical Engineering

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1 University of Southern C alifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #05 Spring, 2002 (Due 03/05/2002) Choma Problem #18: The biasing circuit in Fig. (P18) is typically designed to ensure that transistor is biased within in its linear active domain. If the circuit is to provide a static collector biasing current,, that is nominally independent of temperature over reasonable base-emitter junction temperature excursions, the circuit must be designed so that the two transistors, and, are electrically identical and conduct equal collector current densities. In turn, this design constraint guarantees that the two transistor base-emitter voltages, V BE1 and V BE2, match one another over a wide range of operating temperatures. Consider the case in which the base-emitter junction area of transistor matches that of transistor. (a). Assuming that the circuit is designed correctly to ensure acceptable temperature desensitization, derive an expression for the static collector current,, in terms of circuit parameters, applied static voltages, and transistor h FE and V BE. (b). What design criterion must be satisfied to render almost independent of h FE? (c). Why is the biasing current,, nominally independent of the voltage, V P? (d). For a fixed collector load resistance, R L, what smallest value of applied static voltage, V P, ensures transistor operation in its linear regime? +V CC +V P R 1 R L R 2 R ee Problem #19: Fig. (P18) A modified version of the biasing configuration in Fig. (P18) appears in Fig. P19). All transistors are identical with the possible exception that the area ratios of the two devices can be adjusted to ensure that each transistor conducts nominally identical current densities, thereby preserving nominally identical base-emitter (V BE ) voltages across the two transis-

2 tors. For analytical simplicity and tractability, assume that each transistor has sufficiently large h FE to warrant tacit neglect of all quiescent base currents. +V CC +V P R 1 R L R y R x R 2 R ee Fig. (P19) (a). Derive an expression for the static collector current,, in terms of circuit parameters, applied static voltages, and transistor V BE. (b). Can a design criterion be invoked to render theoretically independent of V BE? If so, what is this design criterion? What circuit situation renders impossible the total desensitization of with respect to V BE? Problem #20: The three transistors in the base current compensated bias current mirror of Fig. (P20) are electrically identical and conduct identical collector current densities. As usual, the circuit is designed to ensure that all transistors operate in their respective linear regimes. +V CC +V P R R l Q3 R x Fig. (P20) (a). Derive an expression for the bias current,, in terms of circuit parameters, transistor h FE, and transistor V BE. Homework #05 31 Spring Semester, 2002

3 (b). What design requirements must be satisfied to render almost independent of h FE? (c). What purpose is served by resistor R X? Would the circuit operate acceptably over wide temperature ranges if R X were supplanted by an open circuit? Problem #21: The TN2219AM NPN transistor has the following abridged set of SPICE parameters. Use SPICE to generate, and submit plots of, the following static characteristic curves. Save copies of these plots; you will need them in subsequent homework assignments! (a). Base current (I B ) -versus- base-emitter voltage (V BE ) for collector-emitter voltages (V CE ) of 1.5, 2.5, and 3.5 volts. Vary V BE from zero -to- 800 mv. (b). Collector current (I C ) -versus- V BE for V CE =1.5, 2.5, and 3.5 volts. Vary V BE from zero - to- 800 mv. (c). Static current gain (h FE = I C /I B ) -versus- I C for V CE =1.5, 2.5, and 3.5 volts. Vary I C from 100 na -to- 10 ma, and plot I C on a logarithmic scale. PARAMETER DESCRIPTION VALUE UNITS IS Transport Saturation Current 1.80 fa βf Forward Current Gain 140 NF B-E Junction Emission Coefficient 1.0 VAF Forward Early Voltage 54 volts IKF Forward Knee Current 22 ma ISE B-E Leakage Saturation Current 800 fa NE B-E Leakage Emission Coefficient 2.05 βr Reverse Current Gain 0.2 NR B-C Junction Emission Coefficient 1.0 RB Average Base Resistance 150 ohms RE Average Emitter Resistance 2 ohms RC Average Collector Resistance 120 ohms CJE Zero Bias B-E Junction Capacitance 5 ff VJE B-E Built-In Potential 950 mv MJE B-E Junction Grading Coefficient 0.5 CJC Zero Bias B-C Junction Capacitance 10 ff VJC B-C Built-In Potential 790 mv MJC B-C Junction Grading Coefficient 0.34 CJS Zero Bias Substrate Capacitance 50 ff VJS Substrate-Collector Built-In Potential 700 mv MJS Subs.-Collector Junction Grading Coeff. 0.5 TF Forward Minority Carrier Transit Time 9 psec TR Reverse Minority Carrier Transit Time 46.9 nsec Homework #05 32 Spring Semester, 2002

4 Problem #22: Use the TN2219AM NPN transistor to design the circuit of Fig. (P18) to meet the following requirements and specifications (presumed quoted at 27 ºC). V CC = V P = 3.3 volts Both transistors biased for linear operation Both transistors identical, inclusive of junction areas = 1.2 V CE1 = 1.8 volts R L 5R ee changes by no more than 10% for temperatures ranging from 27 ºC - to- 75 ºC. Simulate the circuit, making sure to check the following performance indices. When the simulations do not track with either specifications or calculations, find out why and execute the required corrective actions. (a). Collector current ( ) at temperature (T) = 27 ºC, 50 ºC, 75 ºC. (b). Voltage at base of transistor, with respect to ground, at T = 27 ºC, 50 ºC, 75 ºC. (c). Voltage at collector of transistor, with respect to ground, at T = 27 ºC, 50 ºC, 75 ºC. (d). Voltage at emitter of transistor, with respect to ground, at T = 27 ºC, 50 ºC, 75 ºC. Homework #05 33 Spring Semester, 2002

5 University of Southern C alifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #05 Spring, 2002 (SOLUTIONS: Due 03/05/2002) Choma Problem #18: Homework #05 34 Spring Semester, 2002

University of Southern C alifornia School Of Engineering Department Of Electrical Engineering

University of Southern C alifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #04 Spring, 2001 (Due 02/27/2001) Choma Problem #16: n monolithic circuits, diodes