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1 Preprint This is the submitted version of a paper presented at 2th European Conference on Power Electronics and pplications (EPE ECCE Europe), SEP 7-2, 28, Riga, LTVI. Citation for the original published paper: Heinig, S., Jacobs, K., Ilves, K., Norrga, S., Nee, H-P. (28) Reduction of Switching Frequency for the Semi-Full-ridge Submodule Using lternative ypass States In: 28 2TH EUROPEN CONFERENCE ON POWER ELECTRONICS ND PPLICTIONS (EPE'8 ECCE EUROPE) IEEE European Conference on Power Electronics and pplications N.. When citing this work, cite the original published paper. Permanent link to this version:

2 Reduction of Switching Frequency for the Semi-Full-ridge Submodule Using lternative ypass States Stefanie Heinig, Keijo Jacobs, Kalle Ilves 2, Staffan Norrga, and Hans-Peter Nee KTH Royal Institute of Technology 2 Corporate Research Teknikringen 33 Forskargränd 7 SE- 44 Stockholm, Sweden SE Västerås, Sweden sheinig@kth.se cknowledgments Stefanie Heinig s and Keijo Jacobs research projects are funded by the Swedish Centre for Smart Grids and Energy Storage (SweGRIDS). Keywords Multilevel converters, Voltage Source Converter (VSC), HVDC, Modulation strategy, Switching losses bstract s regards modular multilevel converter submodules, a different number of switches may be involved in the transitions between voltage levels depending on the submodule type and choice of switching states. In this paper, an investigation of the average switching frequency associated with different choices of bypass states is performed for the semi-full-bridge submodule. Theoretical considerations and simulation results show that the average switching frequency per device can be halved by using the proposed alternative bypass state. Moreover, the switching losses can be reduced by up to 6%. Finally, a comparative study with the full-bridge submodule has been conducted. Introduction Supergrids based on high-voltage direct current (HVDC) technology are foreseen to be the most attractive solution for handling of massive power variations in electricity grids where most of the generated power originates from renewable power sources [, 2]. s the direction of power in such grids may change on many of the interconnections, voltage source converters (VSCs) are preferable. The state-of-the-art VSC for HVDC transmission is the modular multilevel converter (MMC), which was presented by Marquardt et al. [3 6]. When planning HVDC grids with MMCs, one of the most important aspects to consider is dc-side fault handling. Even if HVDC circuit breakers have been proposed [7], great cost savings are possible if the dc-side fault current can be controlled by the converter itself [8]. mong submodule topologies which facilitate this property, the semi-full-bridge (SF) submodule [9] is particularly interesting because it uses less semiconductors than the conventional full-bridge (F) submodule and also provides the possibility to operate the converter at increased modulation indices which can significantly reduce the energy storage requirements of the submodule capacitors. It has been shown in [9] that the capacitor voltage ripple can be reduced by 59 % compared to unity modulation index. The SF submodule has, however, not been investigated extensively. Recently, the potential problem of parallel connection of submodule capacitors with different voltages was investigated [, ]. Nevertheless, many other aspects of the SF submodule topology still remain to be addressed.

3 s the submodule involves seven controllable switches, additional degrees of freedom with respect to combinations of ON/OFF-states of the different switches are obtained. particularly interesting feature of the SF submodule is that the bypass state described in [9] is only one out of three possible options. detailed investigation of how transitions between insert states and bypass states are performed reveals that a different number of switches are involved during a transition depending on the choice of bypass state. Without extensive analysis, it is a reasonable assumption that the involved switching losses are influenced by the average switching frequency per device. In this paper, therefore, a detailed study of the average switching frequency and the corresponding switching losses associated with different choices of bypass states is presented and compared to a F submodule. Switching Operations of the Semi-Full-ridge Submodule The SF submodule has been firstly presented and described in [9]. It is a double submodule comprising seven switches, S 7, with antiparallel diodes and two capacitors, and, as shown in Fig., where i arm denotes the arm current. i arm Fig. : Schematic diagram of the SF submodule. The available voltage levels, V SF, of the SF submodule are,±v C, and 2V C. Since one negative voltage level can be inserted, it is possible to increase the modulation index above unity. Table I lists possible combinations of switching states to insert these voltage levels. The first four switching states, one per voltage level, have been presented in [9], hereafter referred to as original states. However, the original bypass state is only one out of three possible bypass options. The other two bypass states, hereafter referred to as alternative bypass states, are highlighted in bold. and S 5 are switched simultaneously but only one of the devices is conducting if the alternative bypass state is used, as will be discussed later. Table I: Switching states of SF submodule. V SF Insertion of capacitors S 5 S 7 2V C in series V C in parallel bypassed V C in parallel bypassed bypassed In order to avoid high oscillating redistribution currents when the two capacitors are connected in parallel, it has been recently shown in [] that it could be a viable option to operate the SF at elevated switching frequencies. Hence, the capacitors are connected in series for a shorter time span and the resulting voltage difference, which causes the current-spike, is smaller if not negligible. However, a higher switching frequency increases the switching losses of the submodule. It is, therefore, meaningful to investigate alternative switching states of the SF in order to reduce the average switching frequency per device and, thus, the corresponding losses. s regards converter losses in general, the bypass state is of particular importance since transitions between insert and bypass state coincide with high arm current amplitudes for active power transfer or small phase angles. Fig. 2 illustrates this fact for rectifier and inverter mode. Therefore, there is a high potential to reduce losses if these transitions are improved.

4 .5 p.u. -.5 v s, ref i arm, rectifier i arm, inverter Time [s] Fig. 2: Example of required switching states of the SF, M =.. series parallel pos bypass Phase-shifted carrier pulsewidth modulation (PSC-PWM) has been chosen to determine the required switching states shown in the three lower plots of Fig. 2, where v s,ref denotes the voltage reference. The state which generates negative terminal voltages does not occur in this example since the modulation index M is set to.. It should be noted that the voltage levels change stepwise when applying PSC- PWM. In other words, no voltage level is skipped during a transition and the voltage steps are always V SF = ±V C. Therefore, in order to analyze the number of switches that are involved if the alternative bypass states are chosen, only the transitions between parallel inserted state and bypass state are relevant. The choice of bypass state does not affect switching actions between series inserted and parallel inserted states. Hence, these transitions are not discussed hereafter. The aforementioned relevant switching states for the analysis of the alternative bypass states are illustrated in Figs. 3 7, both for positive and negative arm currents. In these illustrations, conducting on-state devices are depicted in red color, and devices that are turned off are shown in gray color. The switching states when the capacitors are inserted in parallel are shown in Fig. 3 and Fig. 4. The original proposed bypass state [ ] as presented in [9] is shown in Fig. 5, followed by the two alternative bypass states in Fig. 6 and Fig. 7. Comparing transitions between the insert state and the different bypass states, it becomes obvious that especially the transition from insert one positive voltage level, see Fig. 3, to the original bypass, see Fig. 5, and vice versa is unfortunate in terms of switching losses because it involves a change of all switch positions. This transition can be improved if the two alternative bypass states, see Fig. 6 and Fig. 7, are utilized instead. The first alternative state [ ] creates a path for the current along the upper side of the SF, and the second alternative state [ ] allows the current to flow along the lower side of the SF. In contrast to the former case, only one half-bridge needs to be switched to achieve a transition to these bypass states, either half-bridge [ ] or [ S 7 ]. However, it should be noted that the choice of the alternative bypass state influences the required rating of the semiconductors and S 5. These devices have to withstand the full arm current and need to be rated accordingly. In the following, it shall be investigated how the choice of bypass state affects the average switching frequency per device, f sw,avg, of the SF submodule. s a simple and clear way to illustrate this, the switching pattern and frequency of each device, f sw,i, has been individually derived for one fundamental cycle. This is shown for modulation indices below and above unity in Fig. 8 and Fig. 9, respectively.

5 a) b) Fig. 3: Parallel inserted state, with positive polarity. a) Positive arm current. b) Negative arm current. a) b) Fig. 4: Parallel inserted state, with negative polarity. a) Positive arm current. b) Negative arm current. a) b) Fig. 5: Original proposed bypass state. a) Positive arm current. b) Negative arm current. a) b) Fig. 6: lternative bypass state. a) Positive arm current. b) Negative arm current. a) b) Fig. 7: lternative bypass state 2. a) Positive arm current. b) Negative arm current.

6 V SF 2V C V C S 5 S 7 t f sw,i Hz Hz Hz Hz Hz 35.7 Hz 7.4 Hz Fig. 8: Switching pattern and frequency per device based on staircase modulation, M. Original (blue) and alternative (red) bypass state. { f sw,avg V SF 2V C V C ωt -V C S 5 S 7 f sw,i 92.9 Hz Fig. 9: Switching pattern and frequency per device based on staircase modulation, M >. Original (blue) and alternative (red) bypass state. { f sw,avg

7 For visualisation purposes, this analysis is based on staircase modulation. reference waveform (black, solid) with a modulation index of. is used to illustrate the switching pattern for M in Fig. 8, whereas in Fig. 9 the modulation index is set to 3., the maximum value for the SF, to picture the switching pattern for M >. The modulation signal (black, dashed) alternates between the available voltage levels of the submodule as described above. It is further assumed that only one of the alternative bypass states is used, e.g. bypass [ ]. This way the switching actions of the left half-bridge [ ] are minimized, whereas the other alternative bypass would minimize the switching of half-bridge [ S 7 ]. and do not have to be switched at all in the case of M shown in Fig. 8. If, however, the insertion of a negative voltage level is necessary, which is the case in Fig. 9, the half-bridge [ ] has to be switched because needs to be turned on, see also Fig. 4. The switching pattern of every switch in the SF is compared in Fig. 8 and Fig. 9 for the original (blue) or alternative (red) bypass state. The resulting switching frequency per fundamental cycle of each device, f sw,i, is given on the right. The average switching frequency per device, f sw,avg, is given by their sum divided by the number of switches. The most important finding from this theoretical exercise is that the average switching frequency per device can be significantly reduced by employing the alternative bypass state instead of the one proposed in [9]. For the case of M it can be exactly halved. s can be seen in Fig. 8, the devices, and S 5 switch only half as often compared to the original bypass state. S 5 does not need to be switched off during the time when the bypass state [ ] is active. The same is true for if the state [ ] is used. In order to achieve an equal thermal stress distribution among the devices, the two alternative bypass state should be selected alternately. This would, however, not change the outcome of this analysis, i.e. the average switching frequency per device. The switching patterns and hence the switching frequencies change for higher modulation indices, cf. Fig. 9. This is not surprising since an additional transition to the negative voltage level and back takes place. However, the average switching frequency can still be reduced by 46% when employing the alternative bypass state. n overview of this study including the number of switching actions per fundamental cycle is given in Table II. Following the approach presented in Figs. 8 9, the same data can be derived for other MMC submodule topologies as well. For the purpose of comparison two of each submodule with only one capacitor have been considered. The values for the average switching frequency are normalized to a H implementation. However, one should bear in mind that it is not possible to draw direct conclusions about the topologies switching losses from the data presented in Table II. Staircase modulation has been chosen here for the sake of simplicity. The average switching frequency and switching actions may differ if another modulation strategy like PSC-PWM is chosen. The losses also depend on the magnitude of the switched current that is, for example, lower at higher modulation indices. Moreover, the arm current is directed in parallel through the SF submodule during the parallel inserted states. Only half of the arm current needs to be switched during these transitions. Table II: verage switching frequency and switching actions for different MMC submodule topologies employing staircase modulation. Submodule topology No. of switches f sw,avg [pu] No. of switching actions M M > M M > 2x H x F SF (original bypass) SF (alternative bypass)

8 Loss Calculation The loss calculation is performed within the software PSCD/EMTDC on the basis of an MMC converter test case which is presented in the subsequent section. The semiconductor data used in this simulation study has been taken from the datasheet of a commercial StakPak IGT module [2] and is shown in Table III. Table III: Semiconductor data. Parameter Symbol Value Collector-emitter voltage V CE 45 V Nominal supply voltage V C8 V DC collector current I Turn-ON switching energy E on mj Turn-OFF switching energy E off 5 mj Reverse recovery energy E rec 55 mj The power loss for switching events, P sw, is approximated by a linearization of the switching energy characteristics at T vj = 25 C as given in [2]. The instantaneous voltage across the device v S and the total current in the device i S are related to the nominal voltage and current values according to () P sw = T t t T E sw,nom v S i S, () V CC I C where the generally expressed nominal switching loss energy E sw,nom serves as a placeholder for either turn-on losses E on, turn-off losses E off, or reverse recovery losses E rec as stated in Table III. The switching loss calculation is implemented with a sliding interval of period T that corresponds to the time after which the switching pattern of the converter repeats. T depends on the ratio between f c and f and can be determined by means of computing the least common multiple of those two frequencies. T is only equal to / f if f c is an integer multiple of f ; otherwise the time before the switching pattern repeats would be longer. It should be noted that different commutation loops are formed during the transitions between voltage levels depending on the choice of switching states. part from the different number of switches involved, the characteristic of the respective commutation loop may also affect the amount of switching losses. It is, however, reasonable to assume that those differences are comparatively small. detailed study of the switching losses based on commutation loops is, therefore, considered outside the scope of this paper. The calculation is solely based on a reduction of the average switching frequency per device. Simulation The prediction of significantly reduced average switching frequency and thus losses of the SF using different bypass states is verified by simulating a three phase MMC. The converter is equipped with five SF submodules per arm, which corresponds to ten capacitors, and is feeding a passive load. Simulations have been conducted for modulation indices below and above unity while maintaining the same converter power. The respective parameters of the considered system are summarized in Table IV. In the simulation, PSC-PWM is employed with four carriers per cell. The internal arm-balancing control including circulating current and hybrid voltage control is implemented based on [3]. However, the control scheme had to be slightly modified in order to enable the usage of negative voltage levels. That way the converter can be operated with a modulation index greater than unity.

9 Table IV: Specification of considered system. Parameter Symbol Value M M > Converter power 2 MV 22 MV DC voltage (pole-pole) V dc 3 kv 25 kv Modulation index M.9.4 Phase voltage (rms) V s 9.5 kv 2.4 kv lternating current (rms) I s Carrier frequency f c Hz Hz Number of SF submodules per arm N sub 5 5 Nominal capacitor voltage V 3. kv 3. kv Submodule capacitance C 4. mf 4. mf rm inductance L arm 4.5 mh 4.5 mh Passive load R load Ω 2 Ω Results Simulations have been conducted for SF and F submodules. With regard to the SF, the simulation results demonstrate how the alternative bypass states [ ] and [ ] compare to the original proposed bypass using the state [ ]. The resulting switching losses of a SF submodule under the given test case conditions are shown in Figs. and are normalized to the losses of the SF with original bypass and M, which are shown in blue in Fig.. The bar charts group the power loss of the two different bypass states in blue and red columns per switch position, whereby the results for IGT and diode are stacked per bar as indicated in the legend on top of the plots. The result demonstrates a significant loss reduction in all of the seven switch positions of the SF if the alternative bypass states are used at modulation indices below unity, see Fig.. The reverse recovery loss of the diode in switch position can be eliminated and devices and S 5 switch only when the arm current is low. The cumulated losses in all devices 7 are compared on the right. It is found that the halving of the average switching frequency translates into a 6% reduction of switching losses. Original bypass IGT lternative bypass IGT P loss [pu] S 5 S 7 Switch position -7 Fig. : Switching loss break-down per device and total switching loss in a SF submodule. Original (blue) and alternative (red) bypass state, M =.9.

10 Original bypass IGT lternative bypass IGT P loss [pu] S 5 S 7 Switch position -7 Fig. : Switching loss break-down per device and total switching loss in a SF submodule. Original (blue) and alternative (red) bypass state, M =.4. The simulation results for the operation of the MMC at M =.4 are shown in Fig.. The switching loss distribution among the seven devices of the SF submodule appears to be quite different compared to the former case of M =.9. This is due to the fact that the negative voltage level is utilized in this case which causes different transitions. major change can be found in the cumulated losses of the original bypass. This loss reduction originates primarily from the devices and. For M =.4, there are mainly transitions between bypass and parallel insert with negative polarity at high arm currents, whereas for M =.9, those transitions are mainly between bypass and parallel insert with positive polarity. The required switching actions in case of M =.4 are favourable as regards the losses in and since they have not to be switched, cf. Figs However, the total loss comparison on the right-hand side of Fig. shows that the alternative bypass still allows to cut the switching losses by 4%. Finally, the presented switching losses of a SF are compared to two series-connected F submodules. The result is shown in Fig. 2. It indicates that the SF with original bypass state has higher losses in both cases. However, the proposed bypass enables a loss reduction of 6% and 4%, respectively. s a result, the SF has approximately the same losses as two F submodules if the alternative bypass states are chosen. SF Original bypass SF lternative bypass F IGT IGT IGT.8 P loss [pu] M =.9 M =.4 Fig. 2: Total switching losses of a SF and two F submodules.

11 Conclusion This paper proposes alternative bypass states for the SF submodule which reduce the number of switching actions during voltage transitions. Hence, they enable a reduction of the average switching frequency per device which translates into a reduction of switching losses. The effectiveness of these alternative bypass states is validated by simulations of an MMC at different operating points. Moreover, a comparison to an implementation with F submodules is provided. The quantification of the switching losses that is presented for both the original and alternative bypass states of the SF reveals a loss reduction of up to 6%. The simulation results show that a SF submodule with original bypass comes off worse in the comparison with F cells. However, a SF with alternative bypass can close this gap by having approximately the same switching losses as two F submodules. It can be concluded that the proposed bypass states enable a significant reduction of the switching losses of the SF submodule. References [] N. hmed,. Haider, D. V. Hertem, L. Zhang, and H.-P. Nee, Prospects and challenges of future HVDC supergrids with modular multilevel converters, in Proc. 4th European Conf. Power Electron. and pplicat. (EPE ECCE Europe), irmingham, Sep. 2. [2] N. hmed, S. Norrga, H.-P. Nee,. Haider, D. V. Hertem, L. Zhang, and L. Harnefors, HVDC supergrids with modular multilevel converters - The power transmission backbone of the future, in Proc. Int. Multi- Conf. Systems, Signals and Devices, Chemnitz, Mar. 22. [3]. Lesnicar and R. Marquardt, n innovative modular multilevel converter topology suitable for a wide power range, in Proc. IEEE ologna Power Tech Conf., ologna, Jun. 23. [4], new modular voltage source inverter topology, in Proc. th European Conf. Power Electron. and pplicat. (EPE 3 ECCE Europe), Toulouse, Sep. 23. [5] R. Marquardt and. Lesnicar, New concept for high voltage - Modular multilevel converter, in Proc. IEEE 35th Power Electron. Specialist Conf. (PESC), achen, Jun. 24. [6] M. Glinka and R. Marquardt, new ac/ac multilevel converter family, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp , Jun. 25. [7] J. Häfner and. Jacobson, Proactive hybrid HVDC breakers - key innovation for reliable HVDC grids, in CIGRÉ Symposium, ologna, Sep. 2. [8] S. Norrga, X. Li, and L. Ängquist, Converter topologies for HVDC grids, in Proc. IEEE Int. Energy Conf. (ENERGYCON), Cavtat, May 24. [9] K. Ilves, L. essegato, L. Harnefors, S. Norrga, and H.-P. Nee, Semi-full-bridge submodule for modular multilevel converters, in Proc. 9th Int. Conf. Power Electron. and ECCE sia (ICPE 25-ECCE sia), Seoul, Jun. 25. [] S. Heinig, K. Jacobs, K. Ilves, S. Norrga, and H.-P. Nee, Implications of capacitor voltage imbalance on the operation of the semi-full-bridge submodule, in Proc. 9th European Conf. Power Electron. and pplicat. (EPE 7 ECCE Europe), Warsaw, Sep. 27. [] K. Ilves, Y. Okazaki, N. Chen, M. Nawaz, and. ntonopoulos, Capacitor voltage balancing in semi-fullbridge submodule with differential-mode choke, in Proc. 2th Int. Conf. Power Electron. and ECCE sia (ICPE 28-ECCE sia), Niigata, May 28. [2], StakPak IGT Module. 5SN 2K453 datasheet, Oct. 26. [3] K. Sharifabadi, L. Harnefors, H.-P. Nee, S. Norrga, and R. Teodorescu, Design, control and application of modular multilevel converters for HVDC transmission systems. John Wiley & Sons, Ltd., 26.