Efficient Modeling of Hybrid MMCs for HVDC Systems

Transcription

1 Efficient Modeling of Hybrid MMCs for HVDC Systems Lei Zhang, Member, IEEE, Jiangchao Qin, Member, IEEE, Di Shi, Senior Member, IEEE, and Zhiwei Wang, Member, IEEE School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ , USA. GEIRI North America (551 Great America Parkway STE.15) Santa Clara, CA 955, USA. Abstract-Modular multilevel converters (MMCs) have become one of the most promising converter technologies for medium/high-power applications, specifically for highvoltage direct current (HVDC) transmission systems. For large-scale power system applications, i.e., multiterminal dc (MTDC) systems and dc grids, modeling and simulation plays an important role in transient and fault analysis. However, it is time consuming and infeasible to model and simulate large-scale MMCs-embedded power systems with detailed switching model (DSM). To accelerate timedomain simulation and improve computational efficiency, an equivalent circuit simulation model (ESM) is proposed for hybrid MMC configuration based on various SM circuits. The proposed ESM can significantly improve simulation efficiency and be applied in normal and fault operation analysis. The effectiveness of the proposed ESM is verified by a1-level hybrid MMC built in P- SCAD/EMTDC software environment. Index Terms Modular Multilevel Converter (MMC), MMC modeling, equivalent circuit simulation model, PSCAD/EMTDC, voltage-sourced converter (VSC), I. INTRODUCTION Due to modularity and scalability, the modular multilevel converter (MMC) becomes the most attractive converter topology for medium/high voltage applications, especially for voltage-sourced converter high-voltage direct current (VSC- HVDC) transmission systems [1]. The MMC with half-bridge (HB) submodules (SMs) is the dominant topology for HVDC systems. However, in case of a dc-side fault, the HB-MMC cannot block the fault currents feeding from ac grid. Various SMs are investigated to improve the fault blocking performence of MMC, such as the full-bridge (FB), the unipolar-voltage full-bridge (UFB), the clamp-double (CD), and the three-level/five-level crossconnected (3LCC/5LCC) SMs [] []. As compared with HB- MMC, the number of swiching components of the MMC consistis of fault blocking SMs are greatly increased as well as initial cost and power losses. To improve efficiency and reduce cost, the hybrid MMC has been proposed in [], which combined HBSMs and fault-blocking SMs. In large-scale MMCs-embedded power systems, it is required to investigate dynamic performance, fault, protections, and stability [5] [8]. The detailed switching model (DSM) is time consuming and infeasible due to large number of semiconductor switches in high-level applications. To address this challenge, several equivalent models have been developed to accelerate the electromagnetic transient (EMT) simulation. Averaged models: In [9], [1], an averaged model has been proposed only for the HB-MMC configuration under normal operating conditions, without considering dc fault operating conditions. Reference [11] presents two average-value models applied to multiterminal direct current (MTDC) systems. As discussed in [11], although they are scalable and efficient, they are not applicable for investigating dc-side transient and fault conditions. Similar models are also presented for the HB-MMC and FB-MMC in [8], [1], [13]. Detailed equivalent circuit models: To investigate dc fault and transient conditions, a detailed equivalent circuit simulation model (ESM) combined with the hybrid HVDC breaker the is proposed in [1] for the HB-MMC-based MTDC system, which is able to estimate the capacitor voltage for each SM. The switching function of each SM and arm currents are required to calculate the capacitor voltages and arm voltages. The j th SM capacitor voltage in an arm is described by the differential equation and solved by the numerical method. Equivalent circuit models with fault-blocking capability: All above models are propsoed for HB-MMC, which don t have fault blocking capability. To consider the MMC with embedded fault-blocking capability, a detailed ESM has been proposed for self-blocking MMC (SB- MMC) in [15]. However, the proposed ESM is only specified for the SB-MMC. Reference [16] presents a ESM for hardware-in-the-loop (HIL) test bench, which is suitable for HB-MMC and FB-MMC. However, although the computation time is short enough, it is not cost efficient for large-scale power system applications. In addition, as compared with SB-MMC, the hybrid MMC based on HBSM and FBSM has been widely investigated

2 for various applications, such as the HVDC systems [17] [19], wind power trasmission system [], and battery energy storage systems [1]. Therefore, in this paper, the hybrid MMC consists of HBSMs and FBSMs is selected to verify the proposed ESM. Finally, the effectiveness of the ESM is evaluated by a 1-level MMC-HVDC system with considering the normal and fault operation conditions. The studies are carried out based on time-domain simulations in the PSCAD/EMTDC environment. The rest of this paper is structured as follows. Section II briefly introduces the operational principles of the hybrid MMC consists of HBSMs and FBSMs (HBFB-MMC). Then the proposed ESM is developed and analyzed in this section. The simulation results of the 1-level MMC-HVDC system are presented in Section III to verify the proposed ESM. Section IV concludes this paper. II. OPERATIONAL PRINCIPLES AND MODELING OF HYBRID MMC As aforementioned, the hybrid MMC is an efficient solution to improve fault blocking capability of MMCs while keeping low cost and losses. In this paper, an ESM is proposed for the hybrid MMC to accelerate simulation. The studied hybrid MMC is based on HBSMs and FBSMs. A. SM Operation For various fault-blocking SMs in hybrid MMC, when the conducting switchs are turned on, they have the same behavior of HBSM. The conducting switch is continuously conducted during the normal operational condition []. The conducting switches of various fault-blocking SMs are highlighted in Fig. 1. As presented in [], [3], for HBSM, there are three operation states, which are as follows: Inserted: When the S 1 is turned on while the S is turned off, the capacitor is inserted into arm. The charging and discharging of capacitor is determined by the direction of arm current. Bypassed: When the S is turned on while the S 1 is turned off, the SM is bypassed. Blocked: When both the S 1 and S are turned off, the arm current can only flow through the anti-parallel diodes of S 1 and S. B. Operational Principles of Hybrid MMC A schematic diagram of the hybrid HBFB-MMC is shown in Fig.. There are N SM SMs in each arm, which consists of N HB HBSMs and N FB FBSMs. The operation conditions of an MMC include the precharging condition, the normal operation condition, and the fault blocking condition. Precharging:The capacitors in SMs should be precharged to the nominal voltage before getting into normal operation condition. Otherwise, the inrush current might lead to the destroy of IGBTs and capacitors. The precharging strategies have been investigated in [] []. The precharging progress is generally consisted of the uncontrollable precharging stage and controllable precharging stage. During the uncontrollable precharging stage, the current flows through the anti-parallel diodes of IGBTs and charges the capacitors. During the controllable precharging stage, the number of inserted capacitors or the charging current is controlled to charge the capacitors to their nominal voltages. N FB S5 Conducting switch Conducting switch (c) Conducting switch (d) v a v b v c S5 S6 S5 Conducting switch (e) Conducting switch Fig. 1. The configuration of various SMs with highlighted conducting switches: HBSM, the CDSM, (c) FBSM, (d) uufbsm, (e) 3LCCSM, and (f) 5LCCSM. (f) Fig.. Block diagram of a hybrid MMC-HVDC system, including the HBSMs and FBSMs with a highlighted dc-fault current path.

3 T ON : Normal OFF: Block SSMi(1 : N) iarm v arm Voltage calculation (c) vci(1 : N) v arm v arm Normal: ON:, v arm Fig. 3. The proposed equivalent circuit simulation model of an arm: circuit diagram of ESM, normal operation, (c) and (d) current path under blocking condition. Normal operation: The basic operation principles of MMC have been presented in [1], [5], [6], in which the SM configuration, modulation methods, mathematical model, and design constrains are investigated in detail. As analyzed in [5], [6], each arm can be simplified as a controllable voltage source. By controlling the arm voltage, the grid currents and circulating currents can be controlled. DC fault blocking: When the dc fault occurs, all controllable switches are turned off. The current only charges capacitor through anti-parallel diodes. The HBSM will be naturally bypassed while the fault-blocking SMs are blocked. Under this condition, the line-to-line voltage of ac grid is supported by the capacitors in fault-blocking SMs. The capacitor voltage of fault-blocking SM is determined by the amplitude of line-to-line voltage. Fig. shows the current path of a hybrid MMC, which is consisted of HBSMs and FBSMs. (d) C. Equivalent Model of Hybrid MMC The configuration of the proposed ESM for each arm of hybrid MMC is shown in Fig. 3. 1) Normal operation condition: Under normal operation condition, the switching status of the proposed ESM is shown in Fig. 3. All fault-blocking SMs in hybrid MMC can be regarded as HBSM. The operation principles of hybrid MMC is the same as HB-MMC. The voltage source in the ESM represents the sum of inserted capacitor voltages. The dynamic of the i th capacitor voltage in each arm is given by: i ci = C dv ci = S SMi. dt (1) Where v ci represents the i th capacitor voltage; i ci refers to the i th capacitor current; refers to the arm current; S SMi reprensts the switching function of the i th SM, which is defined as: S SMi = { 1, inserted, bypassed. The capacitor voltage at time t k can be derived from (1), which is given by: tk v ci (t k ) = v ci (t k-1 ) 1 i ci (τ)dτ. (3) C t k-1 When applying the simpson quadrature method to solve the integration, (3) can be expressed as: v ci (t k )=v ci (t k-1 ) t 6C [i ci(t k )i ci ( tktk-1 )i ci (t k-1 )]. () Where t = t k t k-1 is the simulation step time. The i ci ( tktk-1 ) is estimated from last simulation step. It assumes that the current has the same derivative as during last simulation interval ( t = t k-1 t k- ). Thus, the average current during the current simulation interval is given by: ( ) tk t k 1 i ci = i ci (t k 1 ) i ci(t k 1 ) i ci (t k ) = 3i ci(t k 1 ) i ci (t k ). (5) Consequently, during each simulation interval ( t = t k t k-1 ), i ci ( tk1tk ) should be estimated for the next simlation step. Finally, the arm voltage can be calculated from switching functions and capacitor voltages, which is given by: () N SM v arm (t k ) = S SMi v ci (t k ). (6) Where N SM is the number of SMs in each arm. ) Special operation conditions: As proposed in [3], during the uncontrollable precharging stage, all SMs are blocked. During the controllable precharging stage, the number of blocked SMs N BLK are gradually reduced to the reference value. Under dc fault-blocking condition, all SMs are blocked. Under blocked operational condition, the switching signals of all switches are zero. The Eq. 1 is not satisfied. Under this condition, when the arm current is negative, the HBSM is bypassed. When the arm current is positive, it can charge the capacitor. For fault-blocking SMs, the arm current always charges the capacitor. For HBSM, the relationship between capacitor current and arm current can be expressed as: i ci = i=1 {, i ci >, i ci <. For fault-blocking SMs, the relationship between capacitor current and arm current can be expressed as: (7) i ci =. (8)

4 1 ESM i a DSM i a Fig.. L ac AC grid MMC R dc R dc DC load Simualtion test circuit for verification of proposed ESM. TABLE I PARAMETERS OF THE SIMULATION 1-LEVEL HYBRID MMC Parameters Nominal Value DC load resistance, R dc 5 Ω DC link voltage 6 kv AC grid line-to-line voltage 3 kv RMS Number of HBSM per arm, N HB 1 Number of FBSM per arm, N FB 1 Arm inductance 5mH Capacitance per SM 1 µf Rated capacitor voltage per SM 3 kv TABLE II COMPARISON OF SIMULATION MODELS FOR 1-LEVEL HYBRID MMCS BASED ON DSM AND ESM Model DSM hybrid MMC Detailed ESM hybrid MMC step (µs) Running III. SIMULATION VERIFICATION In order to verify the proposed ESM, a 1-level hybrid MMC consisted of HBSMs and FBSMs are selected as the study system, as shown in Fig., based on PSCAD/EMTDC simulation program. The parameters of the 1-level hybrid MMC system are listed in Table I. A. Comparison of proposed ESM with DSM A comparison between the proposed ESM and the conventional DSM is conducted. The computational time of DSM and ESM are listed in Table II. During the normal operation condition, the amplitude of phase current should be 1 ka. When dc fault occurs, the current from ac grid is blocked by the FBSMs. The simualtion results of ac-side phase current and dc current are shown in Fig. 5 and respectively, in which DSM refers to the results of detailed switching model, while ESM refers to the results of the proposed equivalent circuit simulation model. The simulation results of arm currents and capacitor voltages of DSM and ESM are shown in Fig. 6 and respectively. As shown in these simulation results, the results of proposed ESM are matched with those of DSM. Currrent (ka) Current (ka) ESM i dc DSM i dc Fig. 5. The simulation results of DSM and ESM of phase current, and dc current. Current (ka) Voltage (kv) ESM i au DSM i au ESM i al DSM i al ESM V cau DSM V cau ESM V cal DSM V cal Fig. 6. The simulation results of DSM and ESM arm currents of phase a, and capacitor voltages in phase a. B. Verification under various operation conditions The capacitor voltages of DSM and ESM under various operation conditions are shown in Fig. 7 and respectively. Precharging:During the uncontrollable precharging stage, the capacitor of FBSMs are charged to about 1.6 kv, while the capacitor voltage in HBSMs are charged to about.8 kv at.1 s. Then, when the controllable switches are turned on, the N BLK reduced to 1. The SM capacitors of the HB and FB SMs are charged to the same steady-state voltage.1 kv at about.6 s. When then BLK is gradually reduced to 1, all capacitor voltages are charged to 3 kv, the nominal capacitor voltage. Normal operation: After all capacitors are charged to nominal voltage, the MMC operates normally. DC fault blocking: When the dc fault occurs, all controllable switches are turned off. The ac-side line-to-line voltage is supported by the capacitors in FBSMs. In this way, the fault current from ac grid can be blocked..9

5 Voltage (kv) Voltage (kv) Precharging 3 Fault Precharging Fault Fig. 7. The capacitor voltage of DSM and ESM under various operation conditions. As indicated in above figures, the simulation results of ESM are in accordance with those of DSM. Consequently, as verified by above simulation results, the proposed ESM can efficiently and accurately simulate the MMC-HVDC with various SM circuits, i.e., HBSM and FBSM. C. Computational times of MMCs with various levels TABLE III COMPUTATIONAL TIMES OF THE ESM FOR VARIOUS MMC LEVELS MMC Levels step (µs) Running To evaluate the simulation speed, the MMCs based on ESM with various levels are simulated in PSCAD/EMTDC program environment. In each arm, the number of HBSMs is equal to the number of FBSMs. The computational times of ESM for various MMC levels are listed in Table III. IV. CONCLUSION In this paper, an equivalent circuit simulation model is proposed for hybrid MMCs with various SM circuits to efficiently speed up the time-domain simulation. The behavior of hybrid MMC consists of HBSMs and FBSMs is also briefly analyzed for the precharging, the normal operation condition, and dc fault condition. Based on the analysis, the equivalent circuit simulation model is developed and its behavior is analyzed in detail. Finally, a simulation model of a 1-level hybrid MMC is built based on the proposed equivalent circuit simulation model. To verify the accuracy and efficiency of the proposed model, all simulation results are compared with those of detailed switching model. As indicated in simulation results, the equivalent circuit simulation model can efficiently and accurately simulate the MMC with various SM circuits under precharging, normal and fault operating conditions. REFERENCES [1] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard, and P. 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