A Spice-2 Subcircuit Representation For Power MOSFETs Using Empirical Methods

Size: px

Start display at page:

Download "A Spice-2 Subcircuit Representation For Power MOSFETs Using Empirical Methods"

Chester Burke
5 years ago
Views:

1 A Spice2 Subcircuit Representation For Power MOSFETs Using Empirical Methods Application Note October 1999 AN759 Title N75 ) ubct (A ice Subcuit epre ntan r wer OS ETs, sing mpiral eths) utho ) eyords nter orpo ion) reor () OC FO f ark ageode se Abstract An accurate powermosfet model is not widely available for CAD circuit simulation. This work provides a subcircuit model which is compatible with SPICE2 software and MOSFET terminal measurements. SPICE2 is the circuit simulation package of choice for this work because of its universal availability, despite its inherent limitations. These limitations are circumvented through circuit means. This effort models powermosfet terminal behavior consistent with SPICE2 limitations; hence it will differ from the physical model as suggested by Wheatley, et al 1, Ronan et al 2 and others. We feel we have advanced prior efforts 3 particularly in areas of thirdquadrant operations, avalanchemode simulation, switching waveforms and diode recovery waveforms. G E 1 C 1 D2 C 2 I (V meas.) E 1 C 3 V pinch V meas. S R DRAIN L SOURCE R SOURCE D BODY NOTE: If the JFET source voltage, E 1, is very low relative to its V PINCH voltage, the JFET is in a highly conductive state, tightly coupling C 2 to the JFET drain. However, as the voltage E 1 approaches V PINCH, the JFET operates in a constantcurrent mode, thereby permitting a much faster drain slew rate, which is determined primarily by C 3. D 1 D V BREAK FIGURE 1. SPICE2 SUBCIRCUIT FOR POWER MOSFET SIMULATION Discussion The subcircuit shown in Figure 1 is described in Table 1. All passive circuit elements are constants. The veryhighgain JFET is used to simulate the dualslope drain voltage vs time switching curve common to the power MOSFET. 1,2 If E 1 exceeds V PINCH, errors will exist in the turnon waveforms. The C 2 discharge currentcontrolled current source remedies this situation in conjunction with the subcircuit containing D 2. The D 2 ideality factor was set at.3 to assure that E 1 minus V PINCH does not exceed several millivolts. The body diode cannot be properly modeled by the JFET gatedrain diode, hence D BODY. Conditions of Table 1 assure that most thirdquadrant current flow is via D BODY. Avalanche breakdown is more accurately modeled by the clamp circuit containing D 1. Table 1 in combination with Figures 2, 3, 4 and 5 provides the required empirical inputs. Table 2 lists the preferred algorithm for parameter extraction. TABLE 1. EMPIRICAL INPUTS MOSFET Enhancement mode; W = L = 1µm; K P (Figure 2); V TO (Figure 2); C s = ; I DSO = IE 12 JFET Depletion mode; areas factor = 1; B = K P (Figure 2); V TO = V PINCH (Figure 5); C s = diode lifetime = R SERIES = ; diode ideality factor = 1., I DSO = IE 2 BODY DIODE I S from Figure 4; Ideality Factor = 1.; R from Figure 4 (must be very much greater than R D ); C (from C OSS ); lifetime = best fit to T RR D 1 I S = arbitrary; C = lifetime = ; ideality factor = best lowcurrent fit; R = best highcurrent fit D 2 I S = 1E 8; C = lifetime = R = ; ideality factor =.3 R S Figure 2. R DRAIN Figure 3. L S Approximately (5L) ln (4 L/d) nh; L and d are source wire inches. V PINCH V TO of JFET. V BRK Avalanche voltage. C 1 From Figure 5. C 2 Maximum from Figure 5. C 3 Minimum from Figure Fairchild Semiconductor Corporation Application Note 759 Rev. A1

2 Application Note 759 I DS R S 25 I DS (AMPERES 1/2 ) SLOPE AT K P V DS > V GS (SATURATED REGIME) 2 SLOPE R D R S 5 V THRESHOLD FIGURE 2. SQUARE ROOT OF DRAIN CURRENT vs GATE VOLTAGE DEFINES V THRESHOLD, K P, AND R S FIGURE 3. DRAIN CURRENT vs DRAIN VOLTAGE WITH CONSTANT GATE VOLTAGE DEFINES ON RESISTANCE V GS = I MAX R 135 R DRAIN = Ω I G = 1mA TEST CIRCUIT (SEE REF. 1) 9. LOG I D (AMPERES) KT SLOPE = q = 6mV/DECADE 9 SLOPE = I G /(C 1 C 2 C 3 ) GATE PLATEAU VOLTAGE 6. I S 45 SLOPE I G /C 2 SLOPE I G /C 1 TRIAL V pinch I D R DSON TIME (µs) FIGURE 4. THIRDQUADRANT OPERATION DEFINES I S AND R OF DIODE D BODY TABLE 2. PREFERRED ALGORITHM FOR PARAMETER EXTRACTION 1. Determine K P of lateral MOS 2. Determine V TH of lateral MOS 3. Determine C 1 4. Determine C 1 C 2 C 3 5. Determine R DS 6. Assign B of JFET = x K P of lateral MOS 7. Use trial V PINCH 8. Use C 2 (Maximum), C 3 (Minimum) are curvefit C s 9. Adjust V PINCH to fix gate voltage plateau FIGURE 5. DRAIN AND GATE VOLTAGE vs TIME DETERMINE C 1, C 2, C 3 AND V PINCH. Results Figure 6 and Figure 7 compare measured static data to calculated transfer curves and output curves. Calculated staticoutput curves are shown in Figure 8 and Figure 9 for thirdquadrant range, including avalanche. Calculated switching data is compared to measured switching curves 1,2 in Figure and Figure 11. Calculated bodydiode recovery curves are shown in Figure Fairchild Semiconductor Corporation Application Note 759 Rev. A1

3 Application Note FIGURE 6. DRAIN CURRENT vs GATE VOLTAGE (NOTE SQUARE ROOT SCALE) CURVE vs POINTS FIGURE 7. DRAIN CURRENT vs DRAIN VOLTAGE FOR CONSTANT VALUES OF GATE VOLTAGE CURVES vs POINTS FIGURE 8. THIRDQUADRANT DRAIN CURRENT vs DRAIN VOLTAGE WITH CONSTANT POSITIVE GATE VOLTAGE () FIGURE 9. FIRSTQUADRANT DRAIN CURRENT vs DRAIN VOLTAGE, V GS = CONSTANT. NOTE AVALANCHE BREAKDOWN () R DRAIN = Ω V SUPPLY = 37.5V, 75V, 112.5V, V TEST CKT. (SEE REF. 1) V V 5Ω Ω 5Ω TIME (µs) TIME (ns) FIGURE. DRAIN AND GATE VOLTAGE vs TIME FOR CONSTANT GATE CIRCUIT CURVES vs POINTS FIGURE 11. DRAIN AND GATE VOLTAGE vs TIME FOR STANDARD SWITCHING CIRCUIT CURVES vs POINTS 22 Fairchild Semiconductor Corporation Application Note 759 Rev. A1

4 Application Note 759 I D (AMPERES) 4A. 4A V GS = Conclusion An equivalentcircuit model for powermosfets, that is suitable for use with the SPICE CAD program, has been demonstrated. The model is compatible with all versions of SPICE presently available without modification to the program s internal code. The model addresses static and dynamic behavior of first and thirdquadrant operation, including avalanche breakdown, and is empirical in nature. All necessary input parameters may be inferred from data sheets or simple terminal measurements. Excellent agreement has been obtained between measured and simulated results TIME (ns) FIGURE 12. THIRDQUADRANT DIODE RECOVERY vs TIME CURVE () References [1] Wheatley Jr., C. F. and Ronan Jr., H. R., Switching Waveforms of the L 2 FET: A 5Volt GateDrive Power MOSFET, Power Electronic Specialists Conference Record, June 1984, p. 238 [2] Ronan Jr., H. R. and Wheatley Jr., C. F., Power MOS FET Switching Waveforms: A New Insight, Proceedings of Powercon II, April 1984, p. C3 [3] Nienhaus, H. A., Bowers, J. C., and Herren Jr., P. C., A High Power MOSFET Computer Model, Power Conversion International, January 1982, p Fairchild Semiconductor Corporation Application Note 759 Rev. A1

5 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E 2 CMOS TM EnSigna TM FACT FACT Quiet Series STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein: 1 Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms FAST â FASTr FRFET GlobalOptoisolator GTO HiSeC I 2 C ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC â OPTOPLANAR PACMAN POP Power247 PowerTrench QFET QS 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness Datasheet Identification Product Status Definition â QT Optoelectronics Quiet Series SILENT SWITCHER â SMART START SPM STAR*POWER Stealth SuperSOT 3 SuperSOT 6 SuperSOT 8 SyncFET TinyLogic TruTranslation UHC UltraFET â VCX Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development Specifications may change in any manner without notice This datasheet contains preliminary data, and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev H5

Features. (Note 1b) 1.2. (Note 1c) 1.0. (Note 1c) 125

Features. (Note 1b) 1.2. (Note 1c) 1.0. (Note 1c) 125 NDS97 V P-Channel PowerTrench MOSFET May NDS97 General Description This P-Channel MOSFET is a rugged gate version of Fairchild Semiconductor s advanced PowerTrench process. It has been optimized for power