FX806A AUDIO PROCESSOR

Transcription

1 FX86A AUDIO PROCESSOR CALIBRATION INPUT (TX) MIC. IN INPUT PROCESS (RX) AUDIO IN POWER SUPPLY MIC. & AMPS LOW & HIGHPASS FILTERS DE-EMPHASIS FILTER CHIP SELECT SENSE GAIN SET SERIAL CLOCK C-BUS INTERFACE COMMAND DATA SENSE SENSE PRE-EMPHASIS LIMITING FILTERING GAIN SETTING MAIN PROCESS MAIN PROCESS PRIMARY and SECONDARY AUDIO INPUTS Voice. Sub-/Audio Tone. FFSK. etc. SUM MODULATION SUMMING AMP MOD. IN ATTENUATOR ATTENUATOR MODULATION TRANSMITTER MODULATION DRIVES MODULATION 2 PUT DRIVES indicates logic control XTAL/CLOCK XTAL CLOCK GENERATOR BUFFER ATTENUATOR LOUDSPEAKER AUDIO To EXTERNAL AUDIO PROCESSES EXTERNAL AUDIO PROCESS IN Fig. FX86A Audio Processor Brief Description Intended primarily to operate as the Audio Terminal of Radio Systems using the DBS 8 Digitally-integrated Baseband System, the FX86A is a PMR Audio Processor which meets EIA and CEPT audio specifications. Using a unique filter line-up, the FX86A offers lower distortion versus modulation level figures than conventional filter/limiter configurations. The FX86A is a half-duplex device whose signal paths and level-setting elements are dynamically configured and adjusted by digital information sent from the Radio µcontroller using C-BUS hardware and software protocol. Figure shows a complete functional block diagram of the FX86A signal paths which can be viewed as 3 sections: Input Process Selectable transmit or receive input paths. The transmit path with low-noise input and amplifiers and bandpass filtered stages provides good signalto-noise performance at low input levels and minimum distortion for high-drive modulation signals. De-emphasis is software selectable at the Rx Audio Input for FM or PM radio configurations. This initial audio, after in-line gain adjustment, is available for switching to either external audio processes (such as scrambling) or internally to the Main Process stages. Publication D/86A/3 July 994 Main Process Conditioning for Input or External Process signals with gain/pre-emphasis, high and lowpass switched capacitor filters and a transmitter deviation limiter. The Main Process Output may be switched to V BIAS. Summation and Output Drives Main voice audio from the Main Process is combined with signalling and data from other DBS 8 facilities, to provide the composite (in and outband) signal for the digitally adjustable Transmitter Modulation Drives. Received audio is level (volume) adjusted for output to loudspeaker circuitry. Signal-level stability and therefore output accuracy, of the FX86A is maintained by a voltage-controlled gain system () with specific gain sensors that are selected automatically by the Internal/External Mode Command. The system permits high deviation with low distortion. This is achieved by reducing the path gain (and so reducing the distortion introduced by the Peak Deviation limiter) when the input signal is large. Signal levels can be controlled to provide dynamiccompensation for such factors as temperature drift, VCO non-linearity, etc. FX86A audio output stages can be completely disabled or the whole microcircuit placed into a Powersave mode, leaving only clock and C-BUS circuitry active. The FX86A is a low-power, -volt CMOS integrated circuit and is available in 24-pin DIL cerdip and 24-pin/lead plastic SMD packages.

2 Pin Number Function FX86A J/LG/LS Xtal: The output of the on-chip clock oscillator. External components are required at this output when a Xtal circuit is employed. See Figure 2, INSET 2. 2 Xtal/clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock should be connected here. See Figure 2, INSET 2. This clock provides timing for on-chip elements, filters etc. 3 Serial Clock: The C-BUS, serial data loading clock input. This clock, produced by the µcontroller, is used for transfer timing of Command Data to the Audio Processor. See Timing diagrams and System Support Document. 4 Command Data: The C-BUS, serial data input from the µcontroller. Command Data is loaded to this device in 8-bit bytes, (B7) first, and (B) last, synchronized to the Serial Clock. The Command/Data instruction is acted upon at the end of loading the whole instruction. Command information is detailed in Tables, 2, 3, 4 and. See Timing diagrams and System Support Document. Chip Select (CS): The C-BUS, data loading control function. This input is provided by the µcontroller. Command Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing diagrams and System Support Document. 6 Out: The output of the relevant sensor. This output, with external attack and decay setting components, should be connected as in Figures 2 and 3, to the In pin. 7 Rx Audio In: The audio input to the FX86A from the radio receiver's demodulator circuits. This input, which requires to be a.c. coupled with capacitor C 2, is selected by a Control Command bit. 8 In: The gain control signal from the selected sensor ( Out) to the Input Process Voltage Controlled Amplifier. operation is enabled via a Mode Command (Bit). Individual sensors, automatically selected, permit gain control from either the Input Process or an external process. External attack and decay setting components should be applied as recommended in Figures 2 and 3. 9 V BIAS : The output of the on-chip analogue circuitry bias system, held internally at V DD /2. This pin should be decoupled to by a capacitor C, See Figure 2. Mic In (+): The non-inverting input to the microphone Op-Amp. This input requires external components for Op-Amp gain/attenuation setting as shown in Figure 2, INSET. Mic In ( ): The inverting input to the microphone Op-Amp. This input requires external components for Op-Amp gain/attenuation setting as shown in Figure 2, INSET. 2 : Negative supply rail (GND). 2

3 Pin Number Function FX86A J/LG/LS 3 Mic Out: The output of the microphone Op-Amp, used with the Mic In ( ) input to provide the required gain/attenuation using external components as shown in Figure 2. The external components shown are to assist in the use of this amplifier with either inverting or non-inverting inputs. During Powersave (Volume Command) this output is placed at. 4 Processed Audio In: The input to the device from such external audio processes as Voice Store and Retrieve or Frequency Domain Scrambling. This input, which requires to be a.c. coupled with a capacitor, C 3, is selected by a Mode Command bit. External Audio Process: The buffered output of the Input Processing stage. For further external audio processing prior to re-introduction at the Processed Audio In pin. 6 CALibration Input: A unique input, intended to be used for dynamic balancing of the modulator drives and for measuring Deviation Limiter levels. A CUE (beep) input from the FX83 Audio Tone Processor can be entered on this line. This input is selected via a Mode Command bit ( H ) and is self-biased. 7 Main Process Out: The output of the Main Process stage. This output is summed with additional system inputs as required (Audio, Sub-Audio Signalling, FFSK See System Overview) in the on-chip Modulation Summing Amplifier. External components as shown in Figure 2 should be used as required. 8 9 Sum In: The input and output terminals of the on-chip Modulation Summing Amplifier. External components are required for input signals, with gain/attenuation setting as shown in Figure 2. For single-signal, no-gain requirements, Main Process Out may be linked directly to Modulation In. Sum Out: 2 Modulation In: The final, composite modulating signal to VCO (Mod ) and Reference (Mod 2) Output Drives. 2 Audio Output: The processed audio signal output intended as a received audio (volume) output. Though normally used in the Rx mode, operation in Tx is permitted. The output level of this attenuator is controlled via a Volume Set command. During Powersave this output is placed at. 22 Modulation Drive: The drive to the radio modulator Voltage Controlled Oscillator (VCO), from the composite audio summing stage. 23 Modulation 2 Drive: The drive to the radio modulator Reference Oscillator, from the composite audio summing stage. NOTE: These VCO output attenuators are individually adjustable using the Modulator Levels command. During Powersave these outputs are placed at. 24 V DD : Positive supply rail. A single, stable + volt supply is required. Levels and voltages within the Audio Processor are dependant upon this supply. 3

4 Analogue Application Information External Components V DD C 9 R 6 XTAL SEE INSET 2 XTAL/CLOCK SERIAL CLOCK COMMAND DATA CHIP SELECT RX AUDIO IN C 2 IN R V BIAS MIC. IN (+) MIC. IN (-) FX86A J V DD MODULATION 2 DRIVE MODULATION DRIVE AUDIO MOD IN SUM SUM IN MAIN PROCESS CALIBRATION IN EXTERNAL AUDIO PROCESS PROCESSED AUDIO IN C MIC. SEE INSET R 8 R 7 C 3 EXTERNAL SIGNAL AND DATA INPUTS R 9 R R R 2 C 8 C C C 4 MIC. IN (+) C 2 R 2 C R MIC. IN (-) R 4 + V BIAS - 3 FX86A J MIC. C 6 XTAL X 2 XTAL/CLOCK C 7 FX86A J R 3 C 3 INSET INSET 2 Fig.2 Recommended External Components Component Value R =.kω R 2.kΩ R 3 2.kΩ R 4 2.kΩ R.kΩ R 6 2.2MΩ R 7 kω R 8 kω kω R 9 R = kω R kω R 2 2.2MΩ C 47nF C 2 47nF C 3 27pF C 4 27pF C.µF 33pF C 6 C 7 = 6pF C 8.µF C 9.µF C.µF C 22pF C 2 nf C 3.nF X 3 4.MHz Tolerance: R = ±%. C = ± 2% Notes To demonstrate the versatility of the Mic. inputs, Input Op-Amp gain/attenuation components for a voltage gain of 6. are shown (INSET ) in a differential configuration. Components for a single (+ or -) input may be employed. Resistor values R 7 to R (summation components) are dependant upon application and configuration requirements. Xtal circuit capacitors C 6 (C D ) and C 7 (C G ) shown (INSET 2) are recommended in accordance with CML Application Note D/XT/2 December 99. Circuit drive and drain resistors are incorporated on-chip. Operation of any CML microcircuit without a Xtal or clock input may cause device damage. To minimise damage in the event of a Xtal/drive failure, it is recommended that the power rail (V DD ) is fitted with a current limiting device (resistor or fast reaction fuse). Components Calculations Figures 2 and 3 Provided R >>.kω and R 6 = R 2 >>R Then: Attack Time (T A ) = R x C 8 Decay Time (T D ) = R 6 x C 8 2 4

5 Analogue Application Information... The Gain Control System EXTERNAL INTEGRATION COMPONENTS R R 6 V DD IN C 8 R 2 MIC. HI PEAK DETECTOR Tx DRIVES MIC. IN Tx HI/LO PEAK DETECTOR MIC. IN VOLTAGE CONTROLLED () AMPLIFIER Tx INPUT PROCESS MAIN PROCESS Rx DRIVE To EXTERNAL AUDIO PROCESSES PROCESSED AUDIO IN Fig.3 Sensors and Timing Components (part of Fig.4) CAL INPUT Tx gain control of the FX86A is by of 2 selectable signal peak detectors whose output is fed via external integrating components to the Voltage Controlled Amplifier positioned in the Tx Input Process Path. The integrated level to the In pin causes the Voltage Controlled Amplifier gain to be reduced. attack and decay calculations are described at the foot of the proceeding page. The FX86A automatically chooses the appropriate peak detector when the signal path is set by a Mode Command. The Hi/Lo Peak Detector is employed when external audio processes are used. The Hi Peak Detector is employed when external audio processes are not used. 2 Limiter Only Output Distortion (%) 2 6% Output Deviation 38mVrms Internal Path with Pre-emphasis Circuit Elements set to Input Level for = 7.mV p-p Input Frequency =.khz Output Deviation = 6% = Hi-Peak & Limiter Mic. Input Level (Vp-p) Fig.4 Distortion vs Mic. Input Level Suggested Calibration Methods To effectively null all internal microcircuit tolerances, the following initial calibration routine is suggested: Tx Calibration : From Mic. In to Modulator Drives Out Rx Calibration: From Rx Audio In to Audio Output Disable Peak Detectors (Mode Command). Set Transmitter Drives to (Mod Levels Set). Pre-emphasis may be employed as required (Control Command). Set Input Level Amp to (Control Command). () Mic. In = 2mVrms at khz; Set Process Gain Amp for output of 44mV p - p (% deviation). (2) With Process Gain Amp set as (); Mic In = 2mVrms at khz, set Input Level Amp for output level of 38 mvrms (6% deviation). +2. Input Level (db) Set Audio Output Drive to (Volume Set). Leave Process Gain Amp set as In () (above). (3) With Rx Audio In level of between 4mVrms and 38mVrms (see Specification page), at khz, set the Input Level Amp for an output level of 38mVrms.

6 6 PLMR Audio Processor Explanatory Block Diagram VDD MIC. IN EXTERNAL INTEGRATION COMPONENTS EXTERNAL SIGNAL MIXING EXTERNAL SIGNAL/DATA INPUTS Gain Set By External Components MIC. IN MIC. IN MIC. OP-AMP Rx (DEMOD) AUDIO IN VBIAS VBIAS AMP -24dB to 6dB -6dB/oct INPUT khz DE-EMPHASIS INPUT PROCESS INPUT SELECT INPUT H.P.F. C4 M4 Tx Rx C to -4dB INPUT LEVEL AMP H.P.F. HI/LO-PEAK DETECTOR +VE & -VE PEAKS H.P.F. M7 M3 HI-PEAK DETECTOR +VE PEAKS C M6 ON OFF DEVIATION LIMITER PROCESS L.P.F. MAIN PROCESS MAIN PROCESS V6 M dB to -4dB PROCESS GAIN AMP Tx Rx VBIAS SUM IN VBIAS SUM MODULATION SUMMING AMPLIFIER Tx MODULATION IN to -2.4dB db db C6 (ENABLE) to -6.2dB db db D() -4 D() -4 MOD TRANSMITTER MODULATOR DRIVES MOD 2 XTAL/CLOCK XTAL CLOCK GENERATOR M3 PROCESS L.P.F. khz PRE-EMPHASIS C7 (ENABLE) PUT DRIVES V - 4 VSS BUFFER AMP db db AUDIO PUT SERIAL CLOCK VBIAS V BIAS to -48. COMMAND DATA CHIP SELECT C-BUS INTERFACE AND CONTROL LOGIC NOTES PROCESSED AUDIO IN = Controlling Logic Bit C = Control Command M = Mode Command D = Mod 2 D = Mod V = Volume Set EXTERNAL AUDIO PROCESS CALIBRATION INPUT Level = 38mVrms (6% Deviation). Fig. PLMR Audio Processor Facilities

7 Controlling Protocol Control of the functions and levels within the FX86A PLMR Audio Processor is by a group of Address/Commands and appended data instructions from the system µcontroller to set/adjust the functions and elements of the FX86A. The use of these instructions is detailed in the following paragraphs and tables. Command Address/Command (A/C) Byte Command Table Assignment Hex Binary Data General Reset Control Command + byte 2 Mode Command + byte 3 Mod. Levels Set bytes 4 Volume Set 3 + byte Table C-Bus Address/Commands In C-BUS protocol the FX86A is allocated Address/ Command (A/C) values H to 3 H. C-BUS Command, Mode, Modulation and Volume assignments and data requirements are given in Table and illustrated in Figure (Main Block Diagram). Each instruction consists of an Address/Command (A/C) byte followed by a data instruction formulated from the following tables. Commands and Data are only to be loaded in the group configurations detailed, as the C-BUS interface recognises the first byte after Chip Select (logic ) as an Address/ Command. Function or Level control data, which is detailed in Tables 2, 3, 4 and, is acted upon at the end of the loaded instruction. Upon Power-Up the value of the bits in this device will be random (either or ). A General Reset Command ( H ) will be required. This command is provided to reset all devices on the C-BUS and has the following effect on the FX86A. Control Address Command Loaded as H Mode Address Command Loaded as H Volume Set Loaded as H Control Command (Preceded by A/C H ) Mode Command (Preceded by A/C H ) Setting Control Bits Setting Mode Bits Bit 7 Transmitted First Audio Output (Rx) Disabled Bit 7 Transmitted First Drive Source Signals Calibration 6 Modulation Drives Disabled 6 Deviation Limiter Disabled Pre-Emphasis By-Pass Disabled 4 Input Select Rx Audio In Mic. In 4 De-Emphasis By-Passed 3 2 Input Level Set Input Amp Disabled Signal Select Internal External Process Gain Set Table 2 Control Commands Table 3 Mode Commands 7

8 Modulator Levels (Preceded by A/C2 H ) Volume Set (Preceded by A/C3 H ) Setting Byte Byte Modulator Drives First byte for transmission Must be Mod. Attenuation 2.4dB 2..6dB.2dB.8dB.4dB. 9.6dB 9.2dB 8.8dB 8.4dB dB 7.2dB 6.8dB 6.4dB 6..6dB.2dB 4.8dB 4.4dB dB 3.2dB 2.8dB 2.4dB 2..6dB.2dB.8dB.4dB Last byte for transmission Must be Mod. 2 Attenuation 6.2dB 6..8dB.6dB.4dB.2dB. 4.8dB 4.6dB 4.4dB 4.2dB dB 3.6dB 3.4dB 3.2dB dB 2.6dB 2.4dB 2.2dB 2..8dB.6dB.4dB.2dB..8dB.6dB.4dB.2dB Setting Table Volume Set Volume Set Transmitted First Main Process Out Biased Powersave Chip Powersaved Volume Set Attenuation Off dB 44.8dB 43.2dB 4.6dB dB 36.8dB 3.2dB 33.6dB dB 28.8dB 27.2dB 2.6dB dB 2.8dB 9.2dB 7.6dB dB 2.8dB.2dB 9.6dB dB 4.8dB 3.2dB.6dB Command Loading Address/Commands and data bytes must be loaded in accordance with the information given in Figure 6 (Timing ). The Powersave function is instigated by bit of the Volume Set Command (Table ). During Powersave, all internal elements except the Clock Generator and C-BUS Interface are off, with the Mic Op- Amp and Output Drive stage outputs connected to. Modulator Drives are controlled separately, but the whole two-byte Modulator Drive command must be loaded for each required adjustment. Chip Select must be held at a logic for the period t CSOFF between transactions. Table 4 Modulator Drive Levels 8

9 Command Loading and Timing CHIP SELECT t CSOFF t CSE t NXT t NXT SERIAL CLOCK t CSH COMMAND DATA t CK ADDRESS/COMMAND BYTE Inter-byte period logic level is not important. FIRST DATA BYTE LAST DATA BYTE Fig.6 C-BUS Timing Information Parameter Min. Typ. Max. Unit t CSE 2. µs t CSH 4. µs t CSOFF 2. µs t NXT 4. µs t CK 2. µs Notes () Command Data is transmitted to the peripheral (bit7) first, (bit) last. (2) Data is clocked into the peripheral on the rising clock edge. (3) Loaded data instructions are acted upon at the end of each individual, loaded byte. (4) To allow for differing µcontroller serial interface formats, the FX86A will work with either polarity Serial Clock pulses. Sets the Control, Mode and Volume Commands to H GENERAL RESET TABLE 2 CONTROL COMMAND DATA BYTE TABLE 3 MODE COMMAND DATA BYTE TABLE VOLUME SET DATA BYTE TABLE 4 MODULATOR LEVELS SET 2 DATA BYTES BYTE (loaded first) BYTE (loaded last) Fig.7 Examples of Command Data Configurations To assist in rapid setting, the quick-reference guide below should be used together with Figure. Control A/C = H Bit 7 Audio Out (Rx) Enable 6 Modulator Drive Enable Pre-Emphasis Enable 4 Input Select (Rx/Tx) 3 Input Level Set (-4dB to ) Mode A/C = H Bit 7 Drive Source 6 Deviation Limiter Enable Enable 4 De-Emphasis Enable 3 Signal Select 2 Process Gain Set (-4dB to 3dB) Table 6 Quick-Reference to Command Allocations Modulator Levels A/C = 2 H Byte Bit 7 4 Mod Attenuation ( to 2.4dB) Byte Mod 2 Attenuation ( to 6.2dB) Volume Set A/C = 3 H Bit 7 6 Powersave 4 Volume Set Attenuation ( to 48dB) 9

10 Specification Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -.3 to 7.V Input voltage at any pin (ref = V) -.3 to (V DD +.3V) Sink/source current (supply pins) +/- 3mA (other pins) +/- 2mA Total device T AMB 2 C 8mW Max. Derating mw/ C Operating temperature range: FX86A J -4 C to +8 C (cerdip) FX86A LG/LS -4 C to +8 C (plastic) Storage temperature range: FX86A J - C to +2 C (cerdip) FX86A LG/LS -4 C to +8 C (plastic) Operating Limits All device characteristics are measured under the following conditions unless otherwise specified: V DD =.V. T AMB = 2 C. Xtal/Clock f = 4.MHz. Audio Level ref: = khz (6% deviation, FM). Characteristics See Note Min. Typ. Max. Unit Static Values Supply Voltage 4... V Supply Current (All Elements ) 8. ma (Maximum Powersave).7 ma C-BUS Interface Input Logic 3. V Input Logic. V Input Leakage Current (logic or ) -.. µa Input Capacitance 7. pf Dynamic Values Overall Performance Microphone Input 4, 2. mvrms Rx Audio In 6, 4 38 mvrms Output Drive Levels For 6% Deviation, mvrms For % Deviation, 7, 8,44 mv p - p Passband Frequencies Hz Passband Ripple db Stopband Attenuation, 3 f = Hz. 2. db f = 34Hz 2. db f = 6Hz db f = 8Hz to 2,Hz 6. db Signal Path Noise Rx -6. dbp Rx -. db Tx -. dbp Tx -4. db Distortion. % Circuit Elements Figure Mic Amp or Mod Summation Amp Open Loop Gain. db Bandwidth 2. khz Input Impedance. MΩ Output Impedance (Open Loop) 6. kω (Closed Loop) 6 Ω De-emphasis Slope -6. db/oct. Gain (at.khz) db Input Impedance kω Voltage Controlled Gain Amp Gain (Non-Compressing) 6. db (Full Compression) -24. db In Input Impedance. MΩ

11 Specification... Characteristics See Note Min. Typ. Max. Unit Peak Detectors Output Impedance - Logic (Compress). kω - Logic. MΩ Hi/Lo Peak Detector Thresholds,3 mv p - p Hi Peak Detector Threshold 6 mv +ve pk Input (Low + Highpass) Filter Gain (at.khz) -.. db Input Level Amp Nominal Adjustment Range -4.. db Error of any Setting -.. db Step Size.7..2 db External Audio Buffer Gain -.. db Pre-emphasis (Main Process and ) Slope 6. db/oct. Gain (at.khz). db Process Highpass Filter Gain (at.khz) -.. db Deviation Limiter Threshold,3 mv p - p Gain -.. db Process Lowpass Filter Gain (at.khz) -.. db Process Gain Amp Nominal Adjustment Range db Error of any Setting -.. db Step Size.7..2 db Output Impedance 6 Ω Transmitter Modulator Drives Input Impedance. kω Mod. Attenuator Nominal Adjustment Range 2.4 db Error of any Setting -.. db Step Size db Output Impedance 6 Ω Mod.2 Attenuator Nominal Adjustment Range 6.2 db Error of any Setting db Step Size..2.3 db Output Impedance 6 Ω Audio Output Attenuator Nominal Adjustment Range 48. db Error of any Setting -.. db Step Size.6 db Output Impedance 6 Ω Miscellaneous Impedances Processed Audio Input kω Calibration Input kω External Process Out Ω Rx with De-Emphasis By-Pass 2. kω Notes. Between Mic. or Rx inputs to Modulator or Audio outputs. 2. The deviation from the ideal overall response that includes the pre- or de-emphasis slope. 3. Excluding the effect of the pre- or de-emphasis slope. 4. Producing an output of with the Mic. Op-Amp set to 6dB (as shown in Figure 2) and the Modulator Drives set to.. With Output Drives set to and the system calibrated, as described in the Application pages. 6. Input level range for output, by adjustment of the Input Level Amp. 7. It is recommended that these output levels will produce 6% or % deviation in the transmitter. 8. With the microphone input level 2 above the level required to produce at the Output Drives. 9. Using external components recommended in Figure 2.. In a 3kHz bandwidth.. dbp = Psophometrically weighted measurement.

12 Package Outlines The FX86A is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section of this document. Pin identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. Handling Precautions The FX86A is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX86A J 24-pin cerdip DIL (J4) FX86A LG 24-pin quad plastic encapsulated bent and cropped (L) NOT TO SCALE NOT TO SCALE Max. Body Length Max. Body Width 32.3mm 4.8mm Max. Body Length Max. Body Width.2mm.2mm FX86A LS 24-lead plastic leaded chip carrier (L2) Ordering Information NOT TO SCALE FX86A J 24-pin cerdip DIL (J4) FX86A LG 24-pin encapsulated bent and cropped (L) FX86A LS 24-lead plastic leaded chip carrier (L2) Max. Body Length Max. Body Width.4mm.4mm CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.

13 CML Microcircuits COMMUNICATION SEMICONDUCTORS CML Product Data In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all % owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. Company contact information is as below: CML Microcircuits (UK)Ltd COMMUNICATION SEMICONDUCTORS Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 ()62 87 Fax: +44 () uk.sales@cmlmicro.com CML Microcircuits (USA) Inc. COMMUNICATION SEMICONDUCTORS 48 Bethania Station Road, Winston-Salem, NC 27, USA Tel: , Fax: us.sales@cmlmicro.com CML Microcircuits (Singapore)PteLtd COMMUNICATION SEMICONDUCTORS No 2 Kallang Pudding Road, 9-/ 6 Mactech Industrial Building, Singapore Tel: Fax: sg.sales@cmlmicro.com D/CML (D)/ February 22