A6800 and A6801. DABiC-5 Latched Sink Drivers

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1 Features and Benefits 3.3 to 5 V logic supply range Up to 0 MHz data input rate High-voltage, high-current outputs Darlington current-sink outputs, with improved low-saturation voltages MOS, TTL compatible inputs Output transient protection Internal pull-down resistors Low-power MOS latches Packages A pin 7.6 mm DIP (A package) 8-pin PL (EP package) Approximate scale : A pin SOIN (L package) 4-pin SOIW (LW package) Description The A6800 and latched-input BiMOS Is merge high-current, high-voltage outputs with MOS logic. The MOS input section consists of 4 or 8 data (D type) latches with associated common LEAR,, and OUTPUT ENABLE circuitry. The power outputs are bipolar NPN Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface Is greatly benefit the simplification of computer or microprocessor I/O. The A6800 Is each contain four latched drivers. Is contain eight latched drivers. The MOS inputs are compatible with standard MOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small D motors, and so forth. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 600 ma and can withstand at least 50 V in the off state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. ontinued on the next page Functional Block Diagram SUPPLY OMMON V DD IN N OUT N LEAR GROUND OUTPUT ENABLE TYPIAL MOS LATH TYPIAL BIPOLAR DRIVE OMMON MOS ONTR OL 680.0H

2 Description (continued) The A6800SA is furnished in a 4-pin DIP with 7.6 mm (0.300 in.) row centers, the A6800SL and SLW in surfacemountable SOIs; and the SEP in a 8-lead PL. These devices are lead (Pb) free, with 00% matte tin plated leadframes. Applications include: Relays Lamps Solenoids Small D motors Selection Guide Part Number Package Packing A6800SA-T* 4-pin DIP 5 per tube A6800SLTR-T 4-pin SOI 500 per reel SEPTR-T 8-pin PL 800 per reel SLWTR-T 4-pin SOI 000 per reel *Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 4, 009. Absolute Maximum Ratings* haracteristic Symbol Notes Rating Units Output Voltage V E 50 V Supply Voltage V DD 7 V Input Voltage Range V IN 0.3 to V DD V ontinuous ollector urrent I 600 ma Operating Ambient Temperature T A Range S 0 to 85 º Maximum Junction Temperature T J (max) 50 º Storage Temperature T stg 55 to 50 º *aution: MOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.

3 Allowable Power Dissipation.5 8-LEAD PL, R JA = 68 /W 4-PIN DIP, R JA = 73 /W PAKAGE POWER DISSIPATION (W) LEAD SOI, R JA = 85 /W 4-LEAD SOI, R JA = 0 /W AMBIENT TEMPERATURE (º) Typical Input ircuit V DD IN 3

4 ELETRIAL HARATERISTIS Unless otherwise noted: T A = 5, logic supply operating voltage V DD = 3.0 to 5.5 V haracteristic Symbol Test onditions V DD = 3.3 V V DD = 5 V Min. Typ. Max. Min. Typ. Max. Output Leakage urrent I EX V OUT = 50 V 0 0 μa Output Sustaining Voltage V E(SUS) I OUT = 350 ma, L = 3 mh V ollector-emitter Saturation Voltage V E(SAT) I OUT = 00 ma V I OUT = 00 ma V I OUT = 350 ma (See note ) V V IN(). 3.3 V Input Voltage V IN(0)..7 V Input Resistance R IN kω Logic Supply urrent I DD() One output on, I OUT = 00 ma.0.0 ma I DD(0) All outputs off μa lamp Diode Leakage urrent I r V r = 50 V μa lamp Diode Forward Voltage V f I f = 350 ma.0.0 V Output Fall Time t f V = 50 V, R = 500 Ω, 30 pf ns Output Rise Time t r V = 50 V, R = 500 Ω, 30 pf ns Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic. Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle. Units Truth Table OUT OUTPUT N IN N LEAR ENABLE t- t X OFF 0 0 X ON X X X X OFF X X X X OFF X ON ON X OFF OFF X = irrelevant t- = previous output state t = present output state 4

5 Timing Requirements and Specifi cations (Logic Levels are V DD and Ground) LEAR G A B B A B IN N H H D E F E OUT N HIGH = ALL OUTPUTS DISABLED (OFF) OUTPUT ENABLE 50% t en(bq) OUT N t dis(bq) 0% t r DATA 90% 50% t f Key Description Time (ns) A Minimum data active time before Strobe enabled (Data Set-Up Time) 5 B Minimum data active time after Strobe disabled (Data Hold Time) 5 Minimum Strobe pulse width 50 D Maximum time between Strobe activation and transition from output on to output off* 500 E Maximum time between Strobe activation and transition from output off to output on* 500 F Maximum time between lear activation and transition from output on to output off* 500 G Minimum lear pulse width 50 H Minimum data pulse width 00 t dis(bq) Output Enable to output off delay* 500 t en(bq) Output Enable to output on delay* 500 *onditions for output transition testing are: V = 50 V, V DD = 5 V, R = 500 Ω, 30 pf. NOTE: Information present at an input is transferred to its latch when the is high. A high LEAR input will set all latches to the output off condition regardless of the data or input levels. A high OUTPUT ENABLE will set all outputs to the off contdition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. 5

6 A6800 L Package 4 A6800 A-4 Package LEAR 4 OUTPUT ENABLE V DD 3 SUPPLY IN 3 OUT IN 4 5 LATHES 0 OUT 6 9 GROUND 7 8 OMMON Dwg. PP-04A Note: The A6800 SOI and DIP packages are electrically identical and share a common terminal number assignment. EP Package LW Package IN 5 4 N 3 ST N LEAR OUTPUT ENABLE 8 OE SUPPLY 7 V DD 6 N 5 OUT LEAR IN IN V DD OUTPUT ENABLE SUPPLY OUT OUT IN IN LATHES 4 3 OUT OUT 5 IN LATHES OUT 5 IN OUT 6 IN OUT 6 IN 7 9 OUT 7 IN OUT 7 N N K N IN OUT 8 IN GROUND 6 LAMP DIODE OMMON 7 8 OUT 8 Dwg. PP-037 GROUND NO ONNETION 4 N N 3 OMMON NO ONNETION Dwg. PP-05-6

7 TYPIAL APPLIATION UNIPOLAR STEPPER-MOTOR DRIVE +30 V OUTPUT ENABLE (ATIVE LOW) LEAR IN IN LATHES 4 V DD V DD OUT OUT 7 8 A6800S A +30 V Dwg. No. B-537 UNIPOLAR WAVE DRIVE UNIPOLAR -PHASE DRIVE IN IN IN IN OUT OUT OUT OUT Dwg. GP-060 Dwg. GP-060-7

8 Package A (A6800) 4-pin DIP A ± MAX SEATING PLANE For Reference Only Dimensions in millimeters (reference JEDE MS-00 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal # mark area 8

9 Package EP () 8-pin PL.45±0.3.5± A 5.± ±0.3.5± ± ± MIN 8X SEATING PLANE 0.43± ± ±0.36 For Reference Only (reference JEDE MS-08 AB) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal # mark area 9

10 Package L (A6800) 4-pin SOIN ±0.0 4 ± ±0.04 A 3.90 ± ± B.75 PB Layout Reference View 4X 0.0 SEATING PLANE SEATING PLANE GAUGE PLANE 0.4 ± MAX For Reference Only Dimensions in millimeters (reference JEDE MS-0 AB) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal # mark area B Reference pad layout (reference IP SOI7P600X75-4M) All pads a minimum of 0.0 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances Package LW () 4-pin SOIW 5.40± ± ± ± A X 0.0 SEATING PLANE SEATING PLANE GAUGE PLANE B PB Layout Reference View 0.4 ± MAX 0.0 ±0.0 For Reference Only (Reference JEDE MS-03 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal # mark area B Reference pad layout (reference IP SOI7P030X65-4M) All pads a minimum of 0.0 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances 0

11 opyright , The products described here are manufactured under one or more U.S. patents or U.S. patents pending. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, assumes no responsibility for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website:

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