Extending IEEE Std Analog Boundary Modules to Enhance Mixed-Signal Test

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1 Board-Level Test Technologies Extending IEEE Std Analog Boundary Modules to Enhance Mixed-Signal Test Uroš Kač and Franc Novak Jozef Stefan Institute Florence Azaïs, Pascal Nouet, and Michel Renovell LIRMM Editor s note: Will it or won t it? The 999 IEEE 49.4 Standard for a Mixed-Signal Test Bus is on the cusp of industrial acceptance, but it s not clear whether industry will pick it up. This study, by two leading European research institutes, delves into the details of hardware implementation and, in so doing, contributes to the growing literature on this topic. R.G. (Ben) Bennetts, Bennetts Associates INCREASINGLY ENSE and complex electronic designs have made established in-circuit test (ICT) techniques more costly and difficult to implement. Several electronic systems manufacturers, such as Philips and IBM, have proposed an innovative boundary scan method to improve design controllability and observability. The method is based on ICT techniques, but it substitutes physical nails with an on-chip shift register placed around the IC core boundary. This boundary scan register captures IC input signals and applies test vectors on IC outputs through its parallel I/Os. Test data is shifted in and out through a simple serial interface, eliminating the need for direct physical access. In 990, as part of the Joint Test Action Group s (JTAG) initiative, the IEEE adopted the approach as IEEE Because IEEE 49. addressed only digital circuits, designers soon began developing equivalent test structures for mixed-signal circuits and corresponding measurement methodologies. 3 Standardization efforts on an IEEE-49.- compatible test bus that would improve mixed-signal design testability at both the device and the assembly level led to the IEEE 49.4 (known as ot 4) standard in The IEEE 49. boundary scan standard has become a widely accepted design for digital circuits, with support from component manufacturers as well as EA tool and test equipment providers. Its mixed-signal twin, on the other hand, has had a much harder time finding its way into real-life applications. Although research has focused on IEEE 49.4, 5,6 and technology demonstrator chips for evaluating its proposed features exist, 7,8 ot 4 lacks support in standard catalog devices, making it difficult for designers to include a standardized mixed-signal test infrastructure in their systems. The absence of commercial ot-4-compliant devices could be due to the test infrastructure s complexity and its potential impact on proven analog and mixed-signal designs. The benefits of including overhead logic in the circuit must justify the effort required to do so. For example, applications aided IEEE 49. s acceptance by demonstrating its value not only in the design testability domain but also in areas such as design validation, debugging, and in-system configuration of programmable devices. 9 The work of Sunter and colleagues on a general-purpose ot-4-compliant IC attempts to improve the standard s status. 9,0 As designers demonstrate the benefits of practical mixed-signal designs and present interesting applications based on the ot 4 infrastructure, interest in the standard will increase. Several researchers have already reported innovative ot-4-based measurement procedures. 9,,2 We describe a ot 4 test chip with extensions to the original 49.4 test infrastructure that expands possible practical applications of the standard /03/$ IEEE Copublished by the IEEE CS and the IEEE CASS IEEE esign & Test of Computers

2 Implementing the ot 4 test chip We approached the design of the ot 4 test chip in two stages. Our preliminary chip, shown in Figure, adheres to the standard IEEE 49.4 architecture. Thus, we can assess the actual characteristics of complex mixed-signal cells analog boundary modules (ABMs) and a test bus interface circuit (TBIC) and identify possible design inefficiencies and necessary modifications. To simplify design debugging, we implemented the test access port (TAP) controller, instruction and bypass registers, and decoder off chip with a programmable logic device (PL). The design follows schematic representations of the boundary scan register modules proposed in the IEEE 49.4 standard. We implemented three main cells: the ABM, the TBIC, and the test control circuitry, each comprising several submodules. Because we wanted users to be able to test the ot 4 infrastructure in their own designs, we didn t include an analog functional core. Although IEEE 49.4 lets designers implement conceptual switches differently, transmission gates are most appropriate for CMOS-based devices. Figure 2 shows an ABM cell s analog-switching architecture. We implemented the preliminary chip in 0.8-micron Austria Microsystems (AMS) CYE technology. The relatively high internal resistance exhibited by standard AMS library switch cells required that we modify the design to obtain transmission gates suitable for inclusion in the ABM/TBIC analog-switching architecture. Similarly, because standard cell comparators would occupy an unacceptably large silicon area, we designed a custom comparator, which satisfies our requirements both in terms of silicon area and electrical characteristics. Table compares the library and modified switched cell. Table 2 compares the standard library and custom comparators. Pin 5 5 Pin 4 4 Pin 3 3 Pin 2 2 Pin TI Common reference voltage V H ABM 5 ABM 4 ABM 3 ABM 2 ABM V L AB 2 V G ot 4 test chip ABM 6 ABM 7 ABM 8 ABM 9 TBIC Mode Update_R Clock_R Mode2 Shift_R Common test control signals TAP controller Complex programmable logic device AB Analog bus ABM Analog boundary module AT Analog test pin TAP Test access port TBIC Test bus interface circuit TI Test data input TO Test data output Pin 6 6 Pin 7 7 Pin 8 8 Pin 9 9 AT AT 2 TO Figure. Preliminary test chip block diagram. We use this chip to assess complex mixedsignal cell characteristics and identify design deficiencies and modifications. Table. Comparison of area and resistance between library and modified switch cell. Cell imensions (µm) Surface area (µm 2 ) R ON at V (Ω) TG2B (library) ,620 TG_inv (modified, integrated inverter) Table 2. Comparison between library and custom comparator implementations. Offset Voltage V out min V out max V th min V th max Surface Cell (µv) gain A V (db) (mv) (V) (V) (V) area (µm 2 ) Comp0B (library) = 23,000 Comparator (full custom) = 2,800 MarchApril

3 Board-Level Test Technologies Reference voltages modified the ABM cell in three key ways: Pin Mode2 Mode Update_R Shift_R From TI Clock_R G 0 SB SH V H V L V G SL SG Analog boundary module S B B 2 ata CTRL Bus Bus2 Synthesizing the control logic and registers was relatively straightforward. Figure 3 shows the test chip layout. Altogether, we laid nine ABM cells and one TBIC on an active area of,980,980 square microns, featuring 39 pads connected to five control signals (Mode, Mode2, Update_R, Shift_R, and Clock_R); two digital test signals (TI and TO); two digital power supply lines (V and GN); two analog power supply lines (V A and GN A ); two analog test signals (AT and AT 2 ); and 8 pairs (pin and core) of ABM functional signals. We directly synthesized the TAP controller, bypass and instruction registers, and instruction decoding logic from RTL VHL source code and programmed them into a Xilinx XC9508 complex PL for a total of 38 macro cells. The second version of the ot 4 test chip incorporates both analog and digital components and includes extensions that let us implement alternative test and measurement procedures. To realize this version, we Switching architecture Control-decoding logic Update register To TO We excluded the core disconnect switch from the ABM switching architecture and implemented it as a separate cell consisting of a lowresistance (R ON < 50 Ω) CMOS transmission gate, where R ON is the transmission gate resistance during the ON state. Users can take advantage of this low-resistance switch or implement the core disconnect facility in their own analog designs. We added two switches to provide ABM analog test bus multiplexing. We added switches to connect the ABM comparator s inverting input to either or one of the V H, V L, or V G common reference voltages. Applying the extended ABM functionality Figure 4a shows how digital boundary modules isolate the core from external circuitry during internal test (Intest). uring digital Intest, digital boundary modules isolate the core from the I/O pins while the tester applies test vectors and monitors responses. On the other hand, according to IEEE 49.4, the analog INTEST instruction keeps external circuitry connected to the analog core. This requires controlling the external onboard circuitry to provide appropriate operating conditions to the core or to ensure that the inputs are quiescent. To circumvent this practical limitation in the original ABM structure, we introduce two additional switches, SB_INT (internally switch to bus, ) and _INT, which bypass the core disconnect switch (S), as Figure 4c illustrates. This lets designers open S during the INTEST instruction, eliminating the need to control external circuitry and simplifying test development. The proposed ABM modification does not replace the original INTEST instruction but rather adds an instruction, letting the designer perform Intest with the core disconnected from the surrounding circuitry. For extended Intest procedures on a multiple input analog core, this approach is limited: The analog stimulus generator can drive only a single input through the analog Control register Figure 2. Schematic representation of an analog boundary module (ABM). We divided the ABM into four submodules to simplify future modifications of the design. 34 IEEE esign & Test of Computers

4 test bus. We therefore include switch SG_INT, which connects the remaining core inputs to the known reference voltage, V G, as Figure 4c shows. The original and modified ABM architectures suit different types of test strategies. The modified ABM structure allows system-wide functional reconfiguration, which might prove useful in analog functional tests. As Kac et al. have demonstrated, designers can reconfigure select analog functional blocks into a selftesting structure by establishing connections via the ot 4 analog test bus, and thus perform efficient go/nogo functional tests. 3 Consider, for example, a device with an active resistor-capacitor (RC) filter core, as depicted in Figure 5 (next page). The core input and output are connected to ABMs. By connecting the filter to an external circuit (an equalizer) via the ot 4 analog test bus, we can perform an oscillation-based test. We can then measure the resulting frequency onboard with a simple digital counter and compare it to a preloaded reference value. An experiment verified this idea s feasibility. Figure 6 shows the resulting oscillation, and Table 3 gives measurement results, where R b determines the equalizer voltage gain and f OSC denotes the resulting oscillation frequency. V L 3 Pin 3 Pin 2 Pin 0 Pin 0 V A V SS V SS V Pin 4 4 Pin 5 V H 5 V H V G Pin 6 Scan_in Scan_out Mode V Mode2 Clock_R Shift_R 6 Pin 7 7 Pin 8 8 AT AT 2 V A V SS V V SS Figure 3. Preliminary test chip layout. Nine ABMs and one TBIC cell are laid out starting from the bottom left. To simplify debugging, we did not include the TAP controller on the chip. To TO Mode V H V L V G Pin OFF G Pin 0 G Shift_R From TI Update_R Clock_R (a) (b) Pin External load SH SL SB SG Pin ON S V H V L V G Pin External load SH SL SG SB Pin OFF S S_INT SG _INT S2_INT (c) Figure 4. Isolating the core during Intest procedures: digital boundary module (a), ABM switching architecture (b), and modified ABM switching architecture (c). MarchApril

5 Board-Level Test Technologies ABM IC Analog core (RC filter) ABM 2 External circuitry TBIC AT System test bus Equalizer AT 2 Figure 5. Active resistor-capacitor (RC) filter functional test. We connect the filter to an equalizer using the ot 4 analog test bus, then perform the oscillation-based test. IC IC 2 Voltage comparator logic signal (Cmp) V short V variations TH CMOS switch SH R ON ABM Out In Cmp 2 C R PA R SHORT <<R ON +R PA V shorth V shortl ABM 2 ABM 2 R ON Out 2 In 2 Cmp 22 SL ABM 22 0 V in (a) V L (b) V L min max V H Figure 6. IEEE 49.4 interconnect test (Extest): A bridging fault produced an intermediate-level voltage on analog input pins (a). Variations in ABM comparator threshold levels can lead to a fault passing undetected (b). Table 3. Measurement results for direct and analog test bus connections. Connection type R b (kω) f OSC (Hz) irect Via analog test bus In the original IEEE 49.4 ABM structure, the control-decoding logic derives the control signals for each switch from the update register contents and the global mode signals, both of which the TAP instruction decoder supplies (Figure 2). The extended ABM switching architecture requires additional control signals, which can be provided in different ways. Because switches (SB,, and SG) and (SB_INT, _INT, and SG_INT) represent two complementary groups, they can use the same update register codes for the control, provided the instruction decoder supplies an additional global control signal (Mode3) during the extended INTEST instruction. Table 4 shows how we modified the equations for this instruction. 36 IEEE esign & Test of Computers

6 The hardware overhead is therefore relatively small, encompassing the additional ABM switches, the modified ABM control-decoding logic, and the additional global control line. Because switches SB_INT, _INT, and SG_INT introduce additional parasitic capacitances to the signal path, minimizing their impact on the analog design functionality requires careful modeling. Our second modification to the ABM cell lets us compare analog input signals to multiple voltage levels. We add switches CG, CL, CH, and CTH, where C is compare, to the ABM switching structure, as Figure 7a illustrates. These switches connect the comparator inverting input to either (mandatory) or one of the V H, V L, or V G common reference voltages (our extension). This feature augments the diagnostic capability of interconnect test (Extest). Assume the tester encounters a bridging fault during Extest, as Figure 6a illustrates. In the preliminary chip implementation (see Figure 2), we implemented SH and SL with identical CMOS transmission gates. These gates exhibit substantial ON-resistance and are connected in series with reference voltage sources. As IEEE 49.4 notes, the voltage at the combined (shorted) net will be at some value between V H and V L. esigners should choose a compare voltage,, that is clearly different from the possible input voltage levels. On the other hand, IEEE 49.4 limits the value of value to the range, (V H + V L )/2 ± (V H V L )/4. Suppose the resulting voltage of the bridging fault depicted in Figure 6a is near the threshold voltage of IC 2. As Table 4. Control equations for the extended INTEST instruction, where B, C, and refer to update register cells (shown in Figure 2), and M refers to mode. Switch Original equation Modified equation SG SG = CM M 2 SG = CM M 2 SB SB = B M SB = B M M 2 = B 2 M 2 = B 2 M M 2 SG_INT NA SG_INT = CM M2 M 3 SB_INT NA SB_INT = B M M2 M 3 _INT NA _INT = B 2 M M2 M 3 Figure 6b shows, variations in comparator threshold levels cause the ABM 2 comparator to identify the input voltage as high logic and the ABM 22 comparator as low logic. Hence, the fault can pass undetected. If we shift the comparator threshold voltage to level V H2 in ABM 2 and V L2 in ABM 22, we can clearly detect the bridging fault, as Figure 7b illustrates. ot 4 states that V H and V L should always be available on both input and output pins and can be pin specific that is, they do not have to be the same on all pins. Therefore, designers can choose appropriate V H2 and V L2 values for IC 2 input pins (In, In 2 ) such that the comparators maintain a sufficient noise margin for both fault-free input voltage levels (V H and V L ). Because Extest does not require high-precision voltage levels, simple MOS voltage dividers can generate V H2 and V L2 on chip. Alternatively, external sources can supply the required multiple volt- Voltage comparator logic signal (Cmp) V G V L V H ABM IC 2 V H2 ABM 2 Cmp 2 V short V in SG SL SB SH CG CL CH CTH V cmp Cmp S V short In Cmp 2 0 V L V H2 V H V In In 2 Cmp 22 Cmp 22 V short V cmp control V L2 ABM 22 0 V L V L2 V H V In2 (a) (b) Figure 7. Controlling during interconnect test (Extest): Added switches CG, CL, CH, and CTH connect the comparator inverting input to either or V H, V L, or V G (a); shifting the comparator threshold voltage to level V H2 in ABM 2 and V L2 in ABM 22 makes the bridging fault easily detectable (b). MarchApril

7 Board-Level Test Technologies Table 5. Control equations for the modified EXTEST instruction. Switch Original equation Modified equation SH SH = CM M 2 SH = CM M 2 SL SL = C M M 2 SL = C M M 2 SG SG = CM M 2 SG = CM M 2 CH NA CH = CM M 2 M 3 CL NA CL = C M M 2 M 3 CG NA CG = CM M 2 M 3 CTH NA CTH = ages through additional, common voltage reference pins. Like the modified INTEST instruction, the modified EXTEST instruction requires additional control signals, which can be similarly provided. Switches SH, SL, and SG on the input pins are always open during conventional Extest; consequently, a common signal can disable them and the modified EXTEST instruction can use their update register codes to control switches CH, CL, and CG. Again, we combine the global mode signals with the codes to produce the switch control signals, as Figure 7 shows. Table 5 shows how we changed the control equations to support the modified EXTEST instruction. Figure 8 depicts a trivial implementation of the modified ABM control-decoding logic. FUTURE WORK will focus on functional reconfiguration strategies exploiting the proposed core disconnect feature. In particular, we shall explore possible reconfigurations of different types of analog circuits into oscillation-based test structures. We also plan to work on applications of the modified ABMs that allow testers to compare analog input signals with multiple voltage levels. In addition to the enhanced interconnect test we describe, the comparator input can be connected to different sensors, thus allowing the system to monitor its environment via the ot 4 infrastructure. Acknowledgments We performed this work as part of the bilateral French-Slovenian Proteus project, which is supported by the French Ministry of Foreign Affairs and the Slovenian Ministry of Education, Science, and Sport. References. R.G. Bennetts, IEEE 49. Test Access Port and Boundary-Scan Std., FT Technology Backgrounders, Feb. 200, tutorial/bscan.pf. 2. IEEE Std , IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, K.P. Parker, J.E. Mcermit, and S. Oresjo, Structure and Metrology for an Analog Testability Bus, Proc. Int l Test Conf. (ITC 93), IEEE Press, 993, pp Switch control signals CTH SB SG_INT SG2_INT SH SL SG CH CL CG SG_INT S Control-decoding logic Mode Mode2 Mode3 Update_R C B B 2 Update register From control register Figure 8. Modified ABM control-decoding logic for extended Intest and Extest. 38 IEEE esign & Test of Computers

8 4. IEEE Std , IEEE Standard for a Mixed- Signal Test Bus, IEEE, A. Cron, IEEE 49.4 Almost a Standard, Proc. Int l Test Conf. (ITC 97), IEEE Press, 997, pp K.P. Parker, The Boundary-Scan Handbook: Analog and igital, Kluwer, JTAG Analog Extension Test Chip: Target Specification for the IEEE P49.4 Working Group, Preliminary Review 02, Keith Lofstrom Integrated Circuits, Beaverton, Ore., 998; klp.html. 8. K.P. Parker et al., esign, Fabrication, and Use of Mixed-Signal IC Testability Structures, Proc. Int l Test Conf. (ITC 97), IEEE Press, 997, pp S. Sunter et al., A General Purpose 49.4 IC with HF Analog Test Capabilities, Proc. Int l Test Conf. (ITC 0), IEEE Press, 200, pp National Semiconductor, Mixed-Signal Test, and the IEEE 49.4 Standard, appinfo/scan/.. K. Lofstrom, Early Capture for Boundary Scan Timing Measurements, Proc. Int l Test Conf. (ITC 96), IEEE Press, 996, pp S. Sunter and B. Nadeau-ostie, Complete, Contactless I/O Testing Reaching the Boundary in Minimizing igital IC Testing Cost, Proc. Int l Test Conf. (ITC 02), IEEE Press, 2002, pp U. Kač et al., Alternative Test Methods Using IEEE 49.4, Proc. esign, Automation, and Test in Europe (ATE 00), IEEE CS Press, 2000, pp Franc Novak heads the Computer Systems epartment at the Jozef Stefan Institute and is an associate professor on the Faculty of Electrical Engineering and Computer Science at the University of Maribor. His research interests include electronic testing and diagnosis, fault-tolerant computing, and FT of analog circuits. Novak has a Ph in electrical engineering from the University of Ljubljana. Florence Azaïs is a researcher for the National Council for Scientific Research (CNRS) in the Microelectronics epartment of LIRMM (the Laboratory of Computer Science, Robotics, and Microelectronics in Montpellier, France). Her research interests include fault modeling and mixed-signal circuit testing, especially FT and BIST techniques. Azaïs has a Ph in electrical engineering from the University of Montpellier. Pascal Nouet is a researcher at LIRMM and an associated professor at the University of Montpellier s Institute for Engineering Sciences. His research interests include analog circuit design and test, and design, test, modeling, and characterization of monolithic microelectromechanical systems. Nouet has a Ph in microelectronics from the University of Montpellier. Uroš Kač is a research assistant at the Jozef Stefan Institute in Ljubljana, Slovenia, where he is also pursuing a Ph. His research interests include high-level synthesis, mixed-signal test, and online/concurrent built-in self-test (BIST). Kač has an MS in electrical engineering from the University of Ljubljana. Michel Renovell heads the Microelectronics epartment at LIRMM. His research interests include fault modeling, analog testing, and FPGA testing. Renovell has a Ph in electrical testing from the University of Montpellier. irect questions and comments about this article to Uroš Kač, Jozef Stefan Institute, Jamova 39, 000 Ljubljana, Slovenia; uros.kac@ijs.si. MarchApril