An Optimal Test Pattern Selection Method to Improve the Defect Coverage

Transcription

1 A Optimal Test Patter Selectio Method to Improve the Defect Coverage Yuxi Tia, Michael R. Grimaila, Weipig Shi ad M. Ray Mercer Departmet of Electrical Egieerig Texas A&M Uiversity, College Statio, Texas 77843, USA Fax: {ytia, wshi, Departmet of Systems ad Egieerig Maagemet Air Force Istitute of Techology, Wright-Patterso AFB, Ohio 45433, USA Abstract It is well kow that -detectio test sets are effective to detect umodeled defects ad improve the defect coverage. However, i these sets, each of the -detectio test patters has the same importace o the overall test set performace. I other words, the test patter that detects a fault for the first time plays the same importat role as the test patter that detects that fault for the ()- th time. This is ot a accurate assumptio, especially as the deep submicro techologies are widely used today. I this paper, we propose a liear programmigbased optimal test patter selectio method which aims at reducig the overall defect part level (DPL). Usig resistive bridge faults as surrogates, our experimetal results o ISCAS85 circuits demostrate the proposed test patter selectio method achieves a higher defect coverage tha traditioal -detectio method. 1 Itroductio Semicoductor maufacturers strive to attai a high yield (ideally 100%) whe fabricatig itegrated circuits. Ufortuately, umerous factors ca lead to a variety of maufacturig defects which may reduce the overall yield. The purpose of testig is to idetify ad elimiate ay defective chips after the chips are maufactured. However, it is curretly impractical to test exhaustively for all possible defects. This is a result of the computatioal ifeasibility of accurately modelig defects, limitatios imposed by existig maufacturig test equipmet ad time/ecoomic costraits imposed by the test egieers. For these reasos, the stuck-at-fault (SAF ) model has bee accepted as the stadard model to geerate test patters. Most of the existig commercial ATPG tools use the SAF coverage as a metric of the quality of a test set ad termiate test geeratio whe a high SAF fault coverage is attaied. Although sigle stuck-at fault detectio is widely accepted i idustry, it ca ot detect may other types of defects [19]. Especially as the widespread usage of deep submicro techology, the probability of developmet of trasiet ad patter sesitive faults is risig tremedously. To address the deficiecy of stuck-at fault detectio, oe approach is to build more sophisticated fault models, such as the bridge fault model [15][12] ad the delay fault model [10]. However, sice most existig ATPG tools are desiged for sigle stuck-at faults, cosiderable effort must be made to exted these tools to the ew fault models. I this paper, we follow aother approach: -detectio, where each sigle stuck-at fault is detected multiple times i order to catch other types of defects [18] [8]. I the -detectio approach, the existig ATPG tools ca be used with miimum efforts to achieve the best results. The first work o -detectio was doe by Ma, Fraco ad McCluskey [14]. I a experimet, they showed that as the umber of uique detectios for each fault icreases, the defect coverage always improves compared with other test geeratio schemes. Whe is sufficietly large, the -detectio stuck-at test patter sets lead to the idetificatio of almost all defective chips. Subsequet works [16][20] have also provided the aalysis of the effectiveess of -detectio test patter sets. However, the set of test patters that detect each stuck-at fault times is ofte too large, resultig i both high tester memory usage ad log testig time. This is because the -detectio method treats all test patters that detect a stuck-at fault equally importat whe the fault is detected less tha times. Previous research has proved that ot all the patters i the test sets are equally efficiet i reducig the defect coverage [9]. Thus, -

2 detectio o each sigle stuck-at fault would somehow waste some test patters ad reduce the performace of the test set. Therefore, a post test geeratio compactio or optimizatio is ecessary. I this paper, we propose a liear programmigbased ew test patter geeratio strategy which selects the optimal subset of test patters from the -detectio test set based o a weighted defect part level estimatio model MPG-D model [4]. Istead of geeratig the test patters directly, our method aims at selectig a optimal patter set from a big -detectio set. We use weighted MPG-D model as our objective fuctio to select the patters, which accurately reflect the cotributios of each patter to detect umodeled defects. Sice the accurate defect coverage is almost impossible to get [1], we use the surrogate detectio approach to compare the fault coverage of the test patter set with the -detectio test patter set. (Here, surrogates mea the fault models that are ot targeted directly durig the test patter geeratio but are used to evaluate the quality of the test patter sets). Uder this approach, the test patters are geerated for a specific target fault model (sigle stuck-at fault) ad the simulated o the surrogate fault model (bridge fault). The rest of this paper is orgaized as follows: I sectio 2, we itroduce the weighted MPG-D defect part level estimatio model. Sectio 3 itroduces the applicatio of liear programmig to select optimal test patters from a -detectio test set. Sectio 4 summarizes the experimetal results ad compares the surrogate fault coverage of our method ad that of the - detectio method o ISCAS85 bechmark circuits. Fially, i sectio 5, we coclude our research results. 2 Defect Part Level Estimatio Model To geerate a test set, test geerators always use some objective fuctios to determie if the fial objective is achieved. For the sigle stuck-at fault orieted ATPG tools, the objective fuctio is the sigle stuck-at fault coverage, ad the objective is to maximize, to 100% if possible, the fault coverage. For the -detectio methods, the objective is to detect each stuck-at fault by differet patters at least times. As log as -detectio o a fault is achieved, this fault is dropped from the fault list ad o loger targeted uder additioal tests. This process ca be explaied by the followig model: Give a set of test patters T = {t 1, t 2,..., t } ad fault set F = {f 1, f 2,..., f m }, defie the objective fuctio as: M(F, T ) = m M(f i, T ) where 1 if f i is detected less tha times by T M(f i, T ) = 0 otherwise. The objective of the -detectio methods is to geerate a set T so that the objective fuctio M(F, T ) is miimized. However, this step objective fuctio of -detectio is ot optimal because as the umber of detectios icreases, the objective fuctio should gradually decrease sice as more defects are detected at each site, the probability of excitig oe of the remaiig defects becomes smaller. Cosider Figure 1, the etire test space available at a test site i the circuit is represeted as a box i the Ve diagram. Each oval represets the portio of that test space which will excite a particular defect at that test site (give that the site is observed). Thus, a defect is detected whe a test is chose so that it falls withi that defect s correspodig oval (Multiple defects may i some cases be detected by the same test patter). Oce a defect is detected, detectig it agai will ot further reduce the defect part level, therefore, defect s oval o loger appears amog those udetected defects. At ay particular poit i time, the probability of excitig a as yet udetected defect give that the site is observed is simply the ratio of the area of the test space covered by the ovals to the total area. Thus, the probability of excitig a as yet udetected defect teds to decrease as test patters are applied ad defects are detected. Based o this observatio, a defect part level estimatio model, MPG-D model, was proposed [3]. Ulike other defect part level estimatio models which deped upo fault coverage, it does ot go to zero whe fault coverage reaches 100%. I additio, it represets the fact that the probability of excitatio decreases as the umber of site observatios icreases ad that more tha oe defect may be preset at ay fault site. The origial MPG-D model defies the relatioship betwee the umber of times a site is observed ad its cotributio to the DPL. First of all, this model assumes the uiform distributio of all the defects across the fault sites. Thus, for each fault site j, a iitial cotributio to the overall DPL is defied as: DP L j (0) = 1 Y No. of Fault Sites (1) where Y is the maufacturig yield. After the applicatio of a test patter sequece T = {p 1, p 2,..., p k }, where k 1, some fault sites have bee observed, some have bee excited, ad some defects have bee detected. Thus, refer to Figure 1, the probability of excitig a udetected defect at a site give that site is observed would

3 ## ### ### ### ### ### ### ### ### ### ### ### ### ### ### # $$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $$$ $ % & %% && %% && %% && %% && '''''''' '''''''' '''''''' '''''' (((((((( (((((((( (((((((( (((((( ''''' ((((( ))))) ))))) )))))) )))))) )))))) ))))) ))))) ))) %% ***** ***** ****** ****** ****** ****** ***** *** && ))) ***%% && %% && %% && # $!!!!!!! """"""" %% &&!!!!!! """""" % & Iitial Test Space Reduced Test Space After Test Patter 1 Applied Reduced Test Space After 2 Test Patters Applied Test Patter 1 Test Patter 2 Figure 1. The probability of excitatio decreases as testig progresses be reduced as more test patters are applied. This probability has bee studied ad show to be a decayig expoetial fuctio of the umber of times that site has bee observed previously ad a time costat φ [3]: P excite = e obs j φ (2) where obs j meas the total umber of observatios of test site j. Sice the idividual probabilities are disjoit, the overall DPL is merely the sum of the cotributio from each idividual site. Therefore, DP L(T ) = No. of Fault Sites DP L j (k) (3) Ad for this test set T with k patters (k 1), each site s defect part level cotributio is give i the followig equatio [3]: DP L j (k) = DP L j (k 1)(1 A e obs j φ ) obs jk (4) where A ad φ are two costats related to the maufacturer s process ad circuits, ad DP L j (k 1) is the Number of Fault Sites Histogram of Couplig Capacitace for Circuit C432 Class III Class II Class I Couplig Capacitace (ff) Figure 2. Weight Fuctio Geeratio defect part level cotributio whe the first k 1 test patters are applied to the circuit uder test. The value obs j meas the total umber of observatios of test site j so far. The value of obs jk is 1 if fault j is observed by vector k, otherwise it is 0. Although the origial MPG-D model ca be used to predict the DPL, it suffers from the limitatio assumptio that all sites i the circuit are equally sesitive to defects. I reality, we fid that each site i the circuit has differet physical ad geometric characteristics that make it more or less susceptible to a uiform distributio of defects. Therefore, each site s cotributio to the overall DPL is ot uiform but istead is a strog fuctio of its physical layout. Larger sites with more die area are more likely to suffer from defects tha smaller sites. I order to create a more accurate model, we must accout for the physical characteristics as represeted i the layout of the circuit. I this paper, we will use a refied MPG-D model to estimate the DPL resultig from the applicatio of a give test set. We refer to this model as the weighted MPG-D sice we will assig differet weight for each site i the circuit based upo the physical ad/or electrochemical characteristics of each site. I geeral, the weights may be a fuctio of all the characteristic such as (but ot limited to) the physical area of the site, proximity to adjacet sites, proximity to active areas, io implatatio eergy, diffusio gradiet, etc. As recet studies have show [2][13], i the deep submicro techology era, the problems due to icreasig couplig capacitace have a sigificat adverse effect o the proper fuctio ad performace of VLSI system. Therefore, for simplicity, i this paper we will employ the couplig capacitace extracted from the layout as a idicator to geerate the weight fuctio ad refie the origial MPG-D model. First, the circuit layout was geerated with Cadece Silico Esemble i TSMC 250m 3V 3-metal techology. Commercial par-

4 asitic extractio tools are used to extract the couplig capacitace of each site. To simplify the problem without losig geerality, we classify the fault sites ito several classes based o their greatest couplig capacitace, for the classes with bigger couplig capacitace, we assig a bigger weight, for the classes with smaller couplig capacitace, we assig a smaller wight. To show these steps i detail, the histogram of couplig capacitace for circuit C432 fault sites is show i Figure 2. For this circuit, we set up two thresholds for to separate the fault sites ito three classes, if the couplig capacitace of a fault site is bigger tha the first threshold (1.5fF), we put them ito class I; if the couplig capacitace is betwee the secod threshold (1fF) ad the first threshold (1.5fF), we put them ito class II; For all other sites, we put them ito class III. Therefore the weight fuctio is defied i the followig step fuctio: w 1 if fault site j is i class I w j = w 2 if fault site j is i class II otherwise. w 3 where w 1 w 2 w 3. I our experimets, we choose the weights betwee 1.0 ad Now we have the weighted MPG-D model defied i equatio (5): DP L(T ) = No. of Fault Sites w j DP L j (k) (5) The solid lie i Figure 3 shows a example of DPL cotributio estimated by equatio (4) with the weight of 1.0. The curve shows that as the umber of observatios o test site j icreases, the cotributio to the overall defect part level decreases as a expoetial fuctio. Now we have derived the DPL estimatio fuctio show i equatio (5), our objective is to geerate a test patter set so that the DPL is miimized. Istead of geeratig the test patters directly, our method selects a optimal patter set from a big -detectio superset. The -detectio superset are geerated by ruig the stadard ATPG tools repeatedly util every fault is detected times. As we discussed before, although -detectio test set could effectively reduce the defect part level, the umber of geerated patters is much larger tha covetioal methods. Limitatios o tester memory size ad the high cost of testig time severely limits the umber of test patters that ca be applied to a device i a commercial settig. As a result, a post processig optimizatio process is required to select the best subset of patters from the -detectio superset to use as the actual test set. I the ext sectio, we are goig to itroduce a liear programmig based method to select the patters from this big -detectio test patter set. DPL Cotributio from a Fault Site (ppm) A B DPL Cotributio Liear Approximatio No. of Observatios o A Idividual Fault Site Figure 3. Liearizig the DPL Reductio Curve 3 Optimal Test Patter Selectio I this sectio, we develop a liear programmig method to solve the optimal test patter selectio problem discussed i sectio 2. Liear programmig is beig widely used today i a wide variety of optimizatio problems, icludig the VLSI desig ad testig problems [5][7]. The fial goal of our liear programmig model is to select a optimal or ear-optimal set of test patters from a superset with the objective that the objective fuctio (5) is miimized. Sice the DPL fuctio defied i (5) is ot a liear oe, it is ot easy to miimize this objective fuctio directly. Therefore, we first liearize the weighted MPG- D model i terms of equatios ad costraits. Cosider the DPL cotributio curve show i Figure 3 which shows the relatioship betwee the umber of detectios for each fault ad the expected value of the objective fuctio for a specific fault, if we wat to geerate the optimal test patter set which results i the miimum expected value, we ca liearize the weighted MPG-D curve with the three liear segmets show i Figure 3 to approximate the real objective fuctio, ad this approach will sigificatly improve the solvability of the origial problem without sacrificig much accuracy. From the previous discussio, we ca defie the problem as follows: Give a fault dictioary Π T F, where T = {t 1, t 2,..., t } is the big -detectio set geerated by ruig ATPG tools repeatedly ad F = {f 1, f 2,..., f m } is the fault set. If (t i, f j ) Π, patter t i detects fault f j. The problem is how to select a set T T so that T u, where u is the upper boud allowed for set T, ad at the same time, the defect part level is miimized. Therefore, the objective fuctio of C

5 the problem is defied as: Mi : DP L(T ) = m w j DP L j (v) (6) where m is the umber of stuck-at faults i the circuit, w j is the weight assiged to fault j, v is the umber of detectios o fault f j ad DP L j (v) is the idividual defect part level cotributio from fault site j. Sice DP L(T ) is ot a liear fuctio, it is ot so easy to fid the optimal solutio of objective fuctio (6) directly. Therefore, we ca approximate DP L j (v) to a liear fuctio DP L j (v) so that we ca use the stadard liear programmig method to solve it. The the objective fuctio becomes: Mi : DP L(T ) = m w j DP L j (v) (7) where DP L j (v) icludes the three liearized segmets show i Figure 3. These three lies correspod to three liear fuctios (here, they are amed as M 1, M 2 ad M 3, respectively) as follows: M 1 = DP L j (v) = M 2 = DP Lj(b) DP Lj(0) b v + DP L j (0) (If 0 v < b) DP Lj(c) DP Lj(b) c b (v b) +DP L j (b) (If b v < c) M 3 = 0 (If v c) where v is the umber of detectios o a fault, b ad c are the x-coordiate values of the poits B ad C i Figure 3. We ca also fid that i each segmet, (e.g., 0 v < b, b v < c ad v c), DP L j (v) is always the maximum value of the three fuctios defied i (8). Therefore, for all v 0, the three equatios i (8) are equivalet to the followig objective fuctio: DP L j (v) = Maximum{M 1, M 2, M 3 } (9) I the fault dictioary, for ay t i T, we defie a idicator variable x i such that if t i is i T, x i = 1; otherwise, x i = 0. Therefore, { 1 If ti T x i = (10) 0 If t i / T Sice the total umber of patters i T is limited to u, we have x i u (11) (8) By usig the idicator variable, we ca easily fid that v, which is the umber of detectios o a fault ca be expressed as: v = x i (12) (t i,f j) Π Here, i equatios from (6) to (12), 1 i ad 1 j m. Combiig equatios (7), (8), (9), (10), (11) ad (12) together, we ca trasform the origial optimizatio problem ito a iteger liear programmig problem sice x i must be a iteger. This problem ca be solved by iteger liear programmig algorithm. However, iteger liear programmig problem is kow a NP-complete problem without ay efficiet solutios. There are several ways to trasfer them ito a o-iteger problem, such as iterior poit method, differetiable method ad Taylor approximatio method [17][21]. I this paper, we use the relaxatio ad roudig method to obtai a o-iteger liear programmig model. First of all, the iteger idicators x 1, x 2,..., x i the origial problem are relaxed ad redefied. After the problem is solved, we will roud these variables back to itegers. So, we first covert the costrait (10) ad chage it to a problem that ca be solved more easily. We redefie x i as the probability of test patter t i to be selected from superset T. Thus, for every 1 i, we form the followig costrait: 0 x i 1,where 1 i (13) With this trasform, we ca fialize our optimal patter selectio problem ito the followig liear programmig model: Mi: DP L(T ) = Subject to: m w j DP L j (v) DP L j (v) DP L j(b) DP L j (0) b +DP L j (0) DP L j (v) DP L j(c) DP L j (b) c b DP L j (v) 0 x i u +DP L j (b) [ (t i,f j) Π (t i,f j) Π x i x i b] 0 x i 1 (14)

6 where 1 i, 1 j m. Compared with the origial iteger liear programmig oe, this liear programmig problem is much easier to solve. After this problem is solved, we eed to roud the solutio of x i back to 0 or 1 sice we assume it is the probability of selectig test patter t i from the superset T. Sice the defiitio of x i is chaged, we eed to verify that the fial result of the x i satisfies the origial coditios (10) ad (11). Suppose the solutios of the liear programmig model above are sets {ˆx i 1 i } ad { DP L j (v) 1 j m}. The based o the defiitio of x i, we ca roud x i back to 0 or 1 by followig the distributios: Probability[x i = 1] = ˆx i Probability[x i = 0] = 1 ˆx i (15) This distributio ca be accomplished i the followig way: 1. Geerate a radom umber r; 2. Compare r ad ˆx i ; 3. If r ˆx i, the x i is set to 1, otherwise, x i is set to 0. By roudig the result set ˆx i i this way, the origial costrait equatio (10) is satisfied. Now, we eed to cosider the origial costrait (11). It is possible that this costrait is violated; However, based o the probability theory [6], if we cosider the expected value of the results, we ca get the followig equatio: E[ x i ] = = = E[x i ] P [x i = 1] ˆx i u (16) I the derivatio here, the first equality is because the operator is liear, eve for radom variables that are depedet, ad the third oe is from equatio (15). Therefore, from equatio (16), we ca see that costrait (11) is satisfied o the average. That meas the expected value of the result is limited to the upper boud of the set T, which satisfies the costrait (11) of the origial problem. From the discussio i this sectio, we have set up a liear programmig model which attempts to obtai the miimum objective fuctio defied i sectio 2 for a test patter set selected from a superset. The whole optimizatio method ca be summarized as the follows: First, a -detectio test patter set as the test patter superset T ad the correspodig fault dictioary Π = T F are geerated, the the liear programmig model which is discussed i this sectio is formed ad solved. After the liear programmig problem is solved, the result is rouded to select the set T from the origial superset T. Fially, the resistive bridge fault is used as the surrogates ad the set selected is iput to the surrogate fault simulator PROBE [11] to get the resistive bridge fault coverage as the idicator of the test quality. 4 Experimetal Results The liear programmig problem preseted i this paper were solved usig a AMD Athlo XP 2800 PC ruig the Redhat Liux operatig system; The bridge fault simulator PROBE are workig o a SUN Ultra-4 workstatio ruig Solaris 5.7 operatig system. Stadard -detectio test patters were geerated by ruig Metor FastSca T M, a commercial ATPG tool, repeatedly. The liear programmig problem is solved by So- Plex 1.2.1, a liear programmig solver based o sequetial object-orieted simplex algorithm writte i the C laguage [22]. 4.1 Experimet Desig We recogize that it is virtually impossible to get the actual defect coverage of a test set without itetioally iducig defects i each device ad coductig a detailed decostructio of all devices. However, to show the effectiveess of liear programmig based patter selectio methodology, we desiged a experimet that would compare the surrogate fault coverage betwee - detectio method ad patter selectio method we proposed. I the experimet, there are two idepedet variables (circuit ad umber of patters geerated) ad the resultig surrogate fault coverage is compared. Our experimets use the te o-trivial ISCAS85 bechmark circuits. For each circuit, we geerate a collapsed stuckat fault list ad ru stadard ATPG tool repeatedly to get a -detectio superset (here i the superset, is set to be 15). Meawhile, 2-detectio set to 7-detectio test sets are also geerated by the same method. The, we use the patter selectio methodology discussed before to select the test patters from this 15-detectio superset ad geerate the set of test patters, whose sizes are limited to the 2-detectio to 7-detectio test sets, respectively. Whe all the test sets are ready, we use PROBE simulator to do the resistive bridge fault simulatio ad get the fault coverage as the fial results. We are also iterested i varyig the umber of test patters to reveal the trade-offs betwee test set size ad the resultig surrogate fault coverage. Here, we geerate a test patter set which has 100% sigle stuck-at fault coverage ad use the umber of test patters geerated as the base umber k. Specifically, the test set size limits are varied from oe times (k) to ie times (9k)

7 Detectio Detectio Figure 4. Bridge fault coverage vs. test set size for circuit c432 Figure 6. Bridge fault coverage vs. test set size for circuit c Detectio Detectio Figure 5. Bridge fault coverage vs. test set size for circuit c2670 Figure 7. Bridge fault coverage vs. test set size for circuit c5315 the umber of test patters that would be applied usig stadard best practice ATPG tool. Subsequetly, we use the ATPG tool to geerate a 15-detectio test patter superset. From this superset, subsets of various sizes were selected for each circuit. The the bridge fault simulatio is performed to get the fial bridge fault coverage. For each of the circuits, test geeratio methodologies, ad umber of patters geerated, we used PROBE resistive bridge fault simulator to get the bridge fault coverage as the idicator of the defect coverage Detectio Experimet Results Figures 4 to 8 shows the resistive fault coverage of the differet test patter size o differet circuits ad methods. is the umber we used i -detectio method, i these figures, chages from 2 to 7, which meas each Figure 8. Bridge fault coverage vs. test set size for circuit c7552

8 Table 1. CPU time to geerate the 15-detectio superset ad to select optimal test patters Circuit CP U 15 det CP U opt T overhead c s 1.9s 1.7% c s 3.2s 2.6% c s 9.5s 4.2% c s 18.6s 4.1% c s 132.7s 12.3% c s 198.5s 14.1% c s 320.4s 16.2% c s 579.3s 28.8% c s 386.9s 25.9% c s s 31.7% fault is detected 2 to 7 times. The umbers o the top of the colums idicate the resistive fault coverage for two differet methods. Based o the superset test patters umber of patters geerated by -detectio method, a optimal test patter set is selected such that it has the same umber of patters as -detectio. The other circuits have the similar results as these figures show. The results show here verify that optimal patter selectio method always get a higher bridge fault coverage tha the -detectio methodology as the size of the test set is same. These results also cofirm the correctess of weighted MPG-D model. Whe the umber of patters is smaller, the surrogate fault coverage differece betwee the two methods is bigger, while with the umber of patters icrease, the differece is smaller. This is because with the icrease of the umber of patters i the test set, the improvemet o the resistive fault coverage is becomig harder ad harder to get, also the overlap betwee the two test sets is bigger sice our superset is a 15-detectio set geerated by the same -detectio methodology, thus, the differece is smaller for bigger i these figures. Table 1 shows the ruig time (i secods) of the proposed algorithm. Colum CP U 15 det idicates the CPU time used to geerate the 15-detectio superset, CP U opt shows the average CPU time used to select the optimal test patter sets ad colum T overhead shows the CPU time overhead. We ca observe from the table that depedig o the circuit size, the CPU time overhead is varyig from 2% to 31.7%. Test egieers are ofte faced with the critical questio: How may test patters should be applied to the device uder test?. Their decisio has a eormous impact o the quality ad profitability of the product. Idustry testig regimes typically cosist of a combiatio of DC parametric, IDDQ, fuctioal, ad sca stuck-at fault based tests. Applyig too may test patters will Optimal Selectio Method Fault Coverage -Detectio Fault Coverage No. of Patters Applied Figure 9. Resistive bridge fault coverage vs. test set size for circuit c880 slow dow the test time ad icrease the tester memory. But if the test patter set is too small, it is hard to detect the umodeled defects. I order to make a ratioal decisio, oe must take ito accout the cost of testig time ad the desired defect coverage, as well as the size of available tester memory. I Figure 9, we use circuit c880 as a example to show a graphical represetatio of the trade-offs i test quality i terms of surrogate fault coverage ad the test set size. For circuit c880, 1-detectio test set icludes 40 patters, we vary the umber of patters applied from k=40 to 9k=360. Here, both optimal patter selectio method ad -detectio method are used ad the results are compared, it is obvious that optimal patter selectio method always results i a higher fault coverage tha -detectio. Graphs such as this provide a visual guide to aid the test egieer i makig trade-off decisios. Similar experimets are also carried o the other ISCAS85 circuits. From this figure, we ca get the umber of patters geerated by two differet methods whe the same bridge fault coverage is achieved. 5 Coclusios I this paper, we preseted a optimal test patter selectio methodology based o the weighted MPG-D model. The couplig capacitace value extracted from the bechmark circuit layout is used as the idicator to select the weight for each fault site to estimate the DPL. The objective of the methodology is to select a subset of test patters from a superset that results i the optimal defect coverage for a give, fixed test size. Compariso of the method to -detectio showig the effectiveess of optimal patter selectio at icreasig defect coverage. The primary result of this research is the icrease of the resistive bridge fault coverage. We achieved this result by the formulatio of a liear programmig model

9 which was the solved based o appropriate costraits for the give circuit. The experimetal results proved that this method is effective i detectig the umodeled defects ad thus improve the defect coverage. We believe that the icrease i the surrogate fault coverage will allow the methodology to be icorporated ito commercial practice. Fially, a graphical represetatio of the trade-off betwee the test quality ad test size is preseted to aid the test egieer i makig decisios regardig trade-offs betwee test set quality ad test set size. 6 Ackowledgmet The authors thak Dr. D. M. H. Walker for providig bridge fault simulator PROBE. Refereces [1] M. L. Bushell ad V. D. Agrawal Essetials of Electroic Testig for Digital, Memory ad Mixed-Sigal VLSI Circuits, Klumer Academic Publishers, [2] Kwag-Tig Cheg, S. Dey, M. Rodgers, K. Roy, Test challeges for deep sub-micro techologies, Proc. Desig Automatio Coferece, pp , [3] J. Dworak, M. R. Grimaila, S. Lee, L. C. Wag ad M. R. Mercer, Ehaced DO-RE-ME Based Defect Level Predictio Usig Defect Site Aggregatio - MPG-D, Proc. Iteratioal Test Coferece, pp , [4] J.Dworak, J.D.Wicker, S.Lee, M.R.Grimaila, K.M.Bulter, B.Stewart, L.C.Wag ad M.R.Mercer. Defect-Orieted Testig ad Defective Part Level Predictio. IEEE Desig ad Test of Computers, 31-41, Ja.-Feb [5] F. Fallah, S. Devadas ad K. Keutzer, Fuctioal vector geeratio for HDL models usig liear programmig ad boolea satisfiability, IEEE Tras. o CAD of Itegrated Circuits ad Systems, 20(8), pp , Aug [6] W. Feller, A Itroductio to Probability Theory ad Its Applicatios, 3rd Editio, Joh Wiley ad Sos, New York, [7] P. F. Flores, H. C. Neto ad J. P. Marques-Silva, A exact solutio to the miimum size test patter problem, ACM Tras. o Desig Automatio of Electroic Systems, 16(4), pp , Oct [8] M. R. Grimaila, S. Lee, J. Dworak, K. M. Bulter, B. Stewart, H. Balachadra, B. Houchis, V. Mathur, J. Park, L. C. Wag ad M. R. Mercer, RE-DO - radom excitatio ad determiistic observatio - first commercial experimet, Proc. VLSI Test Symposium, pp , [9] R. Kapur, J. Park ad M. R. Mercer, All tests for A fault are ot equally valuable for defect detectio, Proc. Iteratioal Test Coferece, pp , [10] A. Krstic ad K.-T. Cheg, Delay Fault Testig for VLSI Circuits, Kluwer Academic Publishers, [11] C. Y. Lee ad D. M. H. Walker, PROBE: A PPSFP simulator for resistive bridgig faults Proc. VLSI Test Symposium, pp , [12] Z. Li, X. Lu, W. Qiu, W. Shi ad H. Walker, A circuit level fault model for resistive opes ad bridges, ACM Tras. o Desig Automatio of Electroic Systems, Vol. 8, No. 4, pp , [13] Jig-Jia Liou, A. Krstic, Yi-Mig Jiag, Kwag-Tig Cheg Modelig, testig, ad aalysis for delay defects ad oise effects i deep submicro devices IEEE Tras. o CAD of Itegrated Circuits ad Systems, Vol. 22, No. 6, pp , [14] S. C. Ma, P. Fraco, ad E. J. McCluskey, A experimetal chip to evaluate test techiques experimet results, Proc. Iteratioal Test Coferece, pp , [15] S. D. Millma ad J. P. Garvery, Sr., A accurate bridgig fault test patter geerator, Proc. Iteratioal Test Coferece, pp , [16] I. Polia, I. Pomeraz, ad B. Becker, Exact computatio of maximally domiatig faults ad its applicatio to -detectio tests, Proc. Asia Test Symposium, pp.9-14, [17] P. Raghava, Probabilistic costructio of determiistic algorithms: approximatig packig iteger programs, J. of Computer ad System Sciece, Vol. 37, pp , [18] S. M. Reddy, I. Pomeraz ad S. Kajihara, O the effects of test compactio o defect coverage, Proc. VLSI Test Symposium, pp , [19] T. M. Storey, W.Maly, J.Adrews, ad M. Miske, Stuck fault ad curret testig compariso usig CMOS chip test, Proc. Iteratioal Test Coferece, pp , [20] C. Tseg, S. Mitra, S. Davidso ad E. J. McCluskey, A evaluatio of pseudo radom testig for detectig real defects, Proc. VLSI Test Symposium, pp , [21] R. J. Vaderbei, Liear Programmig: Foudatios ad Extesios, Kluwer Academic Publishers, Ju [22] R. Wuderlig, Paralleler ud Objektorietierter Simplex-Algorithmus, ZIB techical report TR 96-09, Berli, Germay, 1996.