Functional Integration of Parallel Counters Based on Quantum-Effect Devices

Transcription

1 Proceedings of the th IMACS World Congress (ol. ), Berlin, August 997, Special Session on Computer Arithmetic, pp Functional Integration of Parallel Counters Based on Quantum-Effect Devices Christian Pacha, Karl F. Goser Universität Dortmund, Lehrstuhl Bauelemente der Elektrotechnik Keywords: quantum-effect devices, hybrid integration, linear threshold logic, parallel counters ABSTRACT This paper describes the design of depth- parallel counters with a novel circuit architecture basing on quantum-effect devices. The elementary components of the counters are linear threshold gates with fixed integer weights. To obtain a compact implementation each threshold gate consists of two serially connected resonant tunneling diodes which are integrated in a hybrid way together with multiple heterostructure field effect transistors. A potential application is the computation of arithmetic functions with a reduced logic depth in high performance digital signal processing systems. I. INTRODUCTION Parallel counter networks are a well-known approach to implement arithmetic functions with a reduced logic depth for high performance computing. In the past, various parallel addition and multiplication schemes based on linear threshold logic have been developed [,,8]. In spite of the increased parallelism at the bit level, threshold logic is of less practical significance in LSI-design because the present technologies are optimized for Boolean logic gates. With the appearance of nanoelectronics as a potential future technology the prospect is that novel quantum-effect devices could enable an area efficient implementation of multiple terminal threshold gates []. One promising approach is the novel design principle of functional integration. Here the key idea is to decrease the circuit complexity (number of active components) and the wiring by directly exploiting the internal physical phenomena of quantum-effect devices. In detail, Section II describes the functional integration of linear threshold gates with resonant tunneling diodes (RTD) and heterostructure field effect transistors (HFET). Section III analyzes the operating principle of the proposed circuit. In Section I we discuss the design of generalized parallel counters with depth- linear threshold networks (LTN). II. IMPLEMENTATION OF LINEAR THRESHOLD GATES A linear threshold gate (LTG) is a multiple terminal device that calculates the weighted sum χ of the digital inputs x i, i=..n, and converts this sum afterwards into a digital output y by comparing with a given threshold value Θ. Using different sets of weights {w i } and adapting the threshold value LTGs are capable to compute any linear separable Boolean function of the n inputs [7]. Thus, LTGs combine an internal analog computation of the weighted sum with digital input and output states. The output y of a LTG with fixed integer weights is given by n χ = wi x i= i, { } χ = = if Θ, if χ < Θ y( χ) sgn ( χ Θ ) x i,, w {, ±, L, ± w }, Θ {, ±, L, ± Θ max }. i max ()

2 Proceedings of the th IMACS World Congress (ol. ), Berlin, August 997, Special Session on Computer Arithmetic, pp a) dd b) I RTD I HFET GS, GS, Positive Weights + G out I Θ GS, GS, Negative Weights and Threshold C L = G Fig. Threshold Gate consisting of two RTDs and multiple HFETs (a) and modulation of the RTD-current by the drain source current of the HFETs (b). Recently, a hybrid integrated gate consisting of two RTDs and multiple parallel HFETs has been presented [] (Fig.). It performs the three basic functions of a LTG: An oscillating bias voltage on top of the RTD-pair causes a monostable-bistable transition and enables a clocking of the LTG, being important in multilayer networks. The weighting of the digital inputs is done by using HFETs with different widths. After a comparison of the HFET-current sums in the upper and lower branch the RTD-pair generates a digital output. The RTDs and related devices are the most approved quantum-effect devices. Their typical feature is a peak in the current-voltage characteristics that results from quantum mechanical tunneling of electrons through the energy levels of a quantum well in semiconductor heterostructures. The peak in the current- voltage characteristics occurs if the energy of the electrons before the double barrier coincides with the quantisized energy level inside the quantum well. The hybrid integration of RTDs and HFETs offers the possibility to combine the field effect and resonant tunneling, two classical phenomena of semiconductor physics and quantum mechanics, in one circuit. The field effect guarantees an isolation of the input and output and the negative differential resistance of the two serially connected RTDs causes the increased functionality of the circuit. The drain to source current of the HFETs modulates the peak current of the corresponding RTD (Fig.b). Since this drain to source current depends linearly on the transistor width, a weighting of the input signals is obtained by varying the transistor geometry. The HFETs connected in parallel to the top RTD perform a positive weighting of the inputs whereas HFETs in parallel to the bottom RTD are negative weighted inputs. The threshold value of the gate is an additional negative weight controlled by the gate voltage Θ. Together with an oscillating bias voltage the peak-like RTD current generates a time dependent monostable-bistable transition (bifurcation). The increasing bias voltage changes the number, the location and the stability of the equilibrium points. Thus, the output of the circuit is either monostable or bistable. During the transition from monostability to bistability the output becomes unstable and is very sensitive to a small difference in the modulation currents of the positive and negative weighted inputs. To achieve a bistability the bias voltage has to be larger than twice the peak voltage of a single RTD. In contrast, monostability occurs at bias voltages below twice the peak voltage. According to this switching principle, the circuit is known as MOnostable- BIstable transition Logic Element (MOBILE) []. At present, three terminal LTGs based on In - xga x As/InAs double barrier RTDs with a peak to valley ratio of PR=. at room temperature have been fabricated and tested successfully.

3 Proceedings of the th IMACS World Congress (ol. ), Berlin, August 997, Special Session on Computer Arithmetic, pp Current [ma] Current [ma] Current [ma] Monostable... Fig. Bistable Tristable dd=.6 dd=.... dd=.6 Bifurcation Bifurcation Monostable dd=.8... dd=.... dd= Output out [] Output out [] Equilibrium points and bifurcations of a RTD-pair with a peak voltage of p =. Output out [] Fig. p p p p High p Low p Bias oltage dd [] p Bias voltage dependency of the stable (solid lines) and unstable (dashed lines) equilibrium related to the peak voltage p. III. OPERATING PRINCIPLE AND TRANSIENT ANALYSIS Since RTDs are highly nonlinear devices we analyze the transient behavior of the output voltage out with dynamical systems theory. Taking into consideration a load capacitance C L, one obtains following first order differential equation: C d L dt out ( ) ( ) = I ( t) I + I. () RTD dd out RTD out The load capacitance C L includes the input capacitance of following gates, the wire capacitance and the diode capacitance produced by the charge accumulation at the barriers. In a LTG with N HFETs for positive weighted inputs and M HFETs for in negative weighted inputs, the total modulation current is the current sum N M = i Θ Θ i= l= ( GS, i dd out ) l ( GS, l out ) ( out ) I w I, w I, w I,. () Here I is the drain to source current of a HFET with minimum width. The weight factors w i, w l and w Θ denote the width ratios between the HFETs with weighted inputs and the HFET with minimum width. As mentioned above, the threshold value is a negative weight with a fixed gate voltage. We assume that the total modulation current I in () is small compared to the peak current of the RTDs. Then the interconnection among several LTGs can be regarded as a weakly connected nonlinear network [6]. In a first approximation this allows to neglect the modulation current I. The equilibrium points of the circuit are the zeros of () and equivalent to the intersection points of the upper and the lower RTD-current (Fig.). In the following, these equilibrium points are the logic states of the LTG. Fig. illustrates the nonlinear behavior for two RTDs with a peak voltage of p =., a peak current of I p = ma and a peak to valley ratio of PR=.. The two logic states of the circuit appear at a bias voltage below the monostable-bistable transition at dd =.8 where the central equilibrium point becomes unstable. At a larger bias voltage there is a small region with three stable equilibrium points and two unstable equilibrium points. If the bias voltage exceeds five

4 Proceedings of the th IMACS World Congress (ol. ), Berlin, August 997, Special Session on Computer Arithmetic, pp times the peak voltage the circuit will become monostable again. From the viewpoint of dynamical systems theory the bias voltage dd is a bifurcation parameter or critical parameter. A common feature of many nonlinear systems is a sensitive reaction on small quantitative variations of certain parameters near the bifurcation points. The small variations will influence the stability and number of the equilibrium points []. In the proposed circuit we apply this sensitivity to implement the comparison function of the weighted sum and the threshold value in a compact way. To investigate the influence of different bias voltages more exactly, the bifurcation plot in Fig. shows the location of all equilibrium points as well as the change of their stability at the six bifurcation points. For a given set of RTD-parameters this allows to maximize the noise margin, that is the difference between the high and low state, by adapting the bias voltage. In larger circuits with a multilayer architecture the noise margin and the location of the logic states are important to switch the gates of the HFETs in the subsequent layer. If we choose the RTD-parameters mentioned above an appropriate bias voltage has to be about three times the peak voltage to obtain a noise margin of about. To explain whether the final logic state of the gate is high or low, one has to consider the modulation current again because the sign of I determines the final output The logic state high (low) corresponds to a positive (negative) sign of the modulation current. Thus, the circuit converts the small difference between the current modulation in the upper (positive weighted inputs) and in the lower branch (negative weighted inputs) into a digital output voltage. I. DESIGN AND APPLICATION OF PARALLEL COUNTERS The implementation of arithmetic functions with parallel counters is one promising application of RTD-based LTNs with fixed weights. Counters with different input and output configurations are key components in parallel multiplication schemes and in δ-bit pipelined serial addition [,9]. In both cases the objective is to avoid time consuming carry propagation during multi-operand addition or even to speed up the carry propagation by adding two digital numbers in blocks. When developing a circuit architecture for threshold logic, important features are the magnitude of the weights and the required fan-in of a single LTG. The total number of gates, especially the number of gates in the first layer of the LTN, are related to the output of the previous stage. While the depth of the network primarily affects the time delay, a reliable switching of a gate depends on the magnitude of the weights and the fan-in. Consequently, one has to make a compromise between purely theoretical aspects of LTNs, for example networks with a large number of terminals per gate, and the boundary conditions of small weights. Since the area of a device will decrease in nanoelectronics, the demand for minimizing the number of LTGs in a counter is not as critical as a limitation of the fan-in and the maximum threshold value. Therefore, we focus on designing a depth- generalized counter with three-valued weights w i {,±} between the two layers. Other counter implementations, such as the Kautz-network [] or Telescopic Sums [] are not regarded here. Both types of LTNs are including weight connections between the layers with an absolute value larger than one and are more difficult to implement within the proposed circuit. The most simple type of a counter is a counter, equivalent to a full adder. Concerning the notation, a k r-,..,k m generalized counter receives r columns of k l, l=..r-, digital inputs and computes a digital output of word length m (Fig.) [8]. Each input k l is weighted by l. Then the maximum fanin or the capacity χ max of a counter is given by χ max r = l= l k l. () Fig. shows that the output bit s j, j=..m-, are periodic Boolean functions of the weighted input sum χ. This simplifies the design of the depth- LTN because the network has only to detect those periodic sequences of high and low intervals. For the output s j the intervals are of length j [9]. The connection array between the first and the second layer of the LTN reflects the periodicity of the

5 Proceedings of the th IMACS World Congress (ol. ), Berlin, August 997, Special Session on Computer Arithmetic, pp s s s a) Counter b) 7 Counter c), Counter d),, Counter s χ Fig. Different types of parallel counters. Fig. Periodicity of the sum bits χ χ 6 8 S S S S dd Weights W=+ W= - Threshold Gate Θ st layer t nd layer t S [] S [] S [].... t [ ns ] Fig.6, counter and clocking scheme. Fig.7 Simulation results of a, counter S [] weighted sum χ (Fig.6). The boundaries of the high intervals are defined by a corresponding LTG of the first layer. In the case of a, counter the first layer comprises eight LTGs. Both, the maximum threshold value and the capacity are θ max =χ max =. The second layer detects whether the χ lies within one of the high intervals or not. This is achieved by means of the connection array performing a kind of OR function for each high interval. The clocking scheme for the two layers is overlapping and transfers the valid output of the first layer to the second one before dd decreases to ground. The SPICE simulation of a, counter, based on a semi-empirical device modeling of the RTDs, reveals the expected results. In Fig.7 the weighted sum χ increases from to by applying different input patterns to the counter. During the switching to the low state a short voltage peak appears because the output voltage at the transition point (. ) is larger than this final low state (. ). The occurrences of the voltage peaks agree with the experimental investigations in []. The amplitude of the bias voltage is. and the duration of a single clocking period takes. ns corresponding to a clocking frequency of GHz. A comprehensive evaluation of the proposed RTD-based counters, especially a comparison with a Boolean implementation, at the moment is difficult because of the current state of research on the field of nanoelectronic circuits. As a kind of first estimation Table I classifies different counter configurations concerning the number of LTGs, the capacity χ max, the maximum threshold value θ max in the first layer and the number of avoided carry propagations. The number of HFETs is the overall sum of the inputs in the first and second layer. Inputs with weight w i are equal to w i HFETs in parallel. To evaluate the increase of performance, Table I contains the difference in delay between a counter implementation with conventional full adders (delay n) and the depth- LTN-counters. We assume first that the full adders only include two terminal gates and second that multi-operand addi-

6 Proceedings of the th IMACS World Congress (ol. ), Berlin, August 997, Special Session on Computer Arithmetic, pp Table I Comparison of different parallel counter implementations. Type # LTGs Capacity χ max Θ max # HFETs (st. Layer) # HFETs # Full Adders Delay Delay Difference n n n n-, 6n 6n-,, 6 n n-,,, 77 n n- tion is done successively by parallel adding of two or three digital numbers. The carry bits in this Boolean implementation are pipelined to the following stage (ripple carry adder). The delay n of a single full adder varies for different technologies. Our estimation bases on a high speed direct coupled HFET/MESFET logic (DCFL) technology (only NOR and NOT gates) causing a delay of n=6 per full adder. The shaded columns of Table I display the number of required full adders and the resulting delay for a conventional counter implementation. Even the simple counter is an improvement compared to a DCFL full adder with a delay of n=6. Due to this estimations and simulation results the upper boundaries for an implementation within the proposed circuit are a counter capacity of χ max = for the LTGs in the first layer and a threshold value of Θ max =. Regarding an application of 7 and, counters to multi-operand reduction schemes in parallel multipliers one should prefer 7 counters because of the smaller maximum threshold and fan-in. Summarizing our approach towards threshold logic based counters the functional integration of quantum-effect devices offers a novel prospect to implement complex arithmetic operations with a reduced number of devices and reduced logic depth. To obtain more precise results concerning the maximum clocking frequency, the power dissipation and the limitations of the fan-in and fan-out, an experimental realization is intended. From the algorithmic point of view it is reasonable to consider the boundary conditions of a potential technology when searching for novel computational schemes. REFERENCES [] K. Chen, et al., InP-Based High Performance Monostable-Bistable Transition Logic Elements (MOBILE s) using Integrated Multiple-Input Resonant-Tunneling Devices, IEEE Electron Device Letters, ol. 7, No., March 996, pp [] S. Cotofana, S. assiliadis, Serial Binary Addition with Polynomial Bounded Weights, Proc. of the Int. Conf. on Artificial Neural Networks, Bochum, July 996, pp [] L. Dadda, Some Schemes for Parallel Multipliers, Alta Frequenza,, (96), pp [] K. Goser, C. Pacha, M.L. Rossmann, A. Kanstein, Circuit and System Aspects of Nanoelectronics, to be published in: Proc. IEEE, Special Issue on Nanoelectronics, April 997. [] H. Haken, Advanced Synergetics, Springer Series in Synergetics, ol., Springer, 98, pp [6] C. Pacha, K. Goser, Application of Terminal Dynamics in Cellular Neural Networks, Proc. of the 6th MIRCONEURO Conf., Lausanne, Feb. 996, IEEE Comp. Soc. Press, pp. -. [7] K. Siu, J. Bruck, Neural Computation of Arithmetic Functions, Proc. IEEE, 78 (9), Oct. 99, pp [8] W.J. Stenzel et al., A Compact High-Speed Parallel Multiplication Scheme, IEEE Transactions on Computers, C-6, 977, pp [9] S. assiliadis et al., Block Save Addition with Telescopic Sums, Proc. of the st EUROMICRO Conf., Como, Italy, Sept. -7, 99, IEEE Comp. Soc. Press, pp