EE 332 Design Project

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1 EE 332 Design Project Variable Gain Audio Amplifier TA: Pohan Yang Students in the team: George Jenkins Mohamed Logman Dale Jackson Ben Alsin Instructor s Comments: Lab Grade:

2 Introduction The goal of this project is was to design and construct an audio amplifier. The amplifier should be capable of amplifying audio signals without audible distortion across a bandwidth of 20-20kHz. The gain of the amplifier should be adjustable and the power output should be a minimum of.5w. Efficiency should also be taken into consideration when designing the amplifier. Architecture Design Design specifications Frequency range: 20Hz 20kHz (-3dB) Minimum input: 100mVpp Minimum output power: 0.5W Load Impedance: 8 Ω Block Diagram The following block diagram is representative of the overall design.

3 Discussion on the chosen architecture 1 st Stage - differential amplifier and feedback for gain adjustment The chosen architecture for the first stage is that of a differential amplifier. In class lectures, we have seen the importance of such a topology in circuit designs. The differential amplifier forms the basis for an opamp. Differential amplifiers can be used in a multitude of ways and for the purpose of this project, it will be used as a non-inverting amplifier. One particular thing about a differential amplifier is that we can use negative feedback to adjust the voltage gain of the amplifier. By using a voltage divider network of two resistors, we can change the amount of negative feedback to the amplifier which in turn is directly proportional to the gain. This can be achieved by simply changing the ratios of resistance between the two resistors in the network. To demonstrate this, pspice simulation software was used with an opamp. Please see the following illustrations: Fig A& B

4 Figure A Opamp schematic in pspice representative of our differential stage

Figure B - one particular resistor ratio for gain: R3/R1 ratio = 5kΩ/90Ω = Av 56 2 nd Stage The follower (common collector) Now that we have a voltage gain plan, we now need to keep that voltage up

5 Figure B - one particular resistor ratio for gain: R3/R1 ratio = 5kΩ/90Ω = Av 56 2 nd Stage The follower (common collector) Now that we have a voltage gain plan, we now need to keep that voltage up by increasing the current of the signal from our differential amplifier stage. So this stage needs to function as a current buffer. The emitter follower (or common collector) can help us achieve this. The efficiency is low for a follower topology which is why we would not use this for our final stage. The efficiency of a follower cannot exceed 25%. This is due to the fact that a follower wastes voltage and idle current. However, we will be working with relatively small values of current here and therefore this is not a major concern.

6 Follower with active load illustration 3 rd Stage Class AB power amplifier Our class AB amplifier is the final stage in this design. Class A designs have a conduction angle of 360 and have a limited peak signal swing in comparison to that of Class B which has a 180 conduction angle. Since Class B amplifiers only amplify half of the signal, Class B must be used in a complementary fashion to amplify the entire signal. Consequently, each transistor will amplify one half of the entire signal, so the work is divided in half for each. Class B has a maximum efficiency of 78.5% because it only wastes voltage. One thing about a class B topology is that there is a Vbe threshold voltage that must be exceeded before the transistor begins to conduct (and is therefore turned on). Before this threshold is exceeded, there is a dead zone where the transistor does not conduct. This leads to what is called crossover distortion. In order to correct this problem we prematurely turn on the transistor pair, we put a parallel branch of diodes on the bases of the transistor pair. We use one diode per transistor. The purpose of these diodes is to give the necessary Vbe voltage to each transistor to put it at the edge of conduction. We want to close the gap on the dead zone enough to minimize it, but at the same time we do not want to bias the transistor pair to be constantly on and therefore drain unnecessary excessive idle current. This is where the fine tuning of this stage comes into the picture while working on the bench in the lab. The amount of idle current flow for the transistors is controlled by the current through the diodes. Therefore, we use potentiometers at the top and bottom of the branches of the diode branches to minimize the idle current drain for the complementary transistors. This whole stage collectively is referred to as a Class AB stage since it is a hybrid of Class A and Class B operation. Because of the increased idle current, the Class AB has less efficiency than that of Class B. Class AB efficiency is limited to 50%.

7 It is also important to note that the purpose of the output stage is current gain, not voltage gain. The voltage gain is 1. It is a power stage because of the large amount of current it can deliver to a low impedance load. The first stage cannot do this by itself. It cannot produce enough current to maintain a significant voltage drop over a low impedance load. To the first stage a low impedance load looks like a short circuit and disturbs the operation of that stage. Class AB Topology Current Mirrors In practice, current mirrors are used as active loads for the differential amplifier as well as the follower. As shown in the class Midterm, using an ideal current source is the best choice for any active load. The closest we can get to that standard is by using an electronic current source. Our electronic current source in this case is another transistor. So, where we would normally see a resistor in the topology, we now have an additional transistor supplying current in the direction that we would want the ideal current source to supply this current. An Ideal current source also offers infinite impedance and constant current flow. Our electronic current source will offer us high impedance and near constant current flow. Because of this, we are able to achieve higher gain from our differential amplifier and better performance from the follower. Please see the following schematic for a basic current mirror topology. Current mirror using BJTs

8 Trade offs In choosing a specific topology, there are multiple considerations to choose from. For a Class B power stage output, you would have to be willing to tolerate crossover distortion in the application of the amplifier. However, it is more efficient than Class AB. Class AB gives better signal quality but has more idle current. If battery power consumption is a major consideration then I would consider biasing my Class AB as near to Class B as reasonably possible. On the other hand, using a Darlington Transistor pair seems to be a better design for most purposes. However, because of the higher value for current gain β, it is a good idea to put in an overload protection circuit for any spikes from transients that may occur that would destroy the transistors. However, this takes more time and requires more parts. The tradeoff here is cost and time in further research on constructing overload protection for this circuit topology. Circuit Design Design equations and calculations To achieve 0.5W power we use the relationship: ( ) We then arrive at ( ) So from 100mVpp to 5.6Vpp we must use a gain of 56. Because.100*56 = 5.6 So our minimum goal is to amplify our standard signal of 100mVpp by a gain of 56 without distortion. For a gain of 56 we need a resistor ratio of R1/R2 ratio = 5kΩ/90Ω = Vout/Vin= Av 56 Our differential pair can be treated separately using half circuit analysis. When analyzed using half circuit analysis we find that the circuit is a Common Emitter topology. The small signal differential mode gain of this stage is: Av =, using current sources Av = -gm*(ro Rsource) After putting the circuit together and fine tuning the lower NPN current mirror, the best value that worked is a value of 100KΩ. Assuming base current is negligible will give us an estimate of for mirror current.

9 Schematics Actual circuit used in this design *TIP 33C & TIP 34C Transistors used in place of Q10 & Q9 respectively in actual implementation

10 Alternate Design using Darlington transistors for Power Stage Simulation vs. physical implementation

13 Actual Actual 20Hz

Composite music signal amplification of actual circuit Results Maximum Output Power This section demonstrates the largest Vpk-pk that is not

14 Composite music signal amplification of actual circuit Results Maximum Output Power This section demonstrates the largest Vpk-pk that is not distorted/clipping and greater than or equal to ½ Watt while achieving -3dB bandwidth of 20Hz-20kHz. Both simulation and the actual circuit is used.

15 20Hz

16 20kHz Most at

Most at gain @ 20Hz Best case scenario max output A

17 Most at 20Hz Best case scenario max output A maximum output power of 912mW was achieved without distortion. This is calculated in the following way: Please see oscilloscope picture below. Best case scenario 1kHz

18 .5W Frequency Range The circuit is able to maintain.5 watts with -3dB bandwidth from 20Hz to 20kHz. This is shown in the simulation below. The smallest input that satisfies this is mV. 20kHz minimum input

19 20Hz minimum input For an actual implementation, the smallest input signal that satisfies the condition is 124mV: 20kHz minimum input

20 20Hz minimum input AC frequency Plot This section shows the frequency plot in simulation and is used to estimate parasitic capacitance. The breadboard offers some capacitance (as well as individual parts) which is not part of our computer simulation. Our frequency of interest is the frequency at which we see a -3dB drop.

21 AC frequency plot in decibels without 1030uF speaker coupling capacitor

22 AC frequency plot in decibels with 1030uF speaker coupling capacitor

23 Power plot of Rload with coupling cap In our actual implementation, we have to calculate what Vout/Vin ratio will give us a -3dB drop: Calculating AC -3dB Gain drop in the actual circuit: 5.72v/.17=33.64 = initial Gain 33.64*.7=23.55 = -3dB Gain drop We then take successive measures in logarithmic frequency steps until we get close to the drop off point:

25 4.28/.18 = ~3dB drop

26 Now we can use this information in the following equation: Rout is measured to be 5.1kΩ with an ohm meter. Parasitic capacitance of breadboard = ( )( ) = 93.62pF Transient analysis at 20kHz We can use transient analysis to see the estimate the slew rate of the amplifier. The slew rate is the maximum rate of change of voltage at the output of the amplifier. The capacitance to ground is what causes slew rate limitations. So, for a maximum rate of change of the output voltage for an input signal: Slew Rate SR = At 20kHz the simulation shows a slew rate of 0 which doesn t take into consideration any parasitic capacitances.

Simulation slew rate @20kHz At 20kHz the actual circuit shows a slew rate of = Conclusion After the amplifier has been built and tested it has met the specifications.

27 Simulation slew At 20kHz the actual circuit shows a slew rate of = Conclusion After the amplifier has been built and tested it has met the specifications. A circuit simulator is an excellent tool but the limitations of it should be kept in mind. Circuit simulators work well with ideal conditions. However, ideal is a limit that can only be approached but not reached in an actual implementation. This is why with precise parameters, a circuit would need to be fine-tuned on the bench while being tested. This is due to inherent tolerances that naturally exist. The audio amplifier was an exciting project and only represents one of many applications of semiconductor technology.

Final Design Project: Variable Gain Amplifier with Output Stage Optimization for Audio Amplifier Applications EE 332: Summer 2011 Group 2: Chaz

Final Design Project: Variable Gain Amplifier with Output Stage Optimization for Audio Amplifier Applications EE 332: Summer 2011 Group 2: Chaz Bofferding, Serah Peterson, Eric Stephanson, Casey Wojcik