EVALUATION KIT AVAILABLE Dual, 256-Tap, Volatile, Low-Voltage Linear Taper Digital Potentiometer

Transcription

1 19-514; Rev 2; 11/1 EVAUATION KIT AVAIABE Dual, 256-Tap, Volatile, ow-voltage General Description The dual, 256-tap, volatile, low-voltage linear taper digital potentiometer offers three end-to-end resistance values of 1kI, 5kI, and 1kI. Operating from a single +2.6V to +5.5V power supply, the device provides a low 35ppm/NC end-to-end temperature coefficient. The device features an I 2 C interface. The small package size, low supply operating voltage, low supply current, and automotive temperature range of the make the device uniquely suitable for the portable consumer market, battery backup industrial applications, and the automotive market. The is specified over the automotive -4NC to +125NC temperature range and is available in a 14-pin TSSOP package. Features S Dual, 256-Tap inear Taper Positions S Single +2.6V to +5.5V Supply Operation S ow < 1µA Quiescent Supply Current S 1kI, 5kI, 1kI End-to-End Resistance Values S I 2 C-Compatible Interface S Power-On Sets iper to Midscale S -4NC to + 125NC Operating Temperature Range Applications ow-voltage Battery Applications Portable Electronics Mechanical Potentiometer Replacement Offset and Gain Control Adjustable Voltage References/inear Regulators Automotive Electronics PART Ordering Information PIN-PACKAGE END-TO-END RESISTANCE (ki) AUD+ 14 TSSOP 1 MAUD+ 14 TSSOP 5 NAUD+ 14 TSSOP 1 Note: All devices are specified over the -4NC to +125NC operating temperature range. +Denotes a lead(pb)-free/ros-compliant package. Functional Diagram V DD A A A SDA A A1 A2 I2C ATC POR ATC 256 DECODER 256 DECODER B B B GND Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 Dual, 256-Tap, Volatile, ow-voltage ABSOUTE MAXIMUM RATINGS V DD to GND...-.3V to +6V _, _, _ to GND...-.3V to the lower of (V DD +.3V) and +6V All Other Pins to GND...-.3V to +6V Continuous Current into _, _, and _... Q5mA M... Q2mA N... Q1mA Continuous Power Dissipation (T A = +7NC) 14-Pin TSSOP (derate 1m/NC above +7NC) m Operating Temperature Range... -4NC to +125NC Junction Temperature...+15NC Storage Temperature Range NC to +15NC ead Temperature (soldering, 1s)...+3NC Soldering Temperature (reflow)...+26nc Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EECTRICA CARACTERISTICS (V DD = +2.6V to +5.5V, V _ = V DD, V _ = GND, T A = -4NC to +125NC, unless otherwise noted. Typical values are at V DD = +5V, T A = +25NC.) (Note 1) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS Resolution N 256 Tap DC PERFORMANCE (Voltage-Divider Mode) Integral Nonlinearity IN (Note 2) SB Differential Nonlinearity DN (Note 2) SB Dual Code Matching Register A = register B SB Ratiometric Resistor Tempco (DV /V )/DT; no load +5 SB Full-Scale Error Code = FF Zero-Scale Error Code = DC PERFORMANCE (Variable-Resistor Mode) Integral Nonlinearity R-IN V DD > +2.6V V DD > +4.75V M N M N ±1. ±2.5 M ±.5 ±1. N ±.25 ±.8 ±.4 ±1.5 M ±.3 ±.75 N ±.25 ±.5 Differential Nonlinearity R-DN V DD > 2.6V (Note 3) SB DC PERFORMANCE (Resistor Characteristics) V DD > 2.6V 25 6 iper Resistance (Note 4) R V DD > 4.75V 15 2 Terminal Capacitance C _, C _ Measured to GND 1 pf iper Capacitance C _ Measured to GND 5 pf End-to-End Resistor Tempco TC R No load 35 ppm/nc End-to-End Resistor Tolerance DR iper not connected % SB SB SB I 2

3 EECTRICA CARACTERISTICS (continued) (V DD = +2.6V to +5.5V, V _ = V DD, V _ = GND, T A = -4NC to +125NC, unless otherwise noted. Typical values are at V DD = +5V, T A = +25NC.) (Note 1) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS AC PERFORMANCE Crosstalk (Note 5) -9 db -3dB Bandwidth Total armonic Distortion Plus Noise B Code = 8, 1pF load, V DD = +2.6V 6 M 15 N 75 TD+N Measured at ; V _ = 1V RMS at 1kz.15 % iper Settling Time (Note 6) t S M 1 3 N 2 POER SUPPIES Supply-Voltage Range V DD V Standby Current Digital inputs = V DD or GND 1 FA DIGITA INPUTS Minimum Input igh Voltage V I 7 % x V DD Maximum Input ow Voltage V I 3 % x V DD Input eakage Current FA Input Capacitance 5 pf TIMING CARACTERISTICS (Notes 7, 8) Maximum Frequency f 4 kz Setup Time for START Condition t SU:STA.6 Fs old Time for START Condition t D:STA.6 Fs igh Time t IG.6 Fs ow Time t O 1.3 Fs Data Setup Time t SU:DAT 1 ns Data old Time t D:DAT Fs SDA, Rise Time t R.3 Fs SDA, Fall t F.3 Fs Setup Time for STOP Condition t SU:STO.6 Fs Bus Free Time Between STOP and START Conditions t BUF Minimum power-up rate =.2V/Fs 1.3 Fs Pulse-Suppressed Spike idth t SP 5 ns Capacitive oad for Each Bus C B 4 pf Note 1: All devices are 1% production tested at T A = +25NC. Specifications overtemperature limits are guaranteed by design and characterization. Note 2: DN and IN are measured with the potentiometer configured as a voltage-divider (Figure 1) with _ = V DD and _ = V. The wiper terminal is unloaded and measured with an ideal voltmeter. Note 3: R-DN and R-IN are measured with the potentiometer configured as a variable resistor (Figure 1). DN and IN are measured with the potentiometer configured as a variable resistor. _ is unconnected and _ = GND. For V DD = +5V, the wiper terminal is driven with a source current of 4FA for the 1kI configuration, 8FA for the 5kI configuration, and 4FA for the 1kI configuration. For V DD = +2.6V, the wiper terminal is driven with a source current of 2FA for the 1kI configuration, 4FA for the 5kI configuration, and 2FA for the 1kI configuration. Note 4: The wiper resistance is the worst value measured by injecting the currents given in Note 3 into _ with _ = GND. R = (V - V )/I. kz ns 3

4 Note 5: Drive A with a 1kz GND to V DD amplitude tone. A = B = GND. No load. B is at midscale with a 1pF load. Measure B. Note 6: The wiper settling time is the worst-case to 5% rise time, measured between tap and tap 127. _ = V DD, _ = GND, and the wiper terminal is loaded with 1pF capacitance to ground. Note 7: Digital timing is guaranteed by design and characterization, not production tested. Note 8: The clock period includes rise and fall times (t R = t F ). All digital input signals are specified with t R = t F = 2ns and timed from a voltage level of (V I + V I )/2. N.C. Figure 1. Voltage-Divider and Variable Resistor Configurations (V DD = 5V, T A = +25 C, unless otherwise noted.) Typical Operating Characteristics SUPPY CURRENT (µa) SUPPY CURRENT vs. TEMPERATURE V DD = 5V V DD = 2.6V toc1 SUPPY CURRENT (µa) 1, SUPPY CURRENT vs. DIGITA INPUT VOTAGE V DD = 2.6V V DD = 5V toc2 IDD (µa) SUPPY CURRENT vs. SUPPY VOTAGE toc TEMPERATURE ( C) DIGITA INPUT VOTAGE (V) V DD (V) TO- RESISTANCE (kω) RESISTANCE (-TO-) vs. (1kI) toc4 -TO- RESISTANCE (kω) RESISTANCE (-TO-) vs. (5kI) toc5 RESISTANCE (-TO-) (ki) RESISTANCE (-TO-) vs. (1kI) toc

5 (V DD = 5V, T A = +25 C, unless otherwise noted.) IPER RESISTANCE (Ω) IPER RESISTANCE vs. IPER VOTAGE (1kI) V DD = 5V V DD = 2.6V IPER VOTAGE (V) toc7 END-TO-END RESISTANCE % CANGE Typical Operating Characteristics (continued) END-TO-END RESISTANCE % CANGE vs. TEMPERATURE 1kI 1kI TEMPERATURE (NC) 5kI toc8 DN (SB) VARIABE-RESISTOR DN vs. (1kI) I IPER = 4µA toc VARIABE-RESISTOR DN vs. (5kI) I IPER = 8µA toc VARIABE-RESISTOR DN vs. (1kI) I IPER = 4µA toc VARIABE-RESISTOR IN vs. (1kI) I IPER = 4µA toc DN (SB) DN (SB) IN (SB) VARIABE-RESISTOR IN vs. (5kI) I IPER = 8µA toc VARIABE-RESISTOR IN vs. (1kI) I IPER = 4µA toc VOTAGE-DIVIDER DN vs. (1kI) MAX5386 toc IN (SB) IN (SB) DN (SB)

6 (V DD = 5V, T A = +25 C, unless otherwise noted.) DN (SB) VOTAGE-DIVIDER DN vs. (5kI) toc16 DN (SB) Typical Operating Characteristics (continued) VOTAGE-DIVIDER DN vs. (1kI) toc17 IN (SB) VOTAGE-DIVIDER IN vs. (1kI) toc VOTAGE-DIVIDER IN vs. (5kI) MAX5386 toc VOTAGE-DIVIDER IN vs. (1kI) toc2 TAP-TO-TAP SITCING TRANSIENT (CODE 127 TO 128) (1kI) toc21 V - 2mV/div.2.2 IN (SB) IN (SB) V/div ns/div TAP-TO-TAP SITCING TRANSIENT (CODE 127 TO 128) (5kI) toc22 TAP-TO-TAP SITCING TRANSIENT (CODE 127 TO 128) (1kI) toc23 V - 2mV/div V - 2mV/div 5V/div 5V/div 1µs/div 1µs/div 6

7 (V DD = 5V, T A = +25 C, unless otherwise noted.) Dual, 256-Tap, Volatile, ow-voltage POER-ON IPER TRANSIENT (CODE TO 128) Typical Operating Characteristics (continued) toc24 OUTPUT 2V/div GAIN (db) 1-1 MIDSCAE FREQUENCY RESPONSE V IN = 1V P-P C = 1pF M toc25 V DD 2V/div -2 N 2µs/div , 1, FREQUENCY (kz) CROSSTAK (db) CROSSTAK vs. FREQUENCY toc26 TD+N (%) TOTA ARMONIC DISTORTION PUS NOISE vs. FREQUENCY M.1.8 N.6 toc N M FREQUENCY (kz) FREQUENCY (kz) 7

8 TOP VIE A A A V DD SDA Pin Configuration B 4 11 A B 5 1 A1 B 6 9 A2 I.C. 7 8 GND TSSOP Pin Description PIN NAME FUNCTION 1 A Resistor A igh Terminal. The voltage at A can be higher or lower than the voltage at A. Current can flow into or out of A. 2 A Resistor A iper Terminal 3 A Resistor A ow Terminal. The voltage at A can be higher or lower than the voltage at A. Current can flow into or out of A. 4 B Resistor B igh Terminal. The voltage at B can be higher or lower than the voltage at B. Current can flow into or out of B. 5 B Resistor B iper Terminal 6 B Resistor B ow Terminal. The voltage at B can be higher or lower than the voltage at B. Current can flow into or out of B. 7 I.C. Internally Connected. Connect to GND. 8 GND Ground 9 A2 Address Input 2. Connect to V DD or GND. 1 A1 Address Input 1. Connect to V DD or GND. 11 A Address Input. Connect to V DD or GND. 12 SDA I 2 C-Compatible Serial-Data Input/Output. A pullup resistor is required. 13 I 2 C-Compatible Serial-Clock Input. A pullup resistor is required. 14 V DD Power-Supply Input. Bypass VDD to GND with a.1ff capacitor close to the device. 8

9 Detailed Description The dual, 256-tap, volatile, low-voltage linear taper digital potentiometer offers three end-to-end resistance values of 1kI, 5kI, and 1kI. The potentiometer consists of 255 fixed resistors in series between terminals _ and _. The potentiometer wiper, _, is programmable to access any one of the 256 tap points on the resistor string. The potentiometers are programmable independently of each other. The features an I 2 C interface. I 2 C Digital Interface The I 2 C interface contains a shift register that decodes the command and address bytes, routing the data to the appropriate control registers. Data written to a control register immediately updates the wiper position. ipers A and B power up in midposition, D[7:] = 8. Serial Addressing The operates as a slave device that receives data through an I 2 C-/SMBusK-compatible 2-wire serial interface. The interface uses a serial-data access (SDA) line and a serial-clock line () to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to the, and generates the clock that synchronizes the data transfer (Figure 2). The SDA line operates as both an input and an open-drain output. The SDA line requires a pullup resistor, typically 4.7kI. The line operates only as an input. The line requires a pullup resistor (typically 4.7kI) if there are multiple masters on the 2-wire interface, or if the master in a single-master system provides an open-drain output. Each transmission consists of a START (S) condition (Figure 3) sent by a master, followed by the 7-bit slave address plus the NOP/ bit (Figure 6), 1 command byte and 1 data byte, and finally a STOP (P) condition (Figure 3). START and STOP Conditions and SDA remain high when the interface is inactive. A master controller signals the beginning of a transmission with a START condition by transitioning SDA from high to low while is high. The master controller issues a STOP condition by transitioning the SDA from low to high while is high, after finishing communicating with the slave. The bus is then free for another transmission. t D:STA t SU:STD SDA t SU:DAT t SU:DTA t D:STA t O t IG t D-DAT t BUF t R t F START CONDITION (S) REPEATED START CONDITION (Sr) ACKNOEDGE (A) STOP CONDITION (P) START CONDITION (S) Figure 2. I 2 C Serial Interface Timing Diagram SMBus is a trademark of Intel Corp. 9

10 Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while is high. See Figure 4. Acknowledge The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data. See Figure 5. Each byte transferred requires a total of nine bits. The master controller generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, so the SDA line remains stable low during the high period of the clock pulse. Slave Address The includes a 7-bit slave address (Figure 6). The 8th bit following the 7th bit of the slave address is the NOP/ bit. Set the NOP/ bit low for a write command and high for a no-operation command. The device does not support readback. The device provides three address inputs (A, A1, and A2), allowing up to eight devices to share a common bus (Table 1). The first 4 bits (MSBs) of the factory-set slave addresses are always 11. A2, A1, and A set the next 3 bits of the slave address. Connect each address input to VDD or GND. Each device must have a unique address to share a common bus. SDA S P START CONDITION STOP CONDITION Figure 3. START and STOP Conditions SDA CANGE OF DATA AOED DATA STABE, DATA VAID Figure 4. Bit Transfer START CONDITION COCK PUSE FOR ACKNOEDGMENT NOT ACKNOEDGE SDA ACKNOEDGE Figure 5. Acknowledge 1

11 SDA START 1 1 A2 A1 A NOP/ ACK MSB SB Figure 6. Slave Address ACKNOEDGE O CONTRO BYTE AND DATA BYTE MAP INTO DEVICE REGISTERS ACKNOEDGE R7 R6 R5 R4 R3 R2 R1 R D7 D6 D5 D4 D3 D2 D1 D S A A A P SAVE ADDRESS COMMAND BYTE 1 DATA BYTE NOP/ Figure 7. Command and Single Data Byte Received Message Format for riting rite to the devices by transmitting the device s slave address with NOP/ (eighth bit) set to zero, followed by at least 2 bytes of information. The first byte of information is the command byte. The second byte is the data byte. The data byte goes into the internal register of the device as selected by the command byte (Figure 7 and Table 2). Command Byte Use the command byte to select the destination of the wiper data. See Table 2. Command Descriptions REG A: The data byte writes to register A and the wiper of potentiometer A moves to the appropriate position. D[7:] indicates the position of the wiper. D[7:] = h moves the wiper to the position closest to A. D[7:] = FFh moves the wiper to the position closest to A. D[7:] is 8h following power-on. Table 1. Slave Addresses ADDRESS INPUTS A2 A1 A SAVE ADDRESS GND GND GND 11 GND GND V DD 111 GND V DD GND 111 GND V DD V DD 1111 V DD GND GND 111 V DD GND V DD 1111 V DD V DD GND 1111 V DD V DD V DD

12 Dual, 256-Tap, Volatile, ow-voltage Table 2. I 2 C Command Byte Summary CYCE NO. START (S) ADDRESS BYTE COMMAND BYTE DATA BYTE A6 A5 A4 A3 A2 A1 A ACK (A) R7 R6 R5 R4 R3 R2 R1 R ACK (A) D7 D6 D5 D4 D3 D2 D1 D ACK REG A 1 1 A2 A1 A 1 1 D7 D6 D5 D4 D3 D2 D1 D REG B 1 1 A2 A1 A 1 1 D7 D6 D5 D4 D3 D2 D1 D (A) STOP (P) REGS A AND B 1 1 A2 A1 A D7 D6 D5 D4 D3 D2 D1 D REG B: The data byte writes to register B and the wiper of potentiometer B moves to the appropriate position. D[7:] indicates the position of the wiper. D[7:] = h moves the wiper to the position closest to B. D[7:] = FFh moves the wiper to the position closest to B. D[7:] is 8h following power-on. REGS A and B: The data byte writes to registers A and B and the wipers of potentiometers A and B move to the appropriate position. D[7:] indicates the position of the wiper. D[7:] = h moves the wipers to the position closest to _. D[7:] = FFh moves the wipers to the position closest to _. D[7:] is 8h following power-on. Applications Information Variable Gain Amplifier Figure 8 shows a potentiometer adjusting the gain of a noninverting amplifier. Figure 9 shows a potentiometer adjusting the gain of an inverting amplifier. Adjustable Dual Regulator Figure 1 shows an adjustable dual linear regulator using a dual potentiometer as two variable resistors. Adjustable Voltage Reference Figure 11 shows an adjustable voltage reference circuit using a potentiometer as a voltage-divider. V IN Figure 9. Variable Gain Inverting Amplifier V OUT V IN V OUT OUT1 OUT2 V OUT1 V OUT2 V+ MAX8866 IN SET1 SET2 Figure 8. Variable Gain Noninverting Amplifier Figure 1. Adjustable Dual inear Regulator 12

13 Variable Gain Current to Voltage Converter Figure 12 shows a variable gain current to voltage converter using a potentiometer as a variable resistor. CD Bias Control Figure 13 shows a positive CD bias control circuit using a potentiometer as a voltage-divider. Figure 14 shows a positive CD bias control circuit using a potentiometer as a variable resistor. Programmable Filter Figure 15 shows a programmable filter using a dual potentiometer. Offset-Voltage Adjustment Circuit Figure 16 shows an offset-voltage adjustment circuit using a dual potentiometer. 3.V IN OUT MAX637 V REF +5V VOUT GND Figure 11. Adjustable Voltage Reference Figure 13. Positive CD Bias Control Using a Voltage-Divider R3 +5V IS R1 R2 VOUT VOUT V OUT = -I S x ((R3 x (1 + R2/R1)) + R2) Figure 12. Variable Gain I-to-V Converter Figure 14. Positive CD Bias Control Using a Variable Resistor 13

14 VIN B R3 B B R1 VOUT +5V A A VOUT A A A R2 B A B B Figure 15. Programmable Filter Figure 16. Offset-Voltage Adjustment Circuit PROCESS: BiCMOS Process Information Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoS status. PACKAGE TYPE PACKAGE CODE OUTINE NO. AND PATTERN NO. 14 TSSOP U

15 REVISION NUMBER REVISION DATE DESCRIPTION Revision istory PAGES CANGED 1/1 Initial release 1 4/1 Added Soldering Temperature in Absolute Maximum Ratings; corrected code in Conditions of -3dB Bandwidth specification in Electrical Characteristics 2 11/1 Updated figures for optimal circuit operation 12, 13, 14 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.