A multi-cell battery pack monitoring chip based on 0.35-µm BCD technology for electric vehicles

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1 LETTER IEICE Electronics Express, Vol.12, No.12, 1 12 A multi-cell battery pack monitoring chip based on 0.35-µm BCD technology for electric vehicles Xiaofei Wang 1, Hong Zhang 2, Jianrong Zhang 2, Changyi Li 2, Xin Du 2, and Yue Hao 1a) 1 School of Microelectronics, Xidian University, Xi an , China 2 Department of Microelectronics, Xi an Jiaotong University, Xi an , China a) haoyue@xidian.edu.cn Abstract: This letter presents a multi-cell battery pack monitoring chip for electric vehicles (EVs). A multiplexer based on p- and n-type lateral doublediffused MOS (LDMOS) transistors is proposed to select the battery voltage in a battery pack with up to 12 series-connected battery cells. Measuring of the cell voltages is realized by a 12-bit incremental ΣΔ analog-to-digital converter (ADC) with offset cancellation. Fabricated in a 0.35-µm Bipolar- CMOS-DMOS (BCD) technology, measurement results show that an absolute conversion error of less than 3 mv is obtained. The conversion time for each cell is less than 600 µs under a 1-MHz clock signal generated by an internal oscillator. The chip area is mm 2 and the current consumption is 510 µa in measuring mode, resulting in a operation power loss of 25.5 mw under a 50-V power supply. Keywords: battery monitoring, HV MUX, incremental ΣΔ ADC, electric vehicle, BMS Classification: Integrated circuits References [1] E. Meissner and G. Richter: J. Power Sources 116 (2003) 79. DOI: / S (02) [2] L. Lu, X. Han, J. Li, J. Hua and M. Ouyang: J. Power Sources 226 (2013) 272. DOI: /j.jpowsour [3] S. Peterson, J. Whitacre and J. Apt: J. Power Sources 195 (2010) DOI: /j.jpowsour [4] S. S. Eaves: U. S. Patent (1997). [5] L. G. McIlrath: IEEE J. Solid-State Circuits 36 (2001) 846. DOI: / [6] X. Wang, H. Zhang, G. Yang, C. Li and Y. Hao: IEEE ICSICT Tech. Dig. (2014) O [7] J. Markus, J. Silva and G. C. Temes: IEEE Trans. Circuits Syst. I, Reg. Papers 51 (2004) 678. DOI: /TCSI [8] Analog Devices, Inc.: AD7280 Datasheet (2008) [9] Linear Technology, Inc.: LTC6803 Datasheet (2011) 1

2 1 Introduction Usually, the power system of electric vehicle (EV) is composed of a large number of series or parallel connected lithium-ion batteries. In order to guarantee safety and prolong lifetime of the battery, various battery management systems (BMS) are employed to ensure that the batteries operate in safe and reliable voltage and temperature range [1]. Monitoring the voltage of each battery cell and the ambient temperature is indispensible for a BMS to manage and control the batteries effectively [2]. As there are a large number of batteries in the EV power system, an effective way is to divide the batteries into series-connected packs that include a given number of cells and monitor each pack with a single chip [3]. However, the total voltage of a battery pack is about several tens of volts, imposing big challenges on the design of the front analog multiplexer (MUX) in the monitoring chip. Additionally, for those BMS algorithms relying on open circuit voltages (OCV) of the batteries, the required measurement precision of cell voltages is often in the range of several mili-volts [2], which is tough for implementation of the analog-to-digital converter (ADC) in the noisy environment of EVs. In this paper, a monitoring chip fabricated in a 0.35-µm Bipolar-CMOS-DMOS (BCD) technology that can monitor a lithium battery pack with up to 12 seriesconnected cells is presented. With an internal temperature sensor, the presented chip can also monitor the operational temperature of the battery pack. In order to avoid using MUX with high-voltage (HV) drivers [4], the analog MUX in the presented monitoring chip is implemented with composite n- and p-type lateral double-diffused MOS (LDMOS) transistors controlled by the low-voltage selection bus. The selected cell voltage or the temperature sensor voltage from the MUX is mapped into low-voltage differential signals by a switched-capacitor level shifter circuit for A/D conversion. Because both the cell voltage and the sensor voltage are almost DC signals, low power ADC types such as successive approximation register (SAR) ADC and ADC can be chosen. However, SAR ADC tends to be interfered in a noisy environment, because it performs the conversion for a single sample of the input voltage. Additionally, traditional low-order ADC without dithering techniques is also not suitable for DC signals because of pattern noise issues [5]. In order to utilize the signal-average advantage of techniques, a 12-bit second-order incremental ADC which is also described in [6] is adopted for the presented chip. A two-step calibration algorithm is adopted to cancel the conversion offset and improve the absolute precision. 2 Circuit description 2.1 Architecture of the proposed monitoring chip The proposed chip is designed to monitor a battery pack with up to 12 seriesconnected battery cells under the control of an external micro-control-unit (MCU) in the BMS, as shown in Fig. 1. Because the total voltage of the battery pack is near 50 V, a 85-V BCD technology is chosen for the chip for safety. In order to power the chip directly from the batteries, a regulator is integrated in the chip to provide low-voltage 5-V and 3-V power supplies for the analog and digital circuits except for the MUX and the level shifter. A reference generator 2

3 based on a bandgap reference is used to provide a reference voltage of about 3 V for the ADC and other bias signals for the analog circuits in the chip. An oscillator (OSC) is also designed to provide a clock signal of about 1-MHz frequency for the ADC and the digital control circuits. Both the external and internal temperature sensors can be used to monitor the operational temperature of the battery pack. Overheat protection circuit based on the internal temperature sensor is also integrated in the chip (not shown in Fig. 1). The digital control circuit performs the functions including communication with the MCU, executing the commands from the MCU, calibration control of the ADC, storage of the ADC results, and etc. Whenever the digital control circuit receives a command from the MCU via the Serial Peripheral Interface (SPI) to acquire the voltage of a designated battery cell or a temperature sensor, the MUX selects the corresponding signals under the control of the selection bus. The selected signal pair (V H and V L ) is mapped into low-voltage (LV) domain differential signals by a switched-capacitor based level shifter circuit and then converted into digital word by the 12-bit ADC. The conversion results are then either transmitted to the MCU via the SPI or stored in the internal registers. If no command is detected by the digital control circuit in a given interval, all analog circuits except the voltage regulator are switched into sleeping mode to reduce power consumption. The internal temperature sensor is designed based on a proportional-to-absolute-temperature current generator. The regulator, reference generator, OSC, and the digital control circuit in the proposed chip are realized with traditional circuit techniques and are not discussed in this paper. Fig. 1. Block diagram of the proposed multi-cell battery pack monitoring chip. 2.2 HV MUX The analog MUX is used to select the voltage of a designated battery cell or temperature sensor under the control of the selection bus. The structure of the MUX in this paper is given in Fig. 2(a), which contains 26 switches controlled by corresponding control signals. The output voltages of the MUX (V H and V L ) are selected out from the battery and temperature sensor voltages according to Fig. 2(a). The control signals, T 1, T 2, H 1 H 12, and L 1 L 12, are obtained from a 3

4 4-bit selection bus by an encoding circuit (not given in the figure), and are in the voltage domain of 05 V. For example, if the top cell (B12) is to be selected, only H 12 and L 12 are switched to high state while other control signals are kept low. Therefore, V 12 and V 11 are passed to V H and V L by SH 12 and SL 12, respectively. V TSI and V TSE are the voltages of the internal and external temperature sensor, respectively. The voltage of a single lithium battery cell is usually in the range of 2:54:2 V, resulting in a maximum voltage (V 12, also V þ of the chip) of over 50 V. In order to pass the HV signals to the output of the MUX, HV MOS transistors must be employed. However, HV transistors in most commercial BCD technologies are often realized as LDMOS transistors, which can only withstand high drain-source and drain-gate voltages (V DS and V DG ). Normally, the allowable gate-source voltage (V GS ) for LDMOS is in LV domain. If n-ldmos is used to pass a HV signal under the control of a LV signal, a driver must be used to generate a gate signal larger than the input signal [4], resulting in complex circuit topology. On the other hand, breakdown may occur if a p-ldmos is used to pass a HV signal directly under the control of a LV signal. In order to avoid design of HV drivers and ensure safety, a composite HV switch structure based on both n- and p-ldmos transistors for the MUX is proposed. All switches used to pass the battery voltages (SH 1 SH 12 and SL 2 SL 12 ) are HV switches with the same structure. The proposed HV switch in the MUX to generate V H is given in Fig. 2(b), in which only SH 12,SH 11 and a common block for all switches is given for simplicity. The main switch structure of HV switch comprises a p-ldmos pair (DP 1;i and DP 2;i, i ¼ 1; 2; ; 12) and a n-ldmos pair (DN 1;i and DN 2;i ). The gate nodes of DN 1;i and DN 2;i are controlled by H i directly, while the gate nodes of DP 1;i and DP 2;i are connected to another n-ldmos pair (DN 3;i and DN 4;i ) controlled by H i. When input signal is large than 5 V, DN 1;i and DN 2;i are always in off-state even if the control signal is on. The current sources I 1;i and I 2;i (about 0.5 µa) are realized with LV NMOS transistors. The turn-on process Fig. 2. (a) (b) The proposed HV MUX: (a) overall structure; (b) schematic of HV switches for V H ; (c) schematic of LV switch. (c) 4

5 of the HV switch is analyzed by taking SH 11 for example as following. When H 11 is high, DN 3;11 and DN 4;11 are turned on by H 11, and the value of resister R 1;11 is designed to generate a voltage drop near 3 V to turn on DP 1;11. Because DN 4;11 is on, I 2;11 sinks current from the source follower comprising DP 3,DP 4, and MP 6 in the common block via the reversely biased Zener diode (Z 1;11 ), which drops the gate voltage of DP 2;11 down, and turns it on. V 11 is then passed to V H accurately. The current source I 3 is designed to provide a biasing current slightly larger than I 2;11 for the source follower. As the common block is powered by V 12, it can be derived that the source-gate voltage (V SG )ofdp 2;11 is V SG,DP2,11 ¼ V H ðv H þ V SG,DP4 V Z1,11 Þ¼V Z1,11 V SG,DP4 ; where V Z1,11 is the Zerner voltage of Z 1;11, which is about 4 V for the technology in this paper. Because only very low current flows through DP 4, V SG,DP4 is lower than 1 V. Therefore, V SG,DP2 is about 3 V, ensuring a safe on-state for DP2. When H 11 is high, other control signals are low. Taking SH 12 for example, DP 1;12 is turned off because no current flows through R 1;12 when H 12 is low. For DP 2;12, because DN 3;12 is off and no current flows through Z 1;12, the gate voltage of DP 2;12 equals to the output voltage of the source follower (i.e. V H þ V SG,DP4 ). Therefore, DP 2;12 is in a safe off-state. DN 1;i and DN 2;i in all switches are used to avoid the loss of DP 1;i and DP 2;i when passing input voltages lower than 5 V, especially for SH 1 and SL 2. The on/off procedure is similar for all switches except for a little difference for the on-state of SH 12. When SH 12 is on, V H equals to V 12, which can t turn on DP 4 in the common block. This results in a V SG,DP2,12 slightly lower than that of other HV switches when they are on, but it is still enough for turn on DP 2;12 of SH 12. Because the input voltages for S L1,S T1 and S T2 are always lower than 5 V, their circuits are simpler and can be realized with a same LV switch structure, with an example circuit for V TSI (ST 2 ) shown in Fig. 2(c). The main transistor in the LV switch circuit is DN 7. When T 2 is low, its inverted signal turns DN 6 on and drops the gate of DN 7 to a voltage near ground, which turns DN 7 off. On other hand, when T 2 is high, the gate voltage of DN 7 is pulled up to a value of (V TSI þ V SG,MP8 þ V Z2 ), which ensures a safe on-state of DN 7 and passes V TSI to V H precisely. The implementation of the switch network for V L is similar with that for V H, which is not given for simplicity. The simulated results of the MUX under the condition that each battery has an equal voltage of 5 V and V TSI is 2 V are given in Fig. 3. The control signals are arranged that the bottom cell, the top cell and V TSI ð1þ Fig. 3. Simulated switching performance of the MUX (the bottom cell, the top cell and V TSI are selected sequentially). 5

6 are selected to the output of the MUX sequentially. The waveforms show that accurate multiplexing is obtained with a maximum transition time of about 3.7 µs. 2.3 Switched-capacitor level shifter The absolute voltages of the MUX output are dependent on which battery or senor is selected, and in most cases, the MUX output voltages are in HV domain. However, the voltage of each battery is essentially a LV value, therefore, it is practical to use a level shifter to convert the difference between V H and V L of the MUX into a LV value for a LV ADC. In this paper, an efficient switched-capacitor level shifter is proposed to convert the MUX output into sampled differential signals, as given in Fig. 4(a). As can be seen, the output signals of the MUX, V H and V L, are passed to the left plates of C 1 and C 2 by the 4 switches (SW 1 SW 4 ) alternatively under the control of a pair of non-overlapped clock signals, 1 and 2. With the control scheme given in Fig. 5(a), if C 1 C 4 have equal values, the differential and common-mode (CM) output of the level shifter in 2 phase can be derived as ( V out,diff ¼ V OP V ON ¼ðV H V L Þ V REF ; ð2þ V out,cm ¼ðV OP þ V ON Þ=2 ¼ V CM where V REF and V CM are the reference and CM voltage of the ADC, respectively. The switches SW 1 SW 4 are required to pass HV signals under control of LV clock signals. In order to avoid usage of LDMOS, a charge-pump based switch structure is employed, as given in Fig. 4(b). With the proposed structure, only LV MOS transistors are used to pass the HV signals. It should be noted that metaloxide-metal (MOM) capacitors are chosen to withstand HV signals. (a) (b) Fig. 4. (a) Topology of the level shifter; (b) circuit realization of dash box in (a). The simulated results of the level shifter are given in Fig. 5, which shows that V H and V L are converted into sampled differential signals correctly. 2.4 The 12-bit incremental ADC Incremental ADC is a good choice for DC signal measurement in noisy environment [7]. It is similar with traditional ADC, except for that its integrator and decimation filter are both reset at the beginning of each new conversion. Highorder incremental ADC can obtain high resolution within less conversion time, but tends to be unstable. For battery monitoring, a second-order modulator is 6

7 Fig. 5. Simulated results of the level shifter with different V H and V L values. enough for 12-bit precision. Therefore, a second-order incremental modulator with single-bit quantizer and single feedback loop is adopted, as shown in Fig. 6. The coefficients b, c 1, and c 2 are in the range of 01. Fig. 6. Structure of the 2nd-order incremental ADC in the proposed chip. Similar with the time-domain analysis in [7], the output sequence of the first integrator after reset can be derived as V 1 ½0Š ¼0 V 1 ½1Š ¼bðV in ½0Š d 0 V REF Þ V 1 ½2Š ¼bðV in ½0ŠþV in ½1Š d 0 V REF d 1 V REF Þ. ; ð3þ V 1 ½N 1Š ¼b XN 2 ðv in ½kŠ d k V REF Þ k¼0 where V REF is the reference voltage of the DAC, d k is the output of the comparator in the kth cycle, and N is the number of clock cycles needed for one conversion. Similarly, the output of the 2nd integrator can be described as follows: V 2 ½0Š ¼0 V 2 ½1Š ¼V 2 ½0Šþc 1 V 1 ½0Š c 2 d 0 V REF V 2 ½2Š ¼c 1 ðv 1 ½1ŠþV 1 ½0ŠÞ c 2 ðd 0 V REF þ d 1 V REF Þ.. V 2 ½NŠ ¼c 1 b XN 1 l¼0 X l 1 k¼0 X N 1 ðv in ½kŠ d k V REF Þ c 2 d l V REF l¼0 : ð4þ 7

8 Assuming that V in is constant, the first term of V 2 ½NŠ can be calculated as c 1 b XN 1 l¼0 X l 1 k¼0 V in ½kŠ ¼c 1 b NðN 1Þ V in : 2 With reasonable scaling parameters, V 2 ½NŠ should be bounded in the range of V REF, resulting in the following relationship from Eq. (4) and (5):! 2V ref c 1 b XN 1 X l 1 X N 1 d k c 2 d l l¼0 k¼0 l¼0 V in 2V REF c 1 bnðn 1Þ < ð6þ c 1 bnðn 1Þ Eq. (6) can be regarded as the difference between V in and its digital representation. Therefore, the equivalent value of one least significant bit (LSB) can be found as 4V REF V LSB ¼ c 1 bnðn 1Þ : ð7þ Eq. (7) describes the relationship between the achievable precision and the required number of cycles for the incremental modulator. It can be estimated from Eq. (7), if c 1 ¼ b ¼ 0:5, only 256 clock cycles are required for a 12-bit precision. The DAC and the scaling coefficients in Fig. 6 are realized with switched capacitor structure, and the comparator is realized as a low-power dynamic comparator because the modulator can tolerate large comparator offset. To ensure wide output range of each integrator, a two-stage class-ab operational transconductance amplifier (OTA) is employed for each integrator, as given in Fig. 7 (bias and common-mode feedback (CMFB) circuits are not given for simplicity). ð5þ Fig. 7. The class-ab OTA in each integrator of the ADC. The low-pass decimation filter is also an important block of the incremental ADC. A 2nd-order cascaded integrator comb (CIC) decimation filter is adopted for the proposed ADC, as shown in Fig. 8, which is featured with excellent suppression of periodic noise with low circuit area consumption [7]. As high absolute precision is required for battery monitoring, the offset of the ADC must be cancelled out. A systematic two-step offset cancellation scheme is employed in this paper and implemented by the digital control circuits. In the first step, the cathode voltage of the designated cell is passed to both V H and V L of the MUX. The offset of the ADC is obtained from the conversion results of the 0-V 8

9 IEICE Electronics Express, Vol.12, No.12, 1 12 Fig. 8. Structure of the 2nd order CIC decimation filter of the ADC. difference between VH and VL. In the second step, both anode and cathode voltage of the cell are passed to VH and VL of the MUX, respectively. Calibrated output is then obtained by subtracting the offset from the conversion results in the second step. The price is additional 256 clock cycles needed by the calibration. In practical realization, about 20 additional clock cycles are required in each step for settling of analog signals in the MUX, level shifter, and the ADC. With a clock frequency of 1 MHz, the total conversion time for each cell is less than 600 µs. 3 Chip fabrication and measurement results The proposed multi-cell lithium battery pack monitoring chip is designed and fabricated in a 85-V 0.35-µm BCD technology. The chip area is 4 3:8 mm2, with chip photo shown in Fig. 9. An example battery monitoring system based on the presented monitoring chip is shown in Fig. 10, in which the proposed chip with a test package is directly powered by a battery pack containing 12 series-connected lithium battery cells. An ARM development board is used to control the monitoring Fig. 9. Fig. 10. Chip photo of the proposed monitoring chip. An example battery monitoring system based on the presented chip. 9

10 chip via the LV SPI. A PC connected to the ARM board is also employed to provide a graphic user interface. If no valid SPI communication occurs in a given duration, the monitoring chip will switch into sleeping mode to reduce power consumption. The wake-up process can be triggered by any valid SPI command received by the monitoring chip. The measured wake-up process of the monitoring chip is given in Fig. 11, in which a battery voltage measuring command is sent from the ARM board to the monitoring chip in the period when the chip select signal (nss) of the SPI bus is pulled down (the waveforms on SCLK, MISO, and MOSI signals of the SPI bus are not shown). As can be seen, about 51 ms after the command, the monitoring chip is switched to normal operation mode, and the internal reference signal (V ref ) of the ADC settles to its final value of V. Fig. 11. Measured wake-up process triggered by a SPI command. After the battery voltage of each cell is converted into digital word by the ADC and stored into corresponding registers, the conversion results can be read out by a battery voltage acquiring command. The measured SPI waveforms of the conversion results for a designated cell with a voltage of V is given in Fig. 12, in which the analog voltage of the cell is measured by a high-precision voltage meter. The 8 LSB s and 4 MSB s of the 12-bit results are stored in the first register and the 4 LSB s of the second register, respectively. Therefore, the conversion results, D out, can be read out as 0xA54 from Fig. 12. The converted battery voltage, V bat, is calculated as V through the relation V bat ¼ 2V ref ðd out =4095Þ. Therefore, the conversion error is less than 1 mv. Fig. 12. SPI waveforms for reading out the conversion results of a V battery. 10

11 In order to evaluate the monitoring precision in a wide input voltage range, the top battery in the pack is replaced with a high-precision programmable voltage source. The monitoring chip is configured to select the top battery, and the A/D conversion results with various input voltages are readout through the SPI. The measured maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC in the input range of 05 V are 0.9 LSB and 2 LSB, respectively, as shown in Fig. 13. The measured absolute unadjusted conversion error is less than 3 mv, as shown in Fig. 14. Fig. 13. Measured DNL and DNL of the ADC. Fig. 14. Measured unadjusted conversion error in the voltage range of 05 V. When the chip operates in sleeping and operating mode, the measured current consumptions are 20 µa and 510 µa, resulting in power losses of 1 mw and 25.5 mw for a 50-V power supply, respectively. The performances are summarized in Table I, with comparison to 2 commercial battery monitoring chips. 11

12 Table I. Performance summary and comparison. Parameters [8] [9] This work Number of battery channels External temp. sensors Internal temp. sensor yes no yes Max. batter pack voltage (V) ADC type Incremental SAR Incremental ADC precision (bit) Max. ADC DNL (LSB) Max. ADC INL (LSB) Unadjusted conversion error 10 mv (5 V input) 1% 3 mv (5 V input) Conversion time for one cell 1.08 ms 1 µs 600 µs Technology µm BCD Chip area mm 3:8 mm Standby current (µa) Operation current (ma) Standby power loss (mw) 0.6 (V DD ¼ 50 V) 0.12 (V DD ¼ 30 V) 1 (V DD ¼ 50 V) Operation power loss (mw) 39 (V DD ¼ 50 V) 300 (V DD ¼ 30 V) 25.5 (V DD ¼ 50 V) 4 Conclusion A multi-cell battery pack monitoring chip for EVs is realized in a 0.35-µm BCD technology. With a HV MUX based on composite n-ldmos and p-ldmos transistors, 12 series-connected battery cells can be monitored. A temperature sensor is also integrated in the chip for temperature monitoring and overheat protection. An efficient switched-capacitor level shifter is adopted to convert the output of MUX into sampled differential signals for the ADC. A 2nd-order incremental ADC with a two-step offset cancellation scheme is employed for A/D conversion of the cell voltage or the temperature senor output voltage. Measurement results show that a DNL of 0.9 LSB, an INL of 2 LSB and an absolute conversion error of less than 3 mv are obtained. The chip area is 4 3:8 mm 2 and the current consumption is 510 µa in measuring mode. Acknowledgments This work was supported by the NSFC of China under contract of , and the Science and Technology Project of Shaanxi Province under contract of 2014K