RT7264E. 4A, 21V, 500kHz Synchronous Step-Down Converter. Features. General Description. Ordering Information. Applications

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1 4A, 21V, 500kHz Synchronous StepDown Converter General Description The is a synchronous stepdown regulator with an internal power MOSFET. It achieves 4A of continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cyclebycycle current limiting and thermal shutdown. An adjustable softstart reduces the stress on the input source at startup. The requires a minimal number of readily available external components, providing a compact solution. Ordering Information Package Type QW : WDFN14L 4x3 (WType) SP : SOP8 (Exposed PadOption 2) Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC JSTD020. Suitable for use in SnPb or Pbfree soldering processes. Features Wide Input Range : 4.5V to 21V Adjustable Output from 0.808V to 15V 4A Output Current 120mΩ/40mΩ Internal Power MOSFET Switch Internal Compensation Minimizes External Parts 500kHz Fixed Switching Frequency Synchronized External Clock from 300kHz to 2MHz Adjustable SoftStart CyclebyCycle Over Current Limit Thermal Shutdown Protection Available in SOP8 (Exposed Pad) and 14Lead WDFN Packages RoHS Compliant and Halogen Free Applications Distributive Power Systems Battery Charger DSL Modems PreRegulator for Linear Regulators Simplified Application Circuit V IN Chip Enable C IN BOOT C BOOT L R T R1 C C R2 C OUT 1

2 Marking Information ZQW 03 YM DNN ZSP ZSPYMDNN 03 : Product Code YMDNN : Date Code ZSP : Product Number YMDNN : Date Code Pin Configurations BOOT BOOT (TOP VIEW) WDFN14L 4x A SS PGOOD SOP8 (Exposed Pad) Functional Pin Description WDFN14L 4x3 Pin No. SOP8 (Exposed Pad) 1 1 2, 3, 4, 5 2, 3 Pin Name 6 4 BOOT PGOOD 10 SS , 13, 15 (Exposed Pad) Pin Function Power Input. supplies the power to the IC, as well as the stepdown converter switches. Drive with a 4.5V to 21V power source. Bypass to with a suitably large capacitor to eliminate noise on the input to the IC. Switch Node. is the switching node that supplies power to the output. Connect the output LC filter from to the output load. Note that a capacitor is required from to BOOT to power the high side switch. Bootstrap for High Side Gate Driver. Connect a 100nF or greater capacitor from to BOOT to power the high side switch driver. Enable or External Frequency Synchronization Input. For automatic startup, connect the pin to with a 100kΩ resistor. The switching frequency can be changed by an external clock applying to the SYNC pin. Feedback Input. senses the output voltage via an external resistive voltage divider. The feedback reference voltage is 0.808V typically. Power Good Indicator is an Open Drain Output. The power good rising/falling threshold is 90%/70% of regulation output voltage. SoftStart Control Input. Connect a capacitor from SS to to set the softstart period. Bias Supply. Decouple with 0.1μF to 0.22μF capacitor between this pin and. 8, 9 (Exposed Pad) Ground. The exposed pad must be soldered to a large PCB and connected to for maximum power dissipation. 14 A Analog Ground. Connect this pin to the system ground in PCB layout. 2

3 Function Block Diagram For WDFN14L 4x3 Package PGOOD 5k 3V Shutdown Comparator 1.2V 1µA Lockout 1.7V Comparator Regulator V C Reference V A Ramp Generator Oscillator Error Amplifier S R PWM Comparator Current Sense Amplifier V A Q Driver BOOT V C 10µA 30pF 400k SS 1pF For SOP8 (Exposed Pad) Package 1.2V Shutdown Comparator Regulator Ramp Generator Current Sense Amplifier BOOT 5k 3V 1µA 1.7V Lockout Comparator Oscillator S R PWM Comparator Q Driver Reference Error Amplifier 30pF 400k 1pF 3

4 Operation The is a constant frequency, current mode synchronous stepdown converter. In normal operation, the high side NMOSFET is turned on when the SR latch is set by the oscillator and is turned off when the current comparator resets the SR latch. While the high side N MOSFET is turned off, the low side NMOSFET is turned on to conduct the inductor current until next cycle begins. Error Amplifier The error amplifier adjusts its output voltage by comparing the feedback signal (V ) with the internal reference. When the load current increases, it causes a drop in the feedback voltage relative to the reference. The error amplifier's output voltage then rises to allow higher inductor current to match the load current. Oscillator The internal oscillator runs at fixed frequency 500kHz. In short circuit condition, the frequency is reduced to 150kHz for low power consumption. Internal Regulator The regulator provides low voltage power to supply the internal control circuits and the bootstrap power for high side gate driver. Enable The converter is turned on when the EN pin is higher than 2V. When the EN pin is lower than 0.4V, the converter will enter shutdown mode and reduce the supply current to be less than 1μA. SoftStart (SS) An internal current source charges an internal capacitor to build a softstart ramp voltage. The voltage will track the internal ramp voltage during softstart interval. The typical softstart time is 4ms. UV Comparator If the feedback voltage (V ) is lower than 0.4V, the UV Comparator will go high to turn off the high side MOSFET. The output under voltage protection is designed to operate in Hiccup mode. When the UV condition is removed, the converter will resume switching. Thermal Shutdown The over temperature protection function will shut down the switching operation when the junction temperature exceeds 150 C. Once the junction temperature cools down by approximately 30 C, the converter will automatically resume switching. 4

5 Absolute Maximum Ratings (Note 1) Supply Input Voltage, 0.3V to 26V Switch Voltage, 0.3V to (V IN 0.3V) Boot Voltage, BOOT ( 0.3V) to ( 6V) Other Pins 0.3V to 6V Power Dissipation, P T A = 25 C WDFN14L 4x3 3.33W SOP8 (Exposed Pad) 1.63W Package Thermal Resistance (Note 2) WDFN14L 4x3, θ JA 30 C/W WDFN14L 4x3, θ JC 7.5 C/W SOP8 (Exposed Pad), θ JA 61.2 C/W SOP8 (Exposed Pad), θ JC 6.5 C/W Junction Temperature 150 C Lead Temperature (Soldering, 10 sec.) 260 C Storage Temperature Range 65 C to 150 C ESD Susceptibility (Note 3) HBM (Human Body Model) 2kV Recommended Operating Conditions (Note 4) Supply Input Voltage, 4.5V to 21V Junction Temperature Range 40 C to 125 C Ambient Temperature Range 40 C to 85 C Electrical Characteristics (V IN = 12V, TA = 25 C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Current I SHDN V EN = μa Quiescent Current I Q V EN = 2V, V = 1V 0.7 ma Upper Switch On Resistance R DS(ON)1 120 mω Lower Switch On Resistance R DS(ON)2 40 mω Switch Leakage I LEAK V EN = 0V, V = 0V or 12V 0 10 μa Current Limit I LIM V BOOT V = 4.8V A Oscillator Frequency f V = 0.75V khz Short Circuit Frequency V = 0V 150 khz Maximum Duty Cycle D MAX V = 0.8V 90 % Minimum On Time t ON 100 ns Feedback Voltage V 4.5V V IN 21V V Feedback Current I na EN Threshold LogicHigh V IH Voltage LogicLow V IL 0.4 V 5

6 Parameter Symbol Test Conditions Min Typ Max Unit EN Current I EN V EN = 2V 1 V EN = 0V 0 μa SYNC Threshold LogicHigh V SYNCH 1.8 Voltage LogicLow V SYNCL 0.4 V SYNC Frequency Range f SYNC MHz SYNC Input Current I SYNC V SYNC = 6V μa Power Good Rising Threshold 90 % Power Good Falling Threshold 70 % Power Good Sink Current Capability Sink 4mA 0.4 V Power Good Leakage Current 10 na Under Voltage Lockout Threshold Under Voltage Lockout Threshold Hysteresis V UVLO V IN Rising V ΔV UVLO 400 mv Regulator 5 V Load Regulation I CC = 5mA 5 % SoftStart Period t SS C SS = 47nF 4.7 ms Thermal Shutdown Threshold T SD 150 C Thermal Shutdown Hysteresis ΔT SD 30 C Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 C on a high effective thermal conductivity fourlayer test board per JEDEC 517. θjc is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. 6

7 Typical Application Circuit For WDFN14L 4x3 Package V IN PGOOD ON/OFF C IN 22µF R3 100k C C 0.1µF 1 9 PGOOD 11 7 BOOT 6 2, 3, 4, 5 8 SS 10 C SS 47nF C BOOT 100nF R T L R1 R2 C OUT A 14 12, 13, 15 (Exposed Pad) For SOP8 (Exposed Pad) Package 1 4 V IN BOOT C IN 22µF 2, 3 Chip Enable 5 6 8, 9 (Exposed Pad) 7 C BOOT 100nF R T C C 0.1µF L R2 R1 C OUT Table 1. Recommended Components Selection (V) R1 (kω) R2 (kω) R T (kω) L (μh) C OUT (μf) x x x x x x x 2 7

8 Typical Operating Characteristics Efficiency vs. Output Current Reference Voltage vs. Input Voltage Efficiency (%) = 21V = 12V Reference Voltage (V) VOUT = 1.22V, IOUT = 0A to 4A Output Current (A) Input Voltage (V) Reference Voltage vs. Temperature Output Voltage vs. Output Current Reference Voltage (V) Output Voltage (V) = 21V = 12V VOUT = 1.22V, IOUT = 0A to 4A Temperature ( C) Output Current (A) Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature Switching Frequency (khz) Switching Frequency (khz) VOUT = 1.22V, IOUT = 1A 300 = 12V, VOUT = 1.22V, IOUT = 1A Input Voltage (V) Temperature ( C) 8

9 Current Limit vs. Input Voltage Current Limit vs. Temperature Current Limit (A) Current Limit (A) Input Voltage (V) 0 = 12V, VOUT = 1.22V Temperature ( C) Load Transient Response Load Transient Response (500mV/Div) (500mV/Div) I OUT (2A/Div) = 12V, VOUT = 1.22V, IOUT = 0A to 4A I OUT (2A/Div) = 12V, VOUT = 1.22V, IOUT = 1A to 4A Time (100μs/Div) Time (100μs/Div) Output Ripple Voltage Output Ripple Voltage (50mV/Div) (50mV/Div) V (10V/Div) V (10V/Div) I L (1A/Div) = 12V, IOUT = 1A I L (2A/Div) = 12V, IOUT = 4A Time (1μs/Div) Time (1μs/Div) 9

10 Power On from Power Off from V IN (10V/Div) V IN (10V/Div) VOUT (1V/Div) (1V/Div) V PGOOD (5V/Div) V PGOOD (5V/Div) I L (5A/Div) = 12V, VOUT = 1.22V, IOUT = 4A I L (5A/Div) = 12V, VOUT = 1.22V, IOUT = 4A Time (5ms/Div) Time (25ms/Div) Power On from EN Power Off from EN V EN (5V/Div) V EN (5V/Div) VOUT (1V/Div) (1V/Div) V PGOOD (5V/Div) V PGOOD (5V/Div) I L (5A/Div) = 12V, VOUT = 1.22V, IOUT = 4A IL (5A/Div) = 12V, VOUT = 1.22V, IOUT = 4A Time (2.5ms/Div) Time (50μs/Div) 10

11 Application Information The IC is a synchronous high voltage stepdown converter that can support the input voltage range from 4.5V to 21V and the output current can be up to 4A. Output Voltage Setting The output voltage is set by an external resistive divider according to the following equation : V R1 OUT = V 1 R2 where V is the feedback reference voltage 0.808V (typical). The resistive divider allows the pin to sense a fraction of the output voltage as shown in Figure 1. R1 R2 Figure 1. Output Voltage Setting External Bootstrap Diode Connect a 100nF low ESR ceramic capacitor between the BOOT pin and pin as shown in Figure 2. This capacitor provides the gate driver voltage for the high side MOSFET. It is recommended to add an external bootstrap diode between an external 5V and BOOT pin for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 65%.The bootstrap diode can be a low cost one such as IN4148 or BAT54. The external 5V can be a 5V fixed input from system or a 5V output of the IC. Note that the external boot voltage must be lower than 5.5V. 5V BOOT 100nF SoftStart for WDFN14L Package The ZQW (WDFN14L package) contains an external softstart clamp that gradually raises the output voltage. The softstart timing is programmed by the external capacitor between SS pin and. The chip provides an internal 10μA charge current for the external capacitor. If 47nF capacitor is used to set the softstart, the period will be 4.7ms (typ.). SoftStart for SOP8 (Exposed Pad) Package The ZSP (SOP8 (Exposed Pad) package) contains an internal softstart function to prevent large inrush current and output voltage overshoot when the converter starts up. Softstart automatically begins once the chip is enabled. During softstart, the internal softstart capacitor becomes charged and generates a linear ramping up voltage across the capacitor. This voltage clamps the voltage at the internal reference, causing the duty pulse width to increase slowly and in turn reduce the output surge current. The typical softstart time for this IC is set at 2ms. Under Voltage Lockout Threshold The IC includes an input Under Voltage Lockout Protection (UVLO). If the input voltage exceeds the UVLO rising threshold voltage (4.2V), the converter resets and prepares the PWM for operation. If the input voltage falls below the UVLO falling threshold voltage (3.8V) during normal operation, the device stops switching. The UVLO rising and falling threshold voltage includes a hysteresis to prevent noise caused reset. Chip Enable Operation The EN pin is the chip enable input. Pulling the EN pin low (<0.4V) will shutdown the device. During shutdown mode, the quiescent current drops to lower than 1μA. Driving the EN pin high (2V < EN < 5.5V) will turn on the device again. For external timing control, the EN pin can also be externally pulled high by adding a R EN resistor and C EN capacitor from the pin (see Figure 3). Figure 2. External Bootstrap Diode 11

12 EN V IN 12 Figure 3. Enable Timing Control An external MOSFET can be added to implement digital control on the EN pin, as shown in Figure 4. In this case, a 100kΩ pullup resistor, R EN, is connected between V IN pin and the EN pin. MOSFET Q1 will be under logic control to pull down the EN pin. V IN R EN C EN Figure 4. Digital Enable Control Circuit The chip starts to operate when V IN rises to 4.2V (UVLO threshold). During the V IN rising period, if an 8V output voltage is set, V IN is lower than the target value and it may cause the chip to shut down. To prevent this situation, a resistive voltage divider can be placed between the input voltage and ground and connected to the EN pin to adjust enable threshold, as shown in Figure 5. For example, the setting is 8V and V IN is from 0V to 12V, when V IN is higher than 10V, the chip is triggered to enable the converter. Assume R EN1 = 50kΩ. Then, where V IH(MIN) is the minimum threshold of enable rising (2V) and V IN_S is the target turn on input voltage (10V in this example). According to the equation, the suggested resistor R EN2 is 12.5kΩ. V IN EN R EN 100k (R x V ) EN1 IH(MIN) R EN2 = (V IN_S V IH(MIN) ) R EN1 R EN2 Q1 Figure 5. Resistor Divider for Lockout Threshold Setting EN EN EN Operating Frequency and Synchronization The internal oscillator runs at 500kHz (typ.) when the EN/ SYNC pin is at logichigh level (>2V). If the EN pin is pulled to lowlevel for 10μs above, the IC will shut down. The can be synchronized with an external clock ranging from 300kHz to 2MHz applied to the pin. The external clock duty cycle must be from 30% to 90%. 2ms 10µs VOUT CLK External CLK Figure 6. Startup Sequence Using External Sync Clock Figure 6 shows the synchronization operation in startup period. When the is triggered by an external clock, the enters softstart phase and the output voltage starts to rise. During the softstart phase region, the oscillation frequency will be proportional to the feedback voltage until it is higher than 0.7V. With higher V, the switching frequency is relatively higher. After startup period about 2ms, the IC operates with the same frequency as the external clock. Power Good Output The power good output is an opendrain output and requires a pull up resistor. When the output voltage is lower than 70% of its set voltage, PGOOD will be pulled low. It is held low until the output voltage returns to within the allowed tolerances once more. During softstart, PGOOD is actively held low and only allowed to transition high after softstart is over and the output voltage has reached 90% of its set voltage. Under Output Voltage ProtectionHiccup Mode For the IC, Hiccup Mode of Under Voltage Protection (UVP) is provided. When the voltage drops below half of the feedback reference voltage, V, the UVP function will be triggered and the IC will shut down for a period of time and then recover automatically. The Hiccup Mode of UVP can reduce input current in shortcircuit conditions.

13 Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔI L increases with higher V IN and decreases with higher inductance. V V Δ I = 1 L OUT OUT f L Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. Highest efficiency operation is achieved by reducing ripple current at low frequency, but it requires a large inductor to attain this goal. For the ripple current selection, the value of ΔI L = 0.24(I MAX ) will be a reasonable starting point. The largest ripple current occurs at the highest V IN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : VOUT VOUT L = 1 f I L(MAX) V Δ IN(MAX) The inductor's current rating (caused a 40 C temperature rising from 25 C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. Please see Table 2 for the inductor selection reference and it is highly recommended to keep inductor value as close as possible to the recommended inductor values for each as shown in Table 1. Table 2. Suggested Inductors for Typical Application Circuit Component Supplier Series Dimensions (mm) TDK VLF x 9.7 x 4.5 TDK SLF x 12.5 x 6.5 TAIYO YUDEN NR x 8 x 4 Input and Output Capacitors Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by : VOUT I RMS = IOUT(MAX) 1 VOUT This formula has a maximum at V IN = 2, where I RMS = I OUT / 2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, one 22μF low ESR ceramic capacitors are recommended. For the recommended capacitor, please refer to Table 3 for more detail. Table 3. Suggested Capacitors for C IN and C OUT Location Component Supplier Part No. Capacitance (μf) Case Size C IN MURATA GRM32ER71C226M C IN TDK C3225X5R1C226M C OUT MURATA GRM31CR60J476M C OUT TDK C3225X5R0J476M C OUT MURATA GRM32ER71C226M C OUT TDK C3225X5R1C226M The selection of C OUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, Δ, is determined by : Δ Δ VOUT IL ESR 8fC OUT 1 Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal 13

14 for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, V IN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at excessively high temperatures. When the junction temperature is higher than 150 C, the chip is shut down the switching operation. The chip is automatically reenabled when the junction temperature cools down by approximately 30 C. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) T A ) / θ JA where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125 C. The junction to ambient thermal resistance, θ JA, is layout dependent. For WDFN14L 4x3 package, the thermal resistance, θ JA, is 30 C/W on a standard JEDEC 517 fourlayer thermal test board. For SOP8 (Exposed Pad) package, the thermal resistance, θ JA, is 61.2 C/W on a standard JEDEC 517 fourlayer thermal test board. The maximum power dissipation at T A = 25 C can be calculated by the following formulas : P D(MAX) = (125 C 25 C) / (30 C/W) = 3.33W for WDFN14L 4x3 package P D(MAX) = (125 C 25 C) / (61.2 C/W) = 1.63W for SOP8 (Exposed Pad) package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curve in Figure 7 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W) FourLayer PCB 3.0 WDFN14L 4x SOP8 (Exposed Pad) Ambient Temperature ( C) Figure 7. Derating Curve of Maximum Power Dissipation Layout Considerations Follow the PCB layout guidelines for optimal performance of the IC. Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins ( and ). node is with high frequency voltage swing and should be kept at small area. Keep analog components away from the node to prevent stray capacitive noise pickup. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the IC. Connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. An example of PCB layout guide is shown in Figure 8 for reference. 14

15 Place the input and output capacitors as close to the IC as possible. C IN should be connected to inductor by wide and short trace and keep sensitive components away from this trace. L BOOT C BOOT A SS PGOOD C SS R T R2 R1 Place the feedback as close to the IC as possible. COUT Figure 8 (a). PCB Layout Guide for WDFN14L 4x3 Place the input and output capacitors as close to the IC as possible. C IN should be connected to inductor by wide and short trace and keep sensitive components away from this trace. BOOT R T R2 R1 Place the feedback as close to the IC as possible. L C BOOT C OUT Figure 8 (b). PCB Layout Guide for SOP8 (Exposed Pad) 15

16 Outline Dimension DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A A b D D E E e L WType 14L DFN 4x3 Package 16

17 A H M EXPOSED THERMAL PAD (Bottom of Package) J Y X B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Option 1 Option 2 X Y X Y Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863) Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 17