FUNCTION TVDD DVDD AVDD SVDD GND1 AK4954A. LINE- OUT Jack. HP Jack. Figure 1. AKD4954A-B Block Diagram

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1 KD4954- Evaluation boar Rev.0 for K4954 GENERL DESCRIPTION The KD4954- is an evaluation boar for the K bit CODEC with built-in PLL an MIC/HP/SPK mplifier. On-boar US port enables a GUI on Winows to control various settings. The KD4954- has the interface with KM s /D evaluation boars. Therefore, it s easy to evaluate the K4954. The KD4954- also has the igital auio interface an can achieve the interface with igital auio systems via opt-connector. Orering Guie KD Evaluation boar for K4954 (Cable for connecting with US port an control software are inclue in this package. This control software oes not operate on Winows NT.) FUNCTION Compatible with 2 types of interface - Direct interface with KM s /D converter evaluation boars - DIT/DIR with optical input/output US port for boar control TVDD DVDD VDD SVDD 3.3V 1.8V 3.3V 3.3V GND1 0V REG1 5V 3.3V REG 1.8V REG Digital MIC LIN1 RIN1 LDO (T3) Mini Jack LIN2 RIN2 K4954 PIC4550 External Clock US LIN3 RIN3 K4118 (DIT/DIR) Opt In Opt Out SPP SPN SPK LINE- OUT Jack HP Jack Figure 1. KD4954- lock Diagram * Circuit iagram an PC layout are attache at the en of this manual.

2 Operation Sequence (1) Set up the power supply lines. (1-1) In case of supplying the power from regulator. <Default> JP3 JP17 SVDD US5V 1.8V 5V 3.3V Name of Jack Color Default Setting Using REG1 re 5V for regulator input GND1 black 0V groun Table 1. Set up of power supply lines (1-2) In case of using the power supply connectors. JP3 SVDD JP17 US5V 1.8V 5V 3.3V (2) Set up the evaluation moe, jumper pins an DIP switch. (See the followings.) (3) Power on. The K4954 an K4118 must be reset after the power supplies are applie. The K4954 an K4118 shoul be reset once by bringing SW1 (PDN) L upon power-up. Click the Dummy Comman button on the control software after releasing the reset by SW1= H

3 Evaluation moe In case of using the K4118 when evaluating the K4954, auio interface format of both evices must be matche. Reter to the atasheet for auio interface format of the K4954, an Table 2 for auio interface format of the K4118. The K4118 operates at fs of 32k or more. If the fs is slower than 32k, please use other moe. In aition, MCLK of K4118 supports 256fs an 512fs. When evaluating in a conition except above, please use other moe. Refer to the atasheet for register setting of the K4954. pplicable Evaluation Moe (1) /D Evaluation using the K4118 (DIT). (1-1) Setting in External Slave Moe (2) D/ Evaluation using the K4118 (DIR). <Default> (2-1) Setting in External Slave Moe (3) Evaluation of /D or D/ using the external clock. (3-1) Setting in PLL Master Moe (3-2) Setting in PLL Slave Moe (3-3) Setting in External Slave Moe (4) Evaluation of Loop-back. (4-1) Setting in PLL Master Moe (4-2) Setting in PLL Slave Moe (4-3) Setting in External Slave Moe - 3 -

4 (1) /D Evaluation using the K4118 (DIT) (1-1) Setting in External Slave Moe X1 (X tal: M) an PORT2 (DIT) are use. Do not connect anything to PORT1 (DIR). Registers of the K4954 shoul be set to EXT Slave Moe. MCKI, ICK an LRCK are supplie from the K4118, an SDTO of the K4954 is output to the K4118. The jumper pins shoul be set as follows. JP11 MCKI JP14 ICK JP12 LRCK JP15 SDTO EXT DIR EXT DIR EXT DIR (2) Evaluation of D/ using DIR of K4118. <Default> (2-1) Setting in External Slave Moe PORT1 (DIR) is use. Do not connect anything to PORT2 (DIT). Registers of the K4954 shoul be set to EXT Slave Moe. The jumper pins shoul be set as follows. JP11 MCKI JP14 ICK JP12 LRCK JP13 SDTI JP10 SDTI-SEL EXT DIR EXT DIR EXT DIR EXT DIR DC DIR - 4 -

5 (3) /D or D/ Evaluation using the external clock. External clocks are use. Do not connect anything to PORT1 (DIR) an PORT2 (DIT). (3-1) Setting in PLL Master Moe The master clock is input from the MCKI pin of JP11. n internal PLL circuit generates ICK an LRCK. Registers of the K4954 shoul be set to PLL Master Moe. ICK, LRCK SDTI an SDTO are input into an output from JP14, JP12, JP13 an JP15. K M, 12M, M 13.5M, 24M, 27M DSP or P MCKI ICK LRCK 32fs, 64fs 1fs CLK LRCK SDTO SDTI SDTI SDTO Figure 2. PLL Master Moe

6 (3-2) Setting in PLL Slave Moe reference clock of PLL is selecte among the input clocks that are supplie to the ICK pin. The require clock to operate the K4954 is generate by an internal PLL circuit. Registers of the K4954 shoul be set to PLL Slave Moe (Reference Clock = ICK). ICK, LRCK SDTI an SDTO are input into an output from JP14, JP12, JP13 an JP15. K4954 DSP or P MCKI ICK LRCK 32fs, 64fs 1fs CLK LRCK SDTO SDTI SDTI SDTO Figure 3. PLL Slave Moe 2(PLL Reference Clock: ICK pin) The jumper pins shoul be set as follows. JP11 MCKI EXT DIR - 6 -

7 (3-3) Setting in External Slave Moe Registers of the K4954 shoul be set to EXT Slave Moe. MCLK, ICK, LRCK SDTI an SDTO are input into an output from JP11, JP14, JP12, JP13 an JP15. K4954 MCKI ICK LRCK 256fs,384fs 512fs or 1024fs 32fs 1fs MCLK CLK LRCK DSP or P SDTO SDTI SDTI SDTO Figure 4. EXT Slave Moe (4) Evaluation in Loop-back Moe. (4-1) Setting in PLL Master Moe Do not connect anything to PORT1 (DIR), PORT2 (DIT). Registers of the K4954 shoul be set to PLL Master Moe. (4-1-1) In case of supplying MCLK to JP11 The jumper pins shoul be set as follows. JP15 SDTO JP13 SDTI JP10 SDTI-SEL EXT DIR DC DIR - 7 -

8 (4-2) Setting in PLL Slave Moe Registers of the K4954 shoul be set to PLL Slave Moe (Reference Clock: ICK). Do not connect anything to PORT1 (DIR) an PORT2 (DIT). (4-2-1) In case of supplying ICK an LRCK from the external clock The jumper pins shoul be set as follows. JP11 MCKI JP15 SDTO JP13 SDTI JP10 SDTI-SEL EXT DIR EXT DIR DC DIR (4-3) Setting in External Slave Moe Registers of the K4954 shoul be set to EXT Slave Moe. Do not connect anything to PORT1 (DIR), PORT2 (DIT). (4-3-1) In case of using clocks from K4118 Use X1 ( M). The jumper pins shoul be set as follows. JP11 MCKI JP14 ICK JP12 LRCK JP15 SDTO JP13 SDTI JP10 SDTI-SEL EXT DIR EXT DIR EXT DIR EXT DIR DC DIR - 8 -

9 DIP Switch Setting [S1] (SW DIP-4): Moe setting of the K4118. No. Name ON ( H ) OFF ( L ) Default 1 OCKS1 K4118 Master Clock Setting : See Table 4 L 2 DIF0 L K4118 uio Format Setting 3 DIF1 L See Table 3 4 DIF2 H Table 2. Moe Setting of the K4118 Moe DIF2 DIF1 DIF0 DUX SDTO LRCK ICK I/O I/O bit, Left justifie 16bit, Right justifie H/L O 64fs O bit, Left justifie 18bit, Right justifie H/L O 64fs O bit, Left justifie 20bit, Right justifie H/L O 64fs O bit, Left justifie 24bit, Right justifie H/L O 64fs O bit, Left justifie 24bit, Left justifie H/L O 64fs O Default bit, I 2 S 24bit, I 2 S L/H O 64fs O bit, Left justifie 24bit, Left justifie H/L I fs I bit, I 2 S 24bit, I 2 S L/H I fs I Table 3. K4118 uio Interface Format Setting Toggle SW Function *Upper-sie is H an lower-sie is L. OCKS1 MCKO1 X tal 0 256fs 256fs Default 1 512fs 512fs Table 4. K4118 Master Clock Setting [SW1] (PDN): Power owns K4954 an K4118. Keep H uring normal operation. Control Port It is possible to control KD4954- via general US port. Connect cable with the US connection(port3) on the boar an PC

10 nalog Input/Output Circuits (1) Input Circuits C19 1n C18 1u + RIN3 J1 MIC-IN VSS1 JP2 RIN-SEL LIN3 LIN2 LIN1 JP1 LIN-SEL RIN3 RIN2 RIN1 C17 1n VSS1 VSS1 + C16 1u JP8 MP-LIN2 R6 2.2k MPWR2 MPWR1 JP7 MP-RIN1 LIN3 JP9 MP-RIN2 R7 2.2k C15 1n C13 1n VSS1 VSS1 C14 1u C12 1u RIN2 LIN2 JP6 MP-LIN1 R4 2.2k R5 2.2k C11 1n C9 1n VSS1 C10 1u C8 1u JP5 DMCK JP4 DMDT RIN1 LIN1 VSS1 Figure 5. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 Input Circuits (1-1) LIN1/RIN1Input Circuit <Default> LIN1 an RIN1are input to J1. When the Mic Power is not use, JP6 an JP7 shoul be set to open. JP1 LIN3 LIN2 LIN1 LIN-SEL JP2 RIN3 RIN2 RIN1 RIN-SEL JP4 JP5 JP6 JP7 DMDT DMCK MP-LIN1 MP-RIN1-10 -

11 (1-2) LIN2/RIN2 Input Circuit <Default> LIN2 an RIN2 are input to J2 an J3. When the Mic Power is not use, JP8 an JP9 shoul be set to open. JP1 JP2 JP8 JP9 LIN3 RIN3 LIN2 RIN2 MP-LIN2 MP-RIN2 LIN1 LIN-SEL RIN1 RIN-SEL (1-3) LIN3/RIN3 Input Circuit LIN3 an RIN3 are input to J2 an J3. JP1 LIN3 LIN2 LIN1 LIN-SEL JP2 RIN3 RIN2 RIN1 RIN-SEL (1-4) Digital Mic Input Circuit DMCK is output from JP5 an DMDT is input to JP4. JP4 JP5 DMDT DMCK

12 (2) Output Circuits (2-1) HPL/HPR Output Circuit HPR HPL J2 HP-OUT C u R18 33 C u R17 33 VSS1 HPL an HPR are output from J2 Figure 6. HPL/HPR Output Circuit (2-2) SPP/SPN Output Circuit SPP SPN 1 1 TP1 SPP TP2 SPN SPP an SPN are output from TP1 an TP2. Figure 7. SPP/SPN Output Circuit (2-3) Stereo Line Output Circuit ROUT LOUT C25 C u 1u J3 LINE-OUT R15 22k R16 22k LOUT an ROUT are output from J3. VSS3.Figure 8. LOUT/ROUT Output Circuit * KM assumes no responsibility for the trouble when using the above circuit examples

13 K4954 Control Software Manual Evaluation oar an Control Software Settings 1. Set up the evaluation boar as neee, accoring to the previous terms. 2. Connect cable with the US connection on the boar an PC. 3. The US I/F boar is recognize as HID (Human Interface Device) on PC. It is not necessary to install a new river. 4. Start up the control program.(note 1) Note 1. fter power up the evaluation boar, put SW1 to L to power own the K4954 an the K4118, an return them to H to release the power-own state. Then, an initialization must be execute by pressing the Dummy Comman button. 5. egin evaluation by following the proceure below. Figure 9. Winow of Control Soft

14 Operation Overview Function, register map an testing tool are controlle by this control software. These controls may be selecte by the upper tabs. Frequently use buttons, such as the register initializing button Write Default, are locate outsie of the switching tab winow. Refer to the Dialog oxes section for etails of each ialog box setting. 1. [Port Reset]: Click this button after the control soft starts up. 2. [Write Default]: Initializes Registers When the evice is reset by a harware reset, use this button to initialize the registers. 3. [ll Write]: Executes write comman for all registers isplaye. 4. [ll Rea]: Executes rea comman for all registers isplaye. 5. [Save]: Saves current register settings to a file. 6. [Loa]: Executes ata write from a save file. 7. [ll Req Write]: Opens ll Req Write ialog box. 8. [Data R/W]: Opens Data R/W ialog box 9. [Sequence]: Opens Sequence ialog box. 10. [Sequence (File)]: Opens Sequence(File) ialog box. 11. [Rea]: Reas current register settings an isplays on to the register area (on the right of the main winow). This is ifferent from [ll Rea] button as it oes not reflect to the register map. It only isplays register values in hexaecimal numbers. 12. [Dummy Comman]: The ummy comman is written (Note 2). Note 2. fter power up the evaluation boar, put SW1 to L to power own the K4954 an the K4118, an return them to H to release the power-own state. Then, an initialization must be execute by pressing the Dummy Comman button

Tab Functions (Note 3) 1. [Function]: Function control The ialog box setting is open when click the each button Each operation is execute by [Function] buttons on the left sie of the screen.

15 Tab Functions (Note 3) 1. [Function]: Function control The ialog box setting is open when click the each button Each operation is execute by [Function] buttons on the left sie of the screen. (Refer to the Dialog ox for etails of each ialog box setting.) Note 3. fter power up the evaluation boar, put SW1 to L to power own the K4954 an the K4118, an return them to H to release the power-own state. Then, an initialization must be execute by pressing the Dummy Comman button. Figure 10. [Function] Winow [Power Management Setting] [uio Moe Setting] [System Clock uio I/F] [LC Setting] [Volume Setting] [eep Setting] [Digital Filter] [DRC Setting] : Open [Power Management Setting] ialog. : Open [uio Moe Setting] ialog. : Open [System Clock uio I/F] ialog. : Open [LC Setting] ialog. : Open [Volume Setting] ialog. : Open [eep Setting] ialog. : Open [Filter Setting] ialog. : Open [DRC Function] ialog

16 2. [REG]: Register Map This tab is for a register write an rea. Each bit on the register map is a push-button switch. utton Down inicates H or 1 an the bit name is shown in re (when rea-only, the name is shown in ark re). utton Up inicates L or 0 an the bit name is shown in blue (when rea-only, the name is shown in gray). Graye-out registers are Rea-only registers. They cannot be controlle. The registers which are not efine on the atasheet are inicate as ---. Figure 11. [REG] Winow

2-1. [Write]: Data Write Dialog Select the [Write] button locate on the right of the each corresponing aress when changing tow or more bits on the same aress simultaneously.

17 2-1. [Write]: Data Write Dialog Select the [Write] button locate on the right of the each corresponing aress when changing tow or more bits on the same aress simultaneously. Click the [Write] button for the register pop-up ialog box shown below. When the checkbox next to the register name is checke, the ata will become 1. When the checkbox is not checke, the ata will become 0. Click [OK] to write setting values to the registers, or click [Cancel] to cancel this setting. Figure 12. [Register Set] Winow 2-2. [Rea]: Data Rea Click the [Rea] button locate on the right of the each corresponing aress to execute a register rea. The current register value will be isplaye in the register winow as well as in the upper right han DEUG winow. utton Down inicates 1 an the bit name is shown in re (when rea-only, the name is shown in ark re). utton Up inicates 0 an the bit name is shown in blue (when rea-only, the name is shown in gray). Please be aware that button statuses will be change by a Rea comman

18 Dialog ox 1. [ll Req Write]: ll Reg Write ialog box Click the [ll Reg Write] button in the main winow to open register setting file winow shown below. Register setting files save by the [SVE] button may be applie. Figure 13. [ll Reg Write] Winow [Open (left)] : Selects a register setting file (*.akr). [Write] : Executes register write with selecte setting file. [Write ll] : Executes register write with all selecte setting files. Selecte files are execute in escening orer. [Help] : Opens a help winow. [Save] : Saves a register setting file assignment. File name is *.mar. [Open (right)]: Opens a save register setting file assignment *. mar. [Close] : Closes the ialog box an finish process. ~ Operating Suggestions ~ 1. Files save by [Save] button an opene by [Open] button on the right of the ialog *.mar shoul be store in the same foler. 2. When register settings are change by [Save] button in the main winow, re-rea the file to reflect new register settings

19 2. [Data R/W]: Data R/W Dialog ox Click the [Data R/W] button in the main winow for ata rea/write ialog box. Data is written to the specifie aress. Figure 14. [Data R/W] Winow [ress] ox : Input ata write aress in hexaecimal numbers. [Data] ox : Input write ata in hexaecimal numbers. [Mask] ox : Input masks ata in hexaecimal numbers. This value NDe with the write ata becomes the input ata. [Write] : Writes the ata generate from Data an Mask value is written to the aress specifie in ress box (Note 4). [Rea] : Reas ata from the aress specifie in ress box (Note 4). The result will be shown in the Rea Data ox in hexaecimal numbers. [Close] : Closes the ialog box an finishes process. Data write will not be execute unless the [Write] button is clicke. Note 4. The register map will be upate after executing the [Write] or [Rea] comman

3. [Sequence]: Sequence Dialog ox Click the [Sequence] button to open register sequence setting ialog box. Register sequence may be set in this ialog box. Figure 15.

20 3. [Sequence]: Sequence Dialog ox Click the [Sequence] button to open register sequence setting ialog box. Register sequence may be set in this ialog box. Figure 15. [Sequence] Winow ~ Sequence Setting ~ Set register sequence accoring to the following process bellow. 1. Select a comman Use [Select] pull-own box to choose commans. Corresponing boxes will be vali. < Select Pull-own menu > No_use : Not using this aress Register : Register write Reg(Mask) : Register write (Maske) Interval : Takes an interval Stop : Pauses the sequence En : Ens the sequence

21 2. Input sequence [ress] : Data aress [Data] : Write ata [Mask] : Mask The value in the [Data] box is NDe with the value in the [Mask] box. This ata becomes the actual input ata. When Mask = 0x00, current setting is hol. When Mask = 0xFF, the 8bit ata which is set in the [Data] box is written. When Mask =0x0F, lower 4bit ata which is set in the [Data] box is written. Upper 4bit is hol to current setting. [Interval] : Interval time Vali boxes for each process comman are shown bellow. No_use : None Register : [ress], [Data], [Interval] Reg(Mask) : [ress], [Data], [Mask], [Interval] Interval : [Interval] Stop : None En : None ~ Control uttons~ Functions of Control uttons are shown bellow. [Start] utton : Executes the sequence [Help] utton: Opens a help winow [Save] utton : Saves sequence settings as a file. The file name is *.aks. [Open] utton: Opens a sequence setting file *.aks. [Close] utton: Closes the ialog box an finishes the process. ~ Stop of the sequence~ When Stop is selecte in the sequence, the process is pause. It starts again when the [Start] button is clicke Restart step number is shown in the Start Step box. When executing the process until the en of sequence, the Start Step value will return to 1. The sequence can be starte from any step by writing a step number to the Start Step box. Write 1 to the Start Step box an click [Start] button, when restarting the process from the beginning

22 4. [Sequence(File)]: Sequence Setting File Dialog ox Click the [Sequence(File)] button to open sequence setting file ialog box shown below. Files save in the Sequence setting ialog can be applie in this ialog. Figure 16. [Sequence(File)] Winow [Open (left)] [Start] [Start ll] [Help] [Save] [Open(right)] [Close] : Select a sequence setting file (*.aks). : Executes the sequence by the setting of selecte file. : Executing all sequence settings. Selecte files are execute in escening orer. : Opens a help winow. : Saves a sequence setting file assignment. File name is *.mas. : Select a save sequence setting file assignment *. mas. : Closes the ialog box an finishes the process. ~ Operating Suggestions ~ 1. Files save by the [Save] button an opene by the [Open] button on the right of the ialog *.mas shoul be store in the same foler. 2. When Stop is selecte in the sequence, the process will be pause an the message box shown below pops up. Click OK to continue the process. Figure 17. Winow of [Sequence Pause]

[uio Moe Setting]: uio Moe Setting Dialog ox Click the [uio Moe Setting] button in the function tab to open the auio moe setting ialog box

23 5. [Power Management Setting]: Power Management Setting Dialog ox Click [Power Management Setting] button in the function tab to open the power management setting ialog box shown in Figure 18. Refer to the atasheet for register settings of the K4954. Figure 18. [Power Management Setting] Winow 6. [uio Moe Setting]: uio Moe Setting Dialog ox Click the [uio Moe Setting] button in the function tab to open the auio moe setting ialog box shown in Figure 19. Refer to the atasheet for register settings of the K4954. Figure 19. [uio Moe Setting] Winow

24 7. [System Clock uio I/F]: System Clock uio I/F Dialog ox Click the [System Clock uio I/F] button in the function tab to open the System Clock uio I/F ialog box shown in Figure 20. Refer to the atasheet for register settings of the K4954. Figure 20. [System Clock uio I/F] Winow

[LC Setting] Winow Volume Control by Slier Menu The volume can also be change by writing a value in a ialog box.

25 8. [LC Setting]: LC Setting Dialog ox Click the [LC Setting] button in the function tab to open the LC setting ialog box shown in Figure 21. Refer to the atasheet for register settings of the K4954. Figure 21. [LC Setting] Winow Volume Control by Slier Menu The volume can also be change by writing a value in a ialog box. The slie bar is move to the value that is written in the ialog box. Use the mouse or arrow keys on the keyboar for fine ajustments. Slie bar is move to the selecte value. The configurable value is automatically selecte. Figure 22. Volume Slier

26 9. [Volume Setting]: Volume Setting Dialog ox Click the [Volume Setting] button in the function tab to open the volume setting ialog box shown in Figure 23. Refer to the atasheet for register settings of the K4954. Figure 23. [Volume Setting] Winow

27 10. [EEP Setting]: EEP Setting Dialog ox Click the [EEP Setting] button in the function tab to open is the eep setting ialog box shown in Figure 24. Refer to the atasheet for register settings of the K4954. Figure 24. [EEP Setting] Winow

11. [Digital Filter]: Filter Setting Dialog ox Click the [Digital Filter] button in the function tab to open the filter setting ialog box shown in Figure 25.

28 11. [Digital Filter]: Filter Setting Dialog ox Click the [Digital Filter] button in the function tab to open the filter setting ialog box shown in Figure 25. Refer to the atasheet for register settings of the K4954. Figure 25. [Filter Setting] Winow [Register Setting] : Opens Register Setting for Filter ialog box. [F Response] : Opens the filter characteristic ialog. Executes all filter calculation, but filter coefficients are not written. [Write] : Executes all filter calculation, an filter coefficients are written. [Close] : Closes the ialog box an ens process

29 11-1. Parameter Setting (1) Please set a parameter of each Filter. Parameter Function Setting Range Sampling Rate Sampling frequency (fs) 7350 fs HPF Cut Off Frequency High pass filter cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) LPF Cut Off Frequency Low pass filter cut off frequency fs/20 Cut Off Frequency (0.497 * fs) FIL3 Cut Off Frequency FIL3 cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) Filter type The selection of filter type LPF or HPF Gain Gain -10 Gain < 0 EQ0 Pole Frequency EQ0 Pole Frequency fs/10000 Cut Off Frequency (0.497 * fs) Zero-point Frequency EQ0 Zero-point Frequency fs/10000 Cut Off Frequency (0.497 * fs) Gain Gain -20 Gain < +12 Gain2 Gain2 0 / +12 / an Equalizer EQ1-5 Center Frequency EQ1-5 Center Frequency 0 Center Frequency < (0.497 * fs) EQ1-5 an With EQ1-5 an With (Note 5) 1 an With < (0.497 * fs) EQ1-5 Gain EQ1-5 Gain (Note 6) -1 Gain < 3 Table 5. Parameter Setting of [Filter Setting] Note 5. gain ifference is a banwith of 3 from center frequency. Note 6. When a gain is -1, EQ becomes a notch filter. (2) LPF Enable, HPF Enable, HPFD Enable, FIL3 Enable, EQ0 Enable, EQ1, EQ2, EQ3, EQ4, EQ5 Please set ON/OFF of Filter by a check box. When the check box next to the filter name is checke, the filter will become ON. When Notch Filter uto Correction is checke, automatic correction of the center frequency of the notch filter is performe. Figure 26. Filter ON/OFF Setting Check ox

11-2. [Register Setting]: Register Setting for Filter Dialog ox Click the [Register Setting] button in the filter setting winow to open the register setting ialog box shown below.

30 11-2. [Register Setting]: Register Setting for Filter Dialog ox Click the [Register Setting] button in the filter setting winow to open the register setting ialog box shown below. When a value out of a setting range is set, error message is isplaye, an a calculation of register setting is not carrie out. Figure 27. [Register Setting for Filter] Winow Followings are the cases when register set values are upate. (1) When [Register Setting] button is pushe. (2) When [Frequency Response] button is pushe. (3) When [UpDate] button on a frequency characteristic inication winow is pushe. (4) When Notch Filter uto Correction is ON/OFF

31 11-3. [F Response]: Filter Plot Dialog ox Click the [F Response] button in the filter setting winow to open the filter plot ialog box shown below. Change Frequency Range, an inication of a frequency characteristic is upate when push a [UpDate] button. Figure 28. [F Response] Winow [Frequency Range] [Upate] [Gain/Phase] [Log View] [Close] : The with of the frequency isplay is specifie. : Reraws the filter characteristics. : Gain/Phase isplay Switch. : Linear/Log isplay Switch. : Closes the ialog box an ens process. ~ justment of vertical range ~ [Y-axis Ref] [Vertical slier] [Horizontal slier] : Set the center value of Y-axis. : Moves center reference of the Y-axis. : just scale of the X-axis. (Left: shrinking, Right: expaning)

11-4. 5-anEQ operation in Filter Plot screen When EQ(1~5) is turne on, a green number is isplaye on the Filter Plot ialog box.

The center frequency an the gain setting are change by left click ragging. The setting of the banwith is change by right click ragging.

32 anEQ operation in Filter Plot screen When EQ(1~5) is turne on, a green number is isplaye on the Filter Plot ialog box. This number shows the setting of the center frequency an the gain of each EQ. The isplaye number can be move by ragging, an filter characteristics are set on this screen. The center frequency an the gain setting are change by left click ragging. The setting of the banwith is change by right click ragging. fter ragging the number, the value of the center frequency an the gain are upate. Select the number, left click an rag to set the characteristics. Figure 29. Filter Setting (Left-clicking operation) The banwith is set by right click ragging. Figure 30. Filter Setting (Right-clicking operation)

33 11-5. Simulation of Fil3 Filter Setting of Stereo-MIC [L-ch Level]/[R-ch Level] : Input the level of the MIC input. [Distance] : Set the istance between the soun source an the MIC. [ngle] : Set the angle between the soun source an the MIC. Figure 31. Simulation of Fil3 Filter

34 11-6. Notch uto Correct Function If the gain of 5-an EQ is set to -1, Equalizer becomes a notch filter. If the center frequency of two or more notch filters are ajacent, each center frequency will shift slightly (Figure 32). Check the Notch uto Correct check box to correct notch filter center frequency automatically (Figure 33). The automatic correction of center frequency is only effective for the equalizer that the gain is set to -1 (Note 7). Note 7. There is a possibility that the automatic correction is not applie appropriately if the with of the center frequency is smaller than that of the banwith setting. Setting of center frequency: 4400, 5000, 5400 / anwith : 200(EQ2~4) Figure 32. Notch uto Correct function is OFF Setting of center frequency: 4400, 5000, 5400 / anwith : 200(EQ2~4) Figure 33. Notch uto Correct function is ON

35 12. [DRC Setting]: [DRC Function] Dialog ox Click the [DRC Setting] button in the function tab to open the DRC function ialog box shown in Figure 34. Refer to the atasheet for register settings of the K4954. Figure 34. [DRC Setting] Winow [Write] : Executes all filter calculations, an coefficients are written. [F Response] : Opens the filter characteristic ialog. Executes all filter calculations, but filter coefficients are not written. [DRC Curve] : Opens the DRC Curve ialog. [Close] : Closes the ialog box an ens process

36 12-1. Parameter Setting (1) Set a parameter of each Filter an Gain. Parameter Function Setting Range Sampling Rate Sampling frequency (fs) 7350 fs Noise Suppression LPF Low pass filter cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) HPF High pass filter cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) Dynamic Volume Control Low Frequency Range LPF Low pass filter cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) Mile Frequency Range LPF Low pass filter cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) HPF High pass filter cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) High Frequency Range HPF High pass filter cut off frequency fs/10000 Cut Off Frequency (0.497 * fs) Table 6. Parameter Setting of [DRC Function] (2) When the checkbox next to each filter name is checke, the filter will be enable. When DVLC Enable button is checke, the filters of Low/Mile/High Range are enable accoring to setting of pull-own menu. When fc uto checkbox is checke, the frequency responses of low frequency an high frequency ranges become flat automatically. Figure 35. Filter ON/OFF setting button

37 12-2. Frequency Response Click the [F Response] button in the DRC setting winow to isplay frequency characteristics. Figure 36. frequency characteristic inication result [Frequency Range] [Upate] [Gain/Phase] [Close] : The with of the frequency isplay is specifie. : Reraws the filter characteristics. : Gain/Phase isplay Switch. : Closes the ialog box an ens process

38 12-3. Filter Setting The filter setting can be execute by checking the NSLPF, NSHPF or DVLC Enable checkbox in the [DRC function] ialog box. Select a filter name by left clicking an rag to ajust the filter characteristics. fter changing the characteristics, the value of the cut-off frequency is upate. Figure 37. Filter Setting (Left-clicking operation) fter changing the filter moe by pull-own box, the filter characteristics on the graph is upate. Figure 38. Filter Setting (Filter Selecting)

39 12-4. Noise Suppression Click the [DRC curve] button in the DRC setting winow to open the DRC curve winow. Click the NS raio button to ajust the noise suppression setting. Noise Suppression Threshol Low Level an Reference Value can be ajuste by left-click ragging. Noise Suppression Threshol Low Level Reference Value Register map fter Threshol Low Level point is move, the setting value is reflecte on the register map. The Threshol Low Level point is ajuste, by left- click ragging Figure 39. Noise Suppression Setting

Select the frequency range for DVLV curve Re: LOW lue: MIDDLE Green: HIGH DVLC volume control point in Low range レジスタマップ fter

40 12-5. Dynamic Volume Control Dynamic Volume is isplaye when LOW, MIDDLE or HIGH raio button in DVLC is checke. Then, a register set point is also upate. Dynamic Volume Control Points can be ajuste by left-click ragging. Select the frequency range for DVLV curve Re: LOW lue: MIDDLE Green: HIGH DVLC volume control point in Low range レジスタマップ fter volume control point is move, the setting value is reflecte on the register map. The volume control point is ajuste by left-click ragging. Figure 40. DVLC Curve Setting

41 12-6. Dynamic Range Control Dynamic Range Control is isplaye when DRC raio button is checke. Then, a register set point is also upate. Dynamic Range Compression Level can be ajuste by left-click ragging. Register map fter DRC Compression Level is move, the setting value is reflecte on the register map. The DRC Compression Level is ajuste by left- click ragging. Figure 41. Dynamic Range Control Setting

42 MESUREMENT RESULTS [Measurement conition] Measurement unit : uio Precision, System two Cascae MCKI : 256fs ( M, M) ICK : 64fs fs : 44.1k, 96k it : 24bit Measurement Moe : EXT Slave Moe Power Supply : VDD = SVDD = TVDD = 3.3V, DVDD = 1.8V Input Frequency : 1k Measurement Frequency : 20 ~ 20k (fs=44.1k), 20 ~ 40k (fs=96k) Temperature : Room [Measurement Results] 1. DC Result Lch Rch DC: LIN1/RIN1 DC IVOL, IVOL=0, LC=OFF MGIN = +20 S/(N+D) (-1FS) Unit fs=44.1k, W=20k fs=96k, W=40k DR (FS, -Weighte) S/N (-weighte) MGIN = 0 S/(N+D) (-1FS) fs=44.1k, W=20k fs=96k, W=40k DR (FS, -Weighte) S/N (-weighte) DC Result Lch Rch Unit Heaphone-mp: DC HPL/HPR, IVOL=DVOL=0, RL=16Ω S/(N+D) fs=44.1k, W=20k fs=96k, W=40k S/N (-weighte) Speaker-mp: DC SPP/SPN, IVOL=DVOL=0, SPKG=+6.26, R L =8 fs=44.1k, W=20k S/(N+D) (-0.5FS) 76.1 Output Noise Level (-Weighte) V Stereo Line Output: DC LOUT/ROUT, IVOL=DVOL=0, RL=20kΩ fs=44.1k, W=20k S/(N+D) S/N (-weighte)

43 [Plot] 1. DC (LIN1/RIN1 DC) (+20) [fs=44.1k] K4954 FFT [LIN3/RIN3] fs=44.1k, fin=1k, -1FS Input, MGIN="+20" F S k 2k 5k 10k 20k Figure 42. FFT (Input level= -1FS) K4954 FFT [LIN3/RIN3] fs=44.1k, fin=1k, FS Input, MGIN="+20" F S k 2k 5k 10k 20k Figure 43. FFT (Input level= FS)

44 K4954 FFT [LIN3/RIN3] fs=44.1k, No Signal, MGIN="+20" F S k 2k 5k 10k 20k Figure 44. FFT (No signal) -70 K4954 S/(N+D) vs. Input Level [LIN3/RIN3] fs=44.1k, fin=1k, MGIN="+20" -75 F S r Figure 45. THD+N vs. Input Level

45 F S K4954 S/(N+D) vs. Input Frequency [LIN3/RIN3] fs=44.1k, -1FS Input, MGIN="+20" k 2k 5k 10k 20k Figure 37. THD+N vs. Input Frequency -20 T T TT T K4954 Linearity [LIN3/RIN3] fs=44.1k, fin=1k, MGIN="+20" -40 F S r Figure 47. Linearity

46 K4954 Frequency Responce [LIN3/RIN3] fs=44.1k, -1FS Input, MGIN="+20" -0.5 F S k 4k 6k 8k 10k 12k 14k 16k 18k 20k Figure 48. Frequency Response -70 T T K4954 Crosstalk [LIN3/RIN3] fs=44.1k, -1FS Input, MGIN="+20" k 2k 5k 10k 20k Figure 49. Crosstalk

47 2. DC (LIN1/RIN1 DC) (+20) [fs=96k] K4954 FFT [LIN3/RIN3] fs=96k, fin=1k, -1FS Input, MGIN="+20" F S k 2k 5k 10k 20k 40k Figure 50. FFT (Input level= -1FS) K4954 FFT [LIN3/RIN3] fs=96k, fin=1k, FS Input, MGIN="+20" F S k 2k 5k 10k 20k 40k Figure 51. FFT (Input level= FS)

48 K4954 FFT [LIN3/RIN3] fs=96k, No Signal, MGIN="+20" F S k 2k 5k 10k 20k 40k Figure 52. FFT (No signal) -70 K4954 S/(N+D) vs. Input Level [LIN3/RIN3] fs=96k, fin=1k, MGIN="+20" -75 F S r Figure 53. THD+N vs. Input Level

49 -70 K4954 S/(N+D) vs. Input Frequency [LIN3/RIN3] fs=96k, -1FS Input, MGIN="+20" -75 F S k 2k 5k 10k 20k 40k Figure 54. THD+N vs. Input Frequency -20 T T TT T K4954 Linearity [LIN3/RIN3] fs=96k, fin=1k, MGIN="+20" -40 F S r Figure 55. Linearity

50 K4954 Frequency Response [LIN3/RIN3] fs=96k, -1FS Input, MGIN="+20" F S k 10k 15k 20k 25k 30k 35k 40k 45k Figure 56. Frequency Response K4954 Crosstalk [LIN3/RIN3] fs=96k, -1FS Input, MGIN="+20" T k 2k 5k 10k 20k 40k Figure 57. Crosstalk

51 3. DC (DC HPL/HPR) [fs=44.1k] K4954 FFT [HPL/HPR] fs=44.1k, fin=1k, 0FS Input r k 2k 5k 10k 20k Figure 58. FFT (Input level= 0FS) K4954 FFT [HPL/HPR] fs=44.1k, fin=1k, FS Input r k 2k 5k 10k 20k Figure 59. FFT (Input level= FS)

52 K4954 FFT [HPL/HPR] fs=44.1k, No Signal r k 2k 5k 10k 20k Figure 60. FFT (No signal) K4954 Out of an Noise [HPL/HPR] fs=44.1k, No Signal r k 2k 5k 10k 20k 50k 100k Figure 61. FFT (Out-of-ban Noise)

53 K4954 S/(N+D) vs. Input Level[HPL/HPR] fs=44.1k, fin=1k r FS Figure 62. THD+N vs. Input Level -40 K4954 S/(N+D) vs. Input Frequency [HPL/HPR] fs=44.1k, 0FS Input -50 r k 2k 5k 10k 20k Figure 63. THD+N vs. Input Frequency

54 K4954 Linearity[HPL/HPR] fs=44.1k, fin=1k r FS Figure 64. Linearity.5.4 K4954 Frequency Responce[HPL/HPR] fs=44.1k, 0FS Input.3 r k 4k 6k 8k 10k 12k 14k 16k 18k 20k Figure 65. Frequency Response

55 K4954 Crosstalk [HPL/HPR] fs=44.1k, 0FS Input k 2k 5k 10k 20k Figure 66. Crosstalk

56 4. DC (DC HPL/HPR) [fs=96k] K4954 FFT [HPL/HPR] fs=96k, fin=1k, 0FS Input r k 2k 5k 10k 20k 40k Figure 67. FFT (Input level= 0FS) K4954 FFT [HPL/HPR] fs=96k, fin=1k, FS Input r k 2k 5k 10k 20k 40k Figure 68. FFT (Input level= FS)

57 K4954 FFT [HPL/HPR] fs=96k, No Signal r k 2k 5k 10k 20k 40k Figure 69. FFT (No signal) K4954 Out of an Noise [HPL/HPR] fs=96k, No Signal r k 2k 5k 10k 20k 50k 100k Figure 70. FFT (Out-of-ban Noise)

58 -65 K4954 S/(N+D) vs. Input Level [HPL/HPR] fs=96k, fin=1k -70 r FS Figure 71. THD+N vs. Input Level -40 K4954 S/(N+D) vs. Input Frequency [HPL/HPR] fs=96k, 0FS Input -50 r k 2k 5k 10k 20k 40k Figure 72. THD+N vs. Input Frequency

59 K4954 Linearity[HPL/HPR] fs=96k, fin=1k r FS Figure 73. Linearity K4954 Frequency Response[HPL/HPR] fs=96k, 0FS Input r k 10k 15k 20k 25k 30k 35k 40k 45k Figure 74. Frequency Response

60 -70 K4954 Crosstalk [HPL/HPR] fs=96k, 0FS Input k 2k 5k 10k 20k 40k Figure 75. Crosstalk

61 5. DC (DC SPK) [fs=44.1k] K4954 FFT [SPP/SPN] fs=44.1k, fin=1k, -0.5FS Input, SLG1-0 bits="01" r k 2k 5k 10k 20k Figure 76. FFT (Input level= -0.5FS) K4954 FFT [SPP/SPN] fs=44.1k, fin=1k, FS Input, SLG1-0 bits="01" r k 2k 5k 10k 20k Figure 77. FFT (Input level= FS)

62 K4954 FFT [SPP/SPN] fs=44.1k, No Signal, SLG1-0 bits="01" r k 2k 5k 10k 20k Figure 78. FFT (No Signal) K4954 Out of an Noise [SPP/SPN] fs=44.1kk, No Signal, SLG1-0 bits="01" r k 2k 5k 10k 20k 50k 100k Figure 79. FFT (No Signal)

63 K4954 S/(N+D) vs. Input Frequency[SPP/SPN] fs=44.1k, -0.5FS Input, SLG1-0 bits="01" r k 2k 5k 10k 20k Figure 80. THD+N vs. Input Frequency K4954 Linearity [SPP/SPN] fs=44.1k, fin=1k, SLG1-0 bits="01" r FS Figure 81. Linearity

64 -0.1 K4954 Frequency Responce [SPP/SPN] fs=44.1k, -0.5FS Input, SLG1-0 bits="01" -0.2 r k 4k 6k 8k 10k 12k 14k 16k 18k 20k Figure 82. Frequency Response K4954 THD+N ratio, Output Power vs. Input Level [SPP/SPN] fs=44.1k, fin=1k, RL=8ohm, Po=250mW(SLG1-0 bits="01") m m 200m m W 100m m FS Figure 83. THD+N vs. Output Power

65 6. DC (DC LOUT/ROUT) [fs=44.1k] K4954 FFT [LOUT/ROUT] fs=44.1k, fin=1k, 0FS Input r k 2k 5k 10k 20k Figure 84. FFT (Input level= 0FS) K4954 FFT [LOUT/ROUT] fs=44.1k, fin=1k, FS Input r k 2k 5k 10k 20k Figure 85. FFT (Input level= FS)

66 K4954 FFT [LOUT/ROUT] fs=44.1k, No Signal r k 2k 5k 10k 20k Figure 86. FFT (No signal) K4954 Out of an Noise [LOUT/ROUT] fs=44.1kk, No Signal r k 2k 5k 10k 20k 50k 100k Figure 87. FFT (Out-of-ban Noise)

67 -50 K4954 S/(N+D) vs. Input Level [LOUT/ROUT] fs=44.1k, fin=1k r FS Figure 88. THD+N vs. Input Level K4954 S/(N+D) vs. Input Frequency [LOUT/ROUT] fs=44.1k, 0FS Input r k 2k 5k 10k 20k Figure 89. THD+N vs. Input Frequency

68 K4954 Linearity[LOUT/ROUT] fs=44.1k, fin=1k r FS Figure 90. Linearity.5.4 K4954 Frequency Responce [LOUT/ROUT] fs=44.1k, 0FS Input.3 r k 4k 6k 8k 10k 12k 14k 16k 18k 20k Figure 91. Frequency Response

69 T TTT TTT T K4954 Crosstalk [LOUT/ROUT] fs=44.1k, 0FS Input k 2k 5k 10k 20k Figure 92. Crosstalk

70 7. DC (DC LOUT/ROUT) [fs=96k] K4954 FFT [LOUT/ROUT] fs=96k, fin=1k, 0FS Input r k 2k 5k 10k 20k 40k Figure 93. FFT (Input level= 0FS) K4954 FFT [LOUT/ROUT] fs=96k, fin=1k, 0FS Input r k 2k 5k 10k 20k 40k Figure 94. FFT (Input level= FS)

71 K4954 FFT [LOUT/ROUT] fs=96k, No Signal r k 2k 5k 10k 20k 40k Figure 95. FFT (No signal) K4954 Out of an Noise [LOUT/ROUT] fs=96k, No Signal r k 2k 5k 10k 20k 50k 100k Figure 96. FFT (Out-of-ban Noise)

72 -50 K4954 S/(N+D) vs. Input Level [LOUT/ROUT] fs=96k, fin=1k r FS Figure 97. THD+N vs. Input Level K4954 S/(N+D) vs. Input Frequency[LOUT/ROUT] fs=96k, 0FS Input r k 2k 5k 10k 20k 40k Figure 98. THD+N vs. Input Frequency

73 K4954 Linearity[LOUT/ROUT] fs=96k, fin=1k r FS Figure 99. Linearity.2 K4954 Frequency Responce [LOUT/ROUT] fs=96k, 0FS Input -0.2 r k 10k 15k 20k 25k 30k 35k 40k 45k Figure 100. Frequency Response

74 -70 T T K4954 Crosstalk [LOUT/ROUT] fs=96k, 0FS Input k 2k 5k 10k 20k 40k Figure 101. Crosstalk

75 REVISION HISTORY Date Manual oar Reason Page Contents (YY/MM/DD) Revision Revision 12/06/14 KM First eition - IMPORTNT NOTICE 0. sahi Kasei Microevices Corporation ( KM ) reserves the right to make changes to the information containe in this ocument without notice. When you consier any use or application of KM prouct stipulate in this ocument ( Prouct ), please make inquiries the sales office of KM or authorize istributors as to current status of the Proucts. 1. ll information inclue in this ocument are provie only to illustrate the operation an application examples of KM Proucts. KM neither makes warranties or representations with respect to the accuracy or completeness of the information containe in this ocument nor grants any license to any intellectual property rights or any other rights of KM or any thir party with respect to the information in this ocument. You are fully responsible for use of such information containe in this ocument in your prouct esign or applications. KM SSUMES NO LIILITY FOR NY LOSSES INCURRED Y YOU OR THIRD PRTIES RISING FROM THE USE OF SUCH INFORMTION IN YOUR PRODUCT DESIGN OR PPLICTIONS. 2. The Prouct is neither intene nor warrante for use in equipment or systems that require extraorinarily high levels of quality an/or reliability an/or a malfunction or failure of which may cause loss of human life, boily injury, serious property amage or serious public impact, incluing but not limite to, equipment use in nuclear facilities, equipment use in the aerospace inustry, meical equipment, equipment use for automobiles, trains, ships an other transportation, traffic signaling equipment, equipment use to control combustions or explosions, safety evices, elevators an escalators, evices relate to electric power, an equipment use in finance-relate fiels. Do not use Prouct for the above use unless specifically agree by KM in writing. 3. Though KM works continually to improve the Prouct s quality an reliability, you are responsible for complying with safety stanars an for proviing aequate esigns an safeguars for your harware, software an systems which minimize risk an avoi situations in which a malfunction or failure of the Prouct coul cause loss of human life, boily injury or amage to property, incluing ata loss or corruption. 4. Do not use or otherwise make available the Prouct or relate technology or any information containe in this ocument for any military purposes, incluing without limitation, for the esign, evelopment, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology proucts (mass estruction weapons). When exporting the Proucts or relate technology or any information containe in this ocument, you shoul comply with the applicable export control laws an regulations an follow the proceures require by such laws an regulations. The Proucts an relate technology may not be use for or incorporate into any proucts or systems whose manufacture, use, or sale is prohibite uner any applicable omestic or foreign laws or regulations. 5. Please contact KM sales representative for etails as to environmental matters such as the RoHS compatibility of the Prouct. Please use the Prouct in compliance with all applicable laws an regulations that regulate the inclusion or use of controlle substances, incluing without limitation, the EU RoHS Directive. KM assumes no liability for amages or losses occurring as a result of noncompliance with applicable laws an regulations. 6. Resale of the Prouct with provisions ifferent from the statement an/or technical features set forth in this ocument shall immeiately voi any warranty grante by KM for the Prouct an shall not create or exten in any manner whatsoever, any liability of KM. 7. This ocument may not be reprouce or uplicate, in any form, in whole or in part, without prior written consent of KM

76 USGND US5V J2 HP-OUT J3 LINE-OUT D REG1 1 VDD + C1 C2 100u 0.1u T NC Vin Vcont NC GND PCL Vout NC TK73618ME C3 0.1u + C4 100u JP3 R1 0 R33 SVDD open DVDD D VSS2 1.8V 5V 3.3V SVDD C u C u R15 22k R16 22k C GND1 1 GND C5 0.1u T NC Vin Vcont NC GND PCL Vout NC TK73633ME C6 0.1u VSS1 + C7 100u VSS3 R2 0 R3 5.1 L u VDD TVDD D3V VDD DVDD C32 10u C19 1n + VSS1 C35 2.2u VSS1 C18 1u R20 1M + VSS C31 2.2u C33 0.1u 29 C34 2.2u R19 VSS2 CP CN VDD VSS1 VCOM MRF RIN3 C26 10u 1M C30 2.2u R VEE 24 LIN3 R17 33 HPR 23 RIN2 VSS1 C27 0.1u HPL 22 LIN2 DVDD 21 + TP1 SPP 1 C24 1u U1 K4954EN MPWR2 SPP/LOUT 20 MPWR1 + TP2 SPN 1 SPN/ROUT 19 RIN1/DMCLK C25 1u SVDD SVDD 18 LIN1/DMDT + C22 10u C23 0.1u VSS3 17 PDN VSS3 TVDD 16 MCKI/OVF 15 ICK 14 LRCK 13 SDTO 12 C21 0.1u C20 10u + R12 51 R11 51 VSS2 R9 1k TVDD MCKI ICK LRCK SDTO SDTI SD SCL C SDTI 11 7 SD 10 SCL 9 R14 51 R13 51 R10 51 R8 1k 8 1 TP3 SD 1 TP4 SCL J1 MIC-IN VSS1 JP2 RIN-SEL RIN3 RIN2 RIN1 LIN3 LIN2 LIN1 JP1 LIN-SEL VSS1 C17 1n + C16 1u C14 1u C15 1n VSS1 C12 1u R7 2.2k VSS1 JP9 MP-RIN2 R6 2.2k C13 1n JP8 MP-LIN2 JP7 MP-RIN1 JP6 MP-LIN1 R5 2.2k C11 1n JP5 DMCK C10 1u R4 2.2k VSS1 JP4 DMDT C8 1u C9 1n VSS1 PDN Title KD4954- Size Document Number Rev 3 K Date: Friay, pril 26, 2013 Sheet 1 of 3 1

77 PORT3 US Connector D US5V USGND JP17 US5V 5 4 GND 3 ID 2 D+ 1 D- VUS C49 1u T3 5 6 NC GND PCL Vout NC NC Vin Vcont TK73633ME C50 0.1u + C51 10u D R32 0 R31 0 C u C 1 2 RC7/RX/DT/SDO RD4/SPP4 RC6/TX/CK 44 RC5/D+/VP 43 RC4/D-/VM 42 RD3/SPP3 41 RD2/SPP2 40 RD1/SPP1 39 RD0/SPP0 38 VUS 37 RC2/CCP1/P1 36 RC1/T1OSI/CCP2/UOE_N 35 NC/ICPORTS 34 NC/ICRST_N/ICVpp 33 RC0/T1OSO/T13CKI 32 C C52 10u + C53 0.1u RD5/SPP5/P1 RD6/SPP6/P1C RD7/SPP7/P1D VSS0 VDD0 U3 PIC18F4550 OSC2/CLKO/R6 31 OSC1/CLKI 30 VSS1 29 VDD1 28 RE2/N7/OESPP 27 XTO XTI C57 0.1u C59 X2 20M C58 22p 22p C56 10u + 8 R0/N12/INT0/FLT0/SDI/SD RE1/N6/CK2SPP 26 9 R1/N10/INT1/SCK/SCL RE0/N5/CK1SPP R2/N8/INT2/VMO R5/N4/SS_N/HLVDIN/C2OUT 24 C60 0.1u R27 100k 11 R3/N9/CPP2/VPO NC/ICCK/ICPGC 12 NC/ICDT/ICPGD 13 R4/N11/KI0/CSSPP 14 R5/KI1/PGM 15 R6/KI2/PGC 16 R7/KI3/PGD 17 MCLR_N/Vpp/RE3 18 R0/N0 19 R1/N1 20 R2/N2/Vref-/CVref 21 R4/T0CKI/C1OUT/RCV 23 R3/N3/Vref+ 22 R30 51 SCL SD US-PDN C54 0.1u 5 U4 PC9306DP1 1 GND EN 8 2 VREF1 VREF2 7 3 SCL1 SCL2 6 4 SD1 SD2 5 R28 1k R29 1k 4 1 VDD 2 MCLR 3 PGD 4 PGC 5 GND JP16 PIC R25 4.7k R26 100k 3 C55 0.1u Title KD4954- Size Document Number Rev 3 0 Control I/F (US) Date: Friay, pril 26, 2013 Sheet 3 of 3 1

78 D MCKI JP11 MCKI DIR EXT D3V C38 0.1u PORT2 1 GND 2 3 VCC IN D LRCK SDTI ICK JP12 LRCK DIR JP13 SDTI JP14 ICK EXT DIR EXT DIR EXT JP10 SDTI-SEL DIR DC SDTO ICK MCKO2 LRCK 24 MCKO1 23 VSS DVDD 21 C41 10u C42 0.1u VOUT/GP7 20 UOUT/GP6 19 COUT/GP5 18 OUT/GP4 17 TX1/GP3 16 TX0/GP2 15 NC/GP TVDD 13 C39 10u C40 0.1u VIN/GP0 12 XTL1 11 XTL0 10 OPT-OUT C SDTO US-PDN PDN JP15 SDTO R23 2.2k X M 29 C p C44 5p DUX XTO XTI PDN CM0/CDTO/CD1 U2 K4118 P/SN 9 IPS1/IIC 8 DIF2/RX7 7 VSS1 6 DIF1/RX6 5 S1 SW DIP H (ON) L(OFF) C 33 CM1/CDTI/SD TEST2 4 OCKS1 DIF0 DIF1 DIF2 34 OCKS1/CCLK/SCL DIF0/RX OCKS0/CSN/CD0 NC INT0 IPS0/RX4 1 RP1 47k K D1 HSU119 R24 10k INT1 VDD R L H C48 0.1u + 37 VCOM VSS3 RX NC RX1 TEST1 RX2 VSS4 RX R22 10k C u SW1 RESET C45 0.1u 2 C46 10u R C36 0.1u PORT1 1 2 OUT GND 3 VCC OPT-IN Title KD4954- Size Document Number Rev 3 DIR/DIT 0 Date: Friay, pril 26, 2013 Sheet 2 of 3 1

[AKD570-A] Board Outline Chart Outline Chart J J J JP JP5 JP SW JP JP JP9 J6 T T JP JP JP6 T T JP0 U JP SW JP SW U U JP7 JP8 Port Port J5 J J7 J8 Figu

[AKD570-A] Board Outline Chart Outline Chart J J J JP JP5 JP SW JP JP JP9 J6 T T JP JP JP6 T T JP0 U JP SW JP SW U U JP7 JP8 Port Port J5 J J7 J8 Figu [AKD570-A] AK570 Evaluation Board Rev. GENERA DESCRIPTION AKD570-A is an evaluation board for AK570 which is low voltage bit analog-digital converter developed for digital audio system. It supports Jacks