[AKD555-] Evaluation oard Diagram oard Diagram -5V 5V VIAS AVDD VCC TVDD VDD8 D.V J80 J80 J800 T J805 J80 T J809 J80 J807 J808 T J0 J0 AKD55X- T T5 SW

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1 [AKD555-] AKD555- AK555 Evaluation oard Rev. GENERAL DESCRIPTION The AKD55X- is an evaluation board for AK55X/X, which is bit, 8k 78kHz, ch/ch ADC. ch ADC (AK55X) : AK55, AK555, AK557 ch ADC (AK55X) : AK555, AK557 The AKD55X- is includes the analog input circuit and also has a digital interface transmitter. Further, the AKD55X- can achieve the interface with digital audio systems. Ordering guide AKD Evaluation board for AK555VN FUNCTION DIT with COAX or Optical digital output. ADC ch input is possible. NC Connector for an external clock input. -5V -VOP 5V VOP Regulators.V/.8V.8V 5V/.V TVDD AVDD VDD8 XLR CON (IN) AIN AIN AIN AIN Input uffer Input uffer AK555 AK8A (DIT) COAX-TX (OUT) OPT-TX (OUT) Clock Generator DSP Data 0pin Header Figure. AKD555- lock Diagram * Circuit diagram and PC layout are attached at the end of this manual. <KM90> 08/ - -

2 [AKD555-] Evaluation oard Diagram oard Diagram -5V 5V VIAS AVDD VCC TVDD VDD8 D.V J80 J80 J800 T J805 J80 T J809 J80 J807 J808 T J0 J0 AKD55X- T T5 SW0 SW0 PORT500 J00 PORT0 J0 PORT0 U PORT00 J00 AK55X/X PORT0 J00 PORT00 J0 SW0 SW00 SW0 SW00 U J0 J0 J00 Figure. AKD555- oard Diagram Description () U (AK555 ) bit,8k - 78kHz,ch A/D Converter. () J00,J0,J00,J0 ( Analog data ) Cannon Connector : Differential Analog Input () J0,J0,J0,J0 ( Analog data ) NC Connector : Single-ended Analog Input. () J00 / PORT00 ( Digital data ) NC Connector / Optical Connector: Digital Output. (5) J800, J80, J80,J80,J805,J80,J807,J808,J809 ( Power supply ) Power Supply Connector. () PORT00,PORT0 ( pin header ) Pin header for evaluation (MCLK, ICK, LRCK, SDTO, SDTO, TDMIN). <KM90> 08/ - -

3 [AKD555-] (7) PORT0 ( pin header ) Pin header for evaluation (DCLK, DSDOL/R, DSDOL/R). (8) U ( AK8A ) AK8A has DIT. Transports output data from AK55X/X. (9) SW00 ( Toggle switch ) Toggle type-switch PDN for AK55X/X. H : PDN = High L : PDN = Low (0) SW0 ( Toggle switch ) Toggle type-switch PDN for AK8A. H : PDN = High L : PDN = Low () SW0,SW0,SW0 ( Dip switch) DIP type-switch for AK55X/X. H : Digital signal = High L : Digital Signal = Low () SW00 ( Dip switch (Dual In-line Package switch) DIP type-switch for AK8A. H : Digital signal = High L : Digital Signal = Low () J00 ( MCLK external input ) NC Connector : External Clock Input (MCLK). () T, T, T, T, T5 Regulator for AK55X/X, AK8A, Logic Circuit. T : Regulated AVDD, VIAS (5.0V/.V) from 5V. T : Regulated VCC, VCC (5.0V) from 5V. T : Regulated TVDD (.V) from 5V. T : Regulated TVDD, VDD8 (.8V) from 5V T5 : Regulated DV (.V) from 5V. <KM90> 08/ - -

4 [AKD555-] Evaluation oard Manual Operation sequence [] Power supply line settings [] Jumped pins settings [] DIP switches settings [] Toggle switches settings [5] Register control (Serial control) [] Evaluation modes <KM90> 08/ - -

5 [AKD555-] [] Power supply line settings (-) Power supply settings : Used the regulator (T,T,T,T,T5) <Default> Set up the power supplied lines : * Each supply line should be distributed from the power supply unit. Name Color Setting (Typ) Function Comments Default Settings J800 5V Green 5V Regulator and Op-amp power supply J80-5V lue -5V Regulator and Op-amp power supply Should always be connected 5V Should always be connected -5V J80 AVDD Red 5.0V /.V AK55X/X AVDD 5.0V/.V regulator is J805 VIAS Red 5.0V /.V Referential Voltage source for Op-amp J809 VCC Red 5.0V.V Regulator power supply J80 TVDD Orange.V /.8V AK55X/X TVDD, Logic IC power supply used, R807=short by default. When jack is used, R808=short. 5.0V/.V regulator is used, R809=short by default. When jack is used, R80=short. 5.0V regulator is used, R8=short by default. When jack is used, R8=short..V regulator is used, JP800=.V and JP80=REG by default. When.8V regulator is used, JP800=.8V and JP80=REG. When jack is used, JP80=JACK short. J807 VDD8 Orange.8V AK55X/X VDD8 LDO of AK55X/X is used, J808 D.V Orange.V AK8A.V VDD, Logic IC power supply JP80=open by default. When.8V regulator is used, JP80=REG. When jack is used, JP80=JACK..V regulator is used, JP80=REG by default. When jack is used, JP80=JACK. J80 lack 0V Ground Should always be connected 0V Table -. Power supply line setting ( default : used the regulator ) REG : (R807 = short) REG : (R809 = short) REG : (R8 = short) REG (.V) : (JP800=.V and JP80=REG) Open : (JP80=open) REG : (JP80=REG) <KM90> 08/ - 5-

6 [AKD555-] (-) About jumper for power supply : The roles of the jumper or the short resistance for each power supply supplied from the regulator are as follows. Connection of the jumper for power supply : Name Function Comments Default Settings R807 R808 AVDD Select regulator power supply or jack for AVDD AVDD for AK55X/X: R007=short : 5.0V/.V regulator is used. (default) R008=short : Jack is used. REG : R807=short R808=open R809 R80 VIAS Select regulator power supply or jack for VIAS VIAS for Op-amp Referential Voltage source: R809=short : 5.0V/.V regulator is used. (default) R80=short : Jack is used. REG : R809=short R80=open R8 R8 VCC, VCC Select regulator power supply or jack for 5.0V Regulator power supply VCC, VCC for 5.0V Regulator power supply: R8=short : 5.0V regulator is used. (default) R8=short : Jack is used. REG : R8=short R8=open JP800 TVDD-VSEL Select regulator power supply.v or.8v for TVDD TVDD for AK55X/X and Logic IC: JP800=.V :.V regulator is used. (default).v : JP800=.V JP800=.8V :.8V regulator is used. JP80 TVDD-SEL Select regulator power supply or jack for TVDD TVDD for AK55X/X and Logic IC: JP80=REG : Regulator is used. (default) REG : JP80=REG JP80=JACK: Jack is used. JP80 VDD8-SEL Select External power supply or LDO power supply of AK55XX VDD8 selector for AK55X/X: JP80=REG : External Power supply of.8v regulator is LDO of AK55XX : JP80=open for VDD8 used. JP80=JACK : External Power supply of Jack is used. JP80=open : LDO of AK55X/X is used. (default) JP80 DV-SEL Select regulator power supply or jack for DV DV for AK8A and Logic IC: JP00=REG :.V regulator is used. (default) JP00=JACK : Jack is used. REG : JP80=REG Table -. Jumper for power supply <KM90> 08/ - -

7 [AKD555-] [] Jumped pins settings No Names Default Functions JP00 TXDATA-SEL COAX Select COAX / Optical Connector for TX data of AK8A. COAX: COAX for TX data of AK8A. (default) OPT: Optical for TX data of AK8A. JP0 EXTMCLK-SEL XTL Select input to AK8A (U) MCLK. XTL: X00 to AK8A. (default) EXT: PORT0 signal to AK8A. PORT05 ICK-SEL DIT Select input / output to AK55X/X (U) ICK DIT: ICK-AK8A-T (default) PORT: Pin Header PORT00-ICK GND: Connected to Open: No signal PORT0 LRCK-SEL DIT Select input / output to AK55X/X (U) LRCK DIT: LRCK-AK8A-T (default) PORT: Pin Header PORT00-LRCK GND: Connected to Open: No signal 5 PORT07 ICK-PHASE THR Select polarity (non-inverted output / inverted output) of ICK-SEL inputs / outputs. THR: Non-inverted output. (default) INV: Inverted output. PORT08 SDTO-SEL SDTO Select input to DIT:AK8A (U) DAUX SDTO: AK55X/X-SDTO is used. (default) SDTO: AK55X/X-SDTO is used. open: No signal for DAUX-AK8A-T 7 PORT09 TDMI-SEL Open Select connect to AK55X/X (U) TDMI Open: No signal for TDMIN (default) Short: Pin Header PORT0-TDMIN 8 PORT0 MCKI-SEL DIT Select input to AK55X/X (U) MCLK DIT: MCLK-AK8A-T (default) PORT: Pin Header PORT00-MCLK EXT: External MCLK (JACK:J00 EXT) input. GND: Connected to 9 JP00 EXT Open Open: No input (default) Short: External MCLK (JACK:J00 EXT) input. 0 JP700 PS-SEL SDA/CDTI Select input / output to AK55X/X (U) CKS0/SDA/CDTI SDA/CDTI: SDA/CDTI signal input / output to AK55X/X. (default) CKS0: CKS0 signal of SW0 input to AK55X/X. JP70 PS-SEL CAD0-IC/CSN Select input to AK55XX (U) CKS/CAD0-IC/CSN CAD0-IC/CSN: CAD0-IC/CSN signal input to AK55XX. (default) CKS: CKS signal of SW0 input to AK55XX. JP70 PS-SEL CAD0-IC Select input to JP70 CAD0-IC/CSN CAD0-IC: CAD0-IC signal of SW0 input to JP70. (default) CSN: CSN signal of SW0 input to JP70. <KM90> 08/ - 7-

8 [AKD555-] JP70 PS-SEL SCL/CCLK Select input to AK55X/X (U) CKS/SCL/CCLK SCL/CCLK: SCL/CCLK signal input to AK55X/X. (default) CKS: CKS signal of SW0 input to AK55X/X. JP70 PS-SEL5 CAD Select input to AK55X/X (U) CKS/CAD CAD: CAD signal input to AK55X/X. (default) CKS: CKS signal of SW0 input to AK55X/X. 5 JP705 PS-SEL PS Select input to AK55X/X (U) PS/CAD0-SPI PS: PS signal input to AK55X/X. (default) CAD0-SPI: CAD0-SPI signal of SW0 input to AK55X/X. JP800 TVDD-VSEL.V Select power supply voltage of TVDD.V: Regulator T (5V =>.V) (default).8v: Regulator T (5V =>.8V) 7 JP80 TVDD-SEL TVDD Select power supply to TVDD REG: Regulator T/T (default) JACK: Power supply jack J80 TVDD 8 JP80 VDD8-SEL REG Select power supply to VDD8 REG: Regulator T (default) JACK: Power supply jack J807 VDD8 0 JP80 DV-SEL REG Select power supply to DV REG: Regulator T5 (5V =>.V) (default) JACK: Power supply jack J808 D.V Table. Main board Jumper pin setting <KM90> 08/ - 8-

9 [AKD555-] [] DIP switches settings (-). Setting for SW00 (Sets AK8A (U) audio format and master clock setting) No. Switch Name Function default DIF Set-up of DIF0 pin. H DIF Set-up of DIF pin. L DIF0 Set-up of DIF pin. H OCKS Set-up of OCKS pin. H 5 OCKS0 Set-up of OCKS0 pin. L Table -. SW00 Setting (AK8A) Mode DIF pin DIF pin DIF0 pin LRCK ICK DAUX SW00- SW00- SW00- I/O I/O bit, Left justified H/L O fs O 0 0 bit, Left justified H/L O fs O 0 0 bit, Left justified H/L O fs O 0 bit, Left justified H/L O fs O 0 0 bit, Left justified H/L O fs O 5 0 bit, I S L/H O fs O default 0 bit, Left justified H/L I -8fs I 7 bit, I S L/H I -8fs I Table -. Audio format (AK8A) OCKS pin OCKS0 pin SW00- SW00-5 (X tal) MCKO fs (max) 0 0 5fs 5fs 9 khz 0 5fs 5fs 9 khz 0 5fs 5fs 8 khz default 8fs 8fs 9 khz Table -. Master Clock Frequency Select (AK8A) <KM90> 08/ - 9-

10 [AKD555-] (-). Setting for SW0 (Sets AK55X/X (U) ) No. Switch Name Function default TEST TEST Enable. L PW0 ADC Power Management and Monaural / Stereo select. H PW ADC Power Management and Monaural / Stereo select. H PW ADC Power Management and Monaural / Stereo select. H 5 MSN Master/Slave select. L: Slave Mode H: Master Mode L CAD0-SPI Chip Address0 Pin in -wire serial control mode. L (IC pin = L ) 7 CAD0-IC Chip Address0 Pin in IC bus serial control mode. L (IC pin = H, PS pin = L ) Chip Address Pin in IC bus or -wire serial control mode. L 8 CAD (-wire : IC pin = L ) (IC bus : IC = H, PS pin L ) Table -. SW0 Setting (-). Setting for SW0 (Sets AK55X/X (U) ) No. Switch Name Function default CKS0 Clock Mode Setting #0 L CKS Clock Mode Setting # H CKS Clock Mode Setting # H CKS Clock Mode Setting # L DIF0 : Audio Data Format select in PCM Mode H 5 DIF0/DSDSEL0 L: MS justified H: IS DSDSEL0 : DSD Sampling Rate Control in DSD Mode DIF/DSDSEL DIF : Audio Data Format select in PCM Mode L: -bit Mode H: -bit Mode DSDSEL : DSD Sampling Rate Control in DSD Mode L 7 SLOW/DCK SLOW : Slow Roll-OFF Digital Filter select in PCM Mode L DCLK : Polarity of DCLK in DSD Mode 8 SD/PMOD SD : Short Delay Digital Filter select in PCM Mode L PMOD : DSD Phase Modulation Mode select in DSD Mode Table -5. SW0 Setting <KM90> 08/ - 0-

11 [AKD555-] (-). Setting for SW0 (Sets AK55X/X (U) ) No. Switch Name Function default LDO Enable H LDOE L: LDO Disable H: LDO Enable ODP Output Data Placement Select. L TDM0 TDM Interface Format select #0 L TDM TDM Interface Format select # L Control mode select (IC pin = H ) L 5 PS L: IC us serial control mode H: Parallel control mode Control mode select H IC L: -wire serial control mode H: IC us serial control mode DSD Mode Enable L 7 DP L: PCM Mode H: DSD Mode 8 HPFE/DCKS HPFE : High Pass Filter Enable L: HPF Disable H: HPF Enable DCKS : Master Clock Frequency select at DSD Mode (DSD only) L: 5fs H: 78fs H Table -. SW0 Setting <KM90> 08/ - -

12 [AKD555-] Parallel Mode, ODP pin = L : PW0 pin PW pin PW pin Power ON/OFF Data on Slot SW0- SW0- SW0- Ch Ch Ch Ch Slot Slot Slot Slot L L L OFF OFF OFF OFF All 0 All 0 All 0 All 0 L L H ON ON OFF OFF (CH) (CH) All 0 or All 0 or / / TDMI TDMI L H L OFF OFF ON ON All 0 or All 0 or (CH) (CH) TDMI TDMI / / L H H ON ON ON ON (CH) (CH) (CH) (CH) / / / / H L L OFF ON ON ON All 0 CH CH CH H L H ON ON OFF OFF CH CH All 0 All 0 H H L OFF OFF ON ON All 0 All 0 CH CH H H H ON ON ON ON CH CH CH CH default Table Channel Power & Mono Mode Select (ODP pin = L ) (AK55X) Parallel Mode, ODP pin = H : PW0 pin PW pin PW pin Power ON/OFF Data on Slot SW0- SW0- SW0- Ch Ch Ch Ch Slot Slot Slot Slot L L L OFF OFF OFF OFF All 0 All 0 All 0 All 0 All 0 or All 0 or (CH) (CH) L L H ON ON ON ON TDMI TDMI / / L H L ON ON ON ON CH CH CH CH All 0 All 0 All 0 (CH L H H ON ON ON ON or or or )/ TDMI TDMI TDMI H L L ON ON ON ON CH CH CH CH All 0 or All 0 or (CH) (CH) H L H ON ON ON ON TDMI TDMI / / H H L ON ON ON ON CH CH CH CH All 0 or All 0 or All 0 or (CH H H H ON ON ON ON TDMI TDMI TDMI )/ Table Channel Power & Mono Mode Select (ODP pin = H ) (AK55X) <KM90> 08/ - -

13 [AKD555-] Parallel Mode, ODP pin = L : PW0 pin SW0- PW pin SW0- PW pin SW0- Power Data on Slot ON/OFF Ch Ch Slot Slot L L L OFF OFF All 0 All 0 L L H ON OFF CH All 0 L H L OFF ON All 0 CH L H H ON ON (CH) (CH) / / H L L OFF OFF All 0 All 0 H L H ON OFF CH All 0 H H L OFF ON All 0 CH H H H ON ON CH CH default Table Channel Power & Mono Mode Select (ODP pin = L ) (AK55X) Parallel Mode, ODP pin = H : PW0 pin SW0- PW pin SW0- PW pin SW0- Power Data on Slot ON/OFF Ch Ch Slot Slot L L L OFF OFF All 0 All 0 (CH) (CH) L L H ON ON / / L H L ON ON CH CH All 0 (CH) L H H ON ON or TDMI / H L L ON ON CH CH (CH) (CH) H L H ON ON / / H H L ON ON CH CH All 0 (CH) H H H ON ON or TDMI / Table Channel Power & Mono Mode Select (ODP pin = H ) (AK55X) <KM90> 08/ - -

14 [AKD555-] CKS pin SW0- CKS pin SW0- CKS pin SW0- CKS0 pin SW0- L(0) L(0) L(0) L(0) L(0) L(0) L(0) H() L(0) L(0) H() L(0) L(0) L(0) H() H() L(0) H() L(0) L(0) L(0) H() L(0) H() L(0) H() H() L(0) L(0) H() H() H() H() L(0) L(0) L(0) H() L(0) L(0) H() H() L(0) H() L(0) H() L(0) H() H() H() H() L(0) L(0) H() H() L(0) H() H() H() H() L(0) H() H() H() H() MSN pin SW0-5 L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) H() L(0) - MCLK Frequency 8fs M 9fs M 5fs M 5fs M 8fs M 8fs 8M 5fs M 78fs M fs M fs M 9fs M 8fs M fs 9.M 0fs M NA Auto Table -8. MCLK Frequency Select (AK55X/X) fs Range Quad Speed Mode 08kHz fs khz Quad Speed Mode 08kHz fs khz Normal Speed Mode 8kHz fs 5kHz Double Speed Mode 5kHz fs 08kHz Double Speed Mode 5kHz fs 08kHz Normal Speed Mode 8kHz fs 5kHz Normal Speed Mode 8kHz fs 5kHz Normal Speed Mode 8kHz fs 5kHz Oct Speed Mode fs = 8kHz Hex Speed Mode fs = 78kHz Oct Speed Mode fs = 8kHz Hex Speed Mode fs = 78kHz Hex Speed Mode fs = 78kHz Normal Speed Mode 8kHz fs khz NA 8kHz fs khz default <KM90> 08/ - -

15 [AKD555-] DSDSEL pin SW0- DSDSEL0 pin SW0-5 Frequency Mode DSD Sampling Frequency fs=khz fs=.khz fs=8khz L(0) L(0) fs.08mhz.8mhz.07mhz default L(0) H() 8fs.09MHz 5.8MHz.MHz H() L(0) 5fs 8.9MHz.89MHz.88MHz H() H() - Reserved (8.9MHz) Reserved (.89MHz) Table -9. DSD Sampling Frequency Select (AK55X/X) Reserved (.88MHz) Multiplex Speed TDM No. Mode Mode SW0-0 TDM0 SW0- MSN DIF DIF0 SDTO SW0-5 SW0- SW0-5 LRCK ICK MCLK Pol. I/O Freq. I/O Freq. I/O L(0) L(0) -bit, MS I 8-8fs I 8-0fs I L(0) H() -bit, I S I 8-8fs I 8-0fs I default L(0) H() L(0) -bit, MS I -8fs I 8-0fs I Normal H() H() -bit, I S I -8fs I 8-0fs I Double L(0) L(0) L(0) L(0) -bit, MS O fs O 8-0fs I Quad 5 L(0) H() -bit, I S O fs O 8-0fs I H() H() L(0) -bit, MS O fs O 8-0fs I 7 H() H() -bit, I S O fs O 8-0fs I 8 * L(0) -bit, MS I fs I -9fs I 9 * H() -bit, I S I fs I -9fs I 0 * L(0) -bit, MS I 8fs I -9fs I * H() -bit, I S I 8fs I -9fs I Normal L(0) L(0) L(0) -bit, MS O fs O -9fs I L(0) H() -bit, I S O fs O -9fs I H() L(0) -bit, MS O fs O -9fs I 5 OCT H() H() -bit, I S O fs O -9fs I L(0) L(0) HEX * L(0) -bit, MS I fs I fs I 7 * H() -bit, I S I fs I fs I 8 * L(0) -bit, MS I 8fs I 8fs I 9 * H() -bit, I S I 8fs I 8fs I H() 0 L(0) L(0) -bit, MS O fs O fs I L(0) H() -bit, I S O fs O fs I H() L(0) -bit, MS O fs O fs I H() H() -bit, IS O fs O fs I Table -0. Audio Interface Format Select ( Normal mode, OCT/HEX mode) : PCM Mode (AK55X/X) <KM90> 08/ - 5-

16 [AKD555-] Multiplex Speed TDM No. Mode Mode SW0- TDM0 SW0- MSN SW0-5 DIF SW0- DIF0 SDTO SW0-5 LRCK ICK MCLK Edg. I/O Freq. I/O Freq. I/O L(0) L(0) -bit, MS I 8fs I 8-0fs I 5 L(0) H() -bit, I S I 8fs I 8-0fs I L(0) H() L(0) -bit, MS I 8fs I 8-0fs I Normal 7 H() H() -bit, I S I 8fs I 8-0fs I TDM8 Double L(0) H() 8 L(0) L(0) -bit, MS O 8fs O 8-0fs I Quad 9 L(0) H() -bit, I S O 8fs O 8-0fs I H() 0 H() L(0) -bit, MS O 8fs O 8-0fs I H() H() -bit, I S O 8fs O 8-0fs I L(0) L(0) -bit, MS I 5fs I 5-0fs I L(0) H() -bit, I S I 5fs I 5-0fs I L(0) H() L(0) -bit, MS I 5fs I 5-0fs I 5 TDM5 Normal H() H() -bit, I S I 5fs I 5-0fs I H() L(0) Double L(0) L(0) -bit, MS O 5fs O 5-0fs I 7 L(0) H() -bit, I S O 5fs O 5-0fs I H() 8 H() L(0) -bit, MS O 5fs O 5-0fs I 9 H() H() -bit, I S O 5fs O 5-0fs I 0 L(0) L(0) -bit, MS I 5fs I 5-0fs I L(0) H() -bit, I S I 5fs I 5-0fs I L(0) H() L(0) -bit, MS I 5fs I 5-0fs I H() H() -bit, I S I 5fs I 5-0fs I TDM5 Normal H() H() L(0) L(0) -bit, MS O 5fs O 5-0fs I 5 L(0) H() -bit, I S O 5fs O 5-0fs I H() H() L(0) -bit, MS O 5fs O 5-0fs I 7 H() H() -bit, I S O 5fs O 5-0fs I Table -. Audio Interface Format Select ( TDM mode) : PCM Mode (AK55X/X) SD SW0-8 SLOW SW0-7 Filter L L Sharp Roll-off Filter default L H Slow Roll-off Filter H L Short Delay Sharp Roll-off Filter H H Short Delay Slow Roll-off Filter Table -. Digital Filter Select : PCM Mode (AK55X/X) LDOE SW0- PDN SW00 LDO VDD8 pin TVDD pin Power Supply L L OFF External Power Supply.7~.98V.7~.98V L H OFF External Power Supply.7~.98V.7~.98V H L OFF Internal 500 Pull Down.0~.V H H ON LDO Power Output.0~.V default Table -. LDO Select (AK55X/X) <KM90> 08/ - -

17 [AKD555-] IC pin SW0- PS pin SW0-5 Control Mode L L -wire Serial L H -wire Serial H L I C us default H H Parallel Table -. Control Mode Select (AK55X/X) <KM90> 08/ - 7-

18 [AKD555-] [] Toggle switches settings Up= H, Down= L [SW00] ( Power Down (PDN) for AK55X/X): Power Down (PDN) Switch for AK55X/X Reset AK55X/X (U) once by brining SW00 to L once upon power-up. Keep H when AK55X/X is in use; keep L when AK55X/X is not in use. [SW0] ( Power Down (PDN) for AK8A): Power Down (PDN) Switch for AK8A Reset AK8A (U) once by brining SW0 to L once upon power-up. Keep H when AK8A is in use; keep L when AK8A is not in use. <KM90> 08/ - 8-

19 [AKD555-] [5] Register control (Serial control) AKD555- can be controlled US control box. Connect board to PC using 0-wire flat cable (PORT500 serial up-if) included with the AKD555-. There is a mark on the no.-pin of the 0-pin Connector. See Figure.. The pin assignments of PORT below. 9 CSN CCLK / SCL CDTI / SDA NC NC PORT700 up I/F 0 GND GND GND GND GND Figure. The pin assignments of PORT500 The control software is packed with the evaluation board. The software operation sequence is included in the evaluation board manual. <KM90> 08/ - 9-

20 [AKD555-] [] Evaluation modes (-) ADC Differential Analog Input Connector ( ch/ch Mode ) ADC Channel Ch Ch Ch Ch ch J00 J0 J00 J0 ch J00 J0 - - Table -. Differential Analog Input Connector (--) ch mode ch: Cannon Connector = J00, ch: Cannon Connector = J0 ch: Cannon Connector = J00, ch: Cannon Connector = J0 (--) ch mode ch: Cannon Connector = J00, ch: Cannon Connector = J0 (-) ADC Master / Slave Mode (--) Slave Mode SW0-5 = L ( MSN pin = L ) (--) Matser Mode SW0-5 = H ( MSN pin = H ) (-) ADC PCM / DSD Mode (--) PCM Mode SW0-5 = L ( MSN pin = L ), SW0-7 = L ( DP pin = L ) (--) DSD Mode SW0-5 = H ( MSN pin = H ), SW0-7 = H ( DP pin = H ) (-) ADC (Analog Digital) : PCM Mode, Slave Mode Toggle switch setting: SW00 L H AK55X/X(U) : Used SW0 L H AK8A(U) : Used Table -. Toggle switch setting Start up Control Register Setting : Port Reset & Write Default. : Set Addr: 0h = to Data and Clock format on ADC. Other control register settings are default. Mode settings : Normal Speed Mode, bit, IS, MCLK=5fs DIF-0: Audio Data Interface Modes Select (Table -5, Table -0) CKS-0: Sampling Speed Mode and MCLK Frequency Select (Table -5, Table -8) Addr Register Name D7 D D5 D D D D D0 0H Control CKS CKS CKS CKS0 DIF DIF0 HPFE R/W R/W R/W R/W R/W R/W R/W R/W R/W Default Table -. Addr 0H control register setting <KM90> 08/ - 0-

21 [AKD555-] (-5) ADC (Analog Digital) : PCM Mode, Master Mode Toggle switch setting: SW00 L H AK55X/X(U) : Used SW0 L H AK8A(U) : Used Table -. Toggle switch setting Start up Control Register Setting : Port Reset & Write Default. : Set Addr: 0h = to Data and Clock format on ADC. Other control register settings are default. : Set SW0-5 = H (MSN pin= H ) to Master Mode on ADC. Other switch settings are default. Mode settings : Normal Speed Mode, bit, IS, MCLK=5fs DIF-0: Audio Data Interface Modes Select (Table -5, Table -0) CKS-0: Sampling Speed Mode and MCLK Frequency Select (Table -5, Table -8) Addr Register Name D7 D D5 D D D D D0 0H Control CKS CKS CKS CKS0 DIF DIF0 HPFE R/W R/W R/W R/W R/W R/W R/W R/W R/W Default Table -5. Addr 0H control register setting (-) ADC (Analog Digital) : DSD Mode Toggle switch setting: SW00 L H AK55X/X(U) : Used SW0 L H AK8A(U) : Used Table -. Toggle switch setting Start up Control Register Setting : Port Reset & Write Default. : Set Addr: 0h = 80 to DSD Mode on ADC. Other control register settings are default. : Set SW0-5 = H (MSN pin= H ), SW0-7= H (DP pin= H ) to DSD Mode on ADC. Other switch settings are default. DP: DSD Mode Select 0: PCM Mode (default) : DSD Mode Addr Register Name D7 D D5 D D D D D0 0H DSD DP SD SLOW R/W R/W R/W R/W R/W R/W R/W R/W R/W Default Table -7. Addr 0H control register setting <KM90> 08/ - -

22 [AKD555-] Control Software Manual Set-up evaluation board and control software. Set up AKD555- evaluation board according to above instructions.. Connect PC with AKD555- evaluation board by US control box (included in package).. Insert the CD-ROM labeled AKD555- Evaluation Kit into the CD-ROM drive.. Access the CD-ROM drive, double-click on AKD555.exe and set up the control program. 5. Evaluate according to the following. Operation flow. Set up control program as above and open control program. The following operation screen will be shown. (Default setting) Figure7--. Control software window [AK557] <KM90> 08/ - -

23 [AKD555-] Figure7--. Control software window [AK557] Figure7--. Control software window [AK555] <KM90> 08/ - -

24 [AKD555-] Figure7--. Control software window [AK555] Figure7--5. Control software window [AK55] <KM90> 08/ - -

25 [AKD555-]. Click the Write button on right side of Addr 0H register. Figure 7-. Register set window. Input dummy command settings and click OK to write dummy command to AK55X/X. The following No Ack error message will pop up. Click OK. Figure 7-. No ack message window. Input registers accordingly into dialog box to evaluate AK55X/X. utton Functions. [Port Reset] : Set up US interface board (AKDUSIF-).. [Write Default] : Initialize all register setting.. [All Write] : Write all registers currently displayed.. [All Read] : Read all register setting. 5. [Save] : Save the current register setting to.akr file.. [Load] : Load register setting from saved.akr file. 7. [All Reg Write] : Opens All Register Write dialog box. (see Dialog boxes below) 8. [Data R/W] : Opens Data Read/Write dialog box. (see Dialog boxes below) 9. [Read] : Read and display current register setting in register window (on right side of main window). Different from [All Read] as it does not reflect to the register map. 0. [Close] : Close Control Software window. <KM90> 08/ - 5-

26 [AKD555-] Dialog boxes. [All Register Write]: Dialog box to write register setting files Clicking the [All Reg Write] button in the main window opens the dialog box below. Multiple register setting files created by the [SAVE] button can be set and applied. Figure 7-. Window of [All Reg Write] <Operation flow> () Click [Open(left) utton. () Select file (*.akr) and Click [Open] utton. Up to 0 files can be selected. () Click [Write] to write each file. [Write ALL] writes all files selected. utton Functions:. [Open (left)] : Select register setting file (*.akr).. [Write] : Write register setting file in textbox.. [Write ALL] : Write all register setting files selected. Write is executed in descending order.. [Help] : Help window pops up. 5. [Save] : Save the current register map setting (*.mar).. [Open (right)] : Load register map setting file (*.mar ). 7. [Close] : Close dialog box. <KM90> 08/ - -

27 [AKD555-]. [Data Read/Write]: Dialog box to manually enter register setting Click the [Data R/W] button in the main window to open the data read/write dialog box. Data manually entered into Data box is written to the specified address. Figure 7-5. Window of [Data R/W] Textbox Functions: [Address] : Input register address in hexadecimal digits. [Data] : Input register data in hexadecimal digits. [Mask] : Input mask data in hexadecimal digits. This value is AND-ed with input data. utton Functions: [Write] : Writes data generated from [Data] and [Mask] to register specified in [Address] [Read] : Displays register data specified in [Address] in [Read Data] box in hexadedimal. [Close] : Closes dialog box. To cancel a process close the dialog box without writing Register map updated after [Write] and [Read] operation. <KM90> 08/ - 7-

28 [AKD555-] Tab Functions. [REG]: Register Map Register data is indicated on the register map. Each bit on the register map is a push-button switch. utton DOWN and red lettering indicates and button UP with blue lettering indicates 0. uttons with --- are undefined in the datasheet. Figure 7-. [REG] window (REG 00H-07H) <KM90> 08/ - 8-

29 [AKD555-]. [Tool]: Testing Tools This tab screen is for the evaluation testing tool. Click button for each testing tool. Figure 7-8. [Tool] window <KM90> 08/ - 9-

30 [AKD555-] Analog input Circuit Analog input Circuit on AKD55X- Cannon Connectors (J00,J0,J00,J0) : Differential analog input signals for AK55X/X Analog input Circuit :.7k 0 Analog In.9Vpp.7k VP - VP- NJM55 open Vin- 8µ.k ias n - NJM p.8Vpp AK55X/X AINn VA XLR 0 5n 0k 0k 0µ 0.µ ias VA=5 VP= 5 open Vin 8µ n.k - NJM55 ias 0 00p.8Vpp AK55X/X AINn- Figure 8-. Analog Input Circuit <KM90> 08/ - 0-

31 [AKD555-] Measurement Results [Measurement condition] Measurement unit : Audio Precision SYS-7(0009) MCKI : 5fs/5fs/8fs (.57MHz ) ICK : fs fs : 8kHz / 9kHz / 9kHz it : bit Measurement Mode : Slave Mode Power Supply : VOP(5V)=5V, GND AVDD=5.0V (Regulator), DVDD=.V (Regulator) Input Frequency : khz Measurement Frequency : 0 ~ / / Temperature : Room [Measurement Results]. Stereo ADC (Differential Inputs) Stereo ADC : AINL/R => ADC => SDTO/ S/(ND) Result SDTO - Lch Rch - - fs = 8kHz (-dfs) d fs = 9kHz (-dfs) d fs = 9kHz (-dfs) d DR fs = 8kHz (-0dFS, A-Weighted) d S/N fs = 8kHz (A-weighted) d Unit <KM90> 08/ - -

32 [AKD555-] [Plots] [ SDTO ] : Stereo Mode fs = 8 khz AK555 FFT (-dfs Input) AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S k k 5k 0k 0k Hz Figure 9-. FFT (-dfs Input) AK555 FFT ( -0dFS Input) AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S k k 5k 0k 0k Hz Figure 9-. FFT (-0dFS Input) <KM90> 08/ - -

33 [AKD555-] fs = 8 khz AK555 FFT ( No Signal Input) AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S k k 5k 0k 0k Hz Figure 9-. FFT (No Signal Input) AK555 THDN vs. Input Level AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S dr Figure 9-. THDN vs. Input Level <KM90> 08/ - -

34 [AKD555-] fs = 8 khz AK555 THDN vs. Input Frequency AVDD=5.0V, DVDD=.V, MCLK=5fs, -dfs Input d F S k k 5k 0k 0k Hz Figure 9-5. THDN vs. Input Frequency AK555 Linearity AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S dr Figure 9-. Linearity <KM90> 08/ - -

35 [AKD555-] fs = 8 khz AK555 Frequency Response AVDD=5.0V, DVDD=.V, MCLK=5fs, -dfs input d F S k k 5k 0k 0k Hz Figure 9-7. Frequency Response <KM90> 08/ - 5-

36 [AKD555-] fs = 9 khz AK555 FFT (-dfs Input) AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S k k 5k 0k 0k 0k Hz Figure 9-8. FFT (-dfs Input) AK555 FFT ( -0dFS Input) AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S k k 5k 0k 0k 0k Hz Figure 9-9. FFT (-0dFS Input) <KM90> 08/ - -

37 [AKD555-] fs =9 khz AK555 FFT ( No Signal Input) AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S k k 5k 0k 0k 0k Hz Figure 9-0. FFT (No Signal Input) AK555 THDN vs. Input Level AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S dr Figure 9-. THDN vs. Input Level <KM90> 08/ - 7-

38 [AKD555-] fs = 9 khz AK555 THDN vs. Input Frequency AVDD=5.0V, DVDD=.V, MCLK=5fs, -dfs Input d F S k k 5k 0k 0k 0k Hz Figure 9-. THDN vs. Input Frequency AK555 Linearity AVDD=5.0V, DVDD=.V, MCLK=5fs, fin=khz d F S dr Figure 9-. Linearity <KM90> 08/ - 8-

39 [AKD555-] fs = 9 khz AK555 Frequency Response AVDD=5.0V, DVDD=.V, MCLK=5fs, -dfs Input d F S k k 5k 0k 0k 0k Hz Figure 9-. Frequency Response <KM90> 08/ - 9-

40 [AKD555-] fs = 9 khz AK555 FFT (-dfs Input) AVDD=5.0V, DVDD=.V, MCLK=8fs, fin=khz d F S k k 5k 0k 0k 50k 80k Hz Figure 9-5. FFT (-dfs Input) AK555 FFT ( -0dFS Input) AVDD=5.0V, DVDD=.V, MCLK=8fs, fin=khz d F S k k 5k 0k 0k 50k 80k Hz Figure 9-. FFT (-0dFS Input) <KM90> 08/ - 0-

41 [AKD555-] fs =9 khz AK555 FFT ( No Signal Input) AVDD=5.0V, DVDD=.V, MCLK=8fs, fin=khz d F S k k 5k 0k 0k 50k 80k Hz Figure 9-7. FFT (No Signal Input) AK555 THDN vs. Input Level AVDD=5.0V, DVDD=.V, MCLK=8fs, fin=khz d F S dr Figure 9-8. THDN vs. Input Level <KM90> 08/ - -

42 [AKD555-] fs = 9 khz AK555 THDN vs. Input Frequency AVDD=5.0V, DVDD=.V, MCLK=8fs, -dfs Input d F S k k 5k 0k 0k 50k 80k Hz Figure 9-9. THDN vs. Input Frequency AK555 Linearity AVDD=5.0V, DVDD=.V, MCLK=8fs, fin=khz d F S dr Figure 9-0. Linearity <KM90> 08/ - -

43 [AKD555-] fs = 9 khz AK555 Frequency Response AVDD=5.0V, DVDD=.V, MCLK=8fs, -dfs Input d F S k k 5k 0k 0k 50k 80k Hz Figure 9-. Frequency Response <KM90> 08/ - -

44 [AKD555-] REVISION HISTORY Date (YY/MM/DD) Manual Revision oard Revision 5/0/0 KM900 0 First edition - Reason Page Contents 5/07/0 KM90 Change - Add Measurement Results. 5/09/0 KM90 Change - Device Revision Up. Update oard Revision. /05/ KM90 Change - Update Measurement Results. 8//8 KM90 Change - Schematic Changed. Update oard Revision. <KM90> 08/ - -

45 [AKD555-] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ( AKM ) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ( Product ), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products.. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIAILITY FOR ANY LOSSES INCURRED Y YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing.. Though AKM works continually to improve the Product s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption.. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. <KM90> 08/ - 5-

46 5 E AIN-N0 TP5 AIN-P0 TP TEST TP LDOE TP HPFE/DCKS TP DP E D SD/PMOD SLOW/DCK CKS/CAD D C R7 5 TDMIN/DSDOR R 5 LRCK/DSDOL C R5 5 ICK/DCLK TEST MCLK TVDD D VDD8 PDN PW0 PW PW TP0 IC MSN TP9 PS/CAD0-SPI AINN TP8 TDM/OVFRST AINP TP7 TDM0/OVFFUNC TEST TP DIF/DSDSEL LODE TP5 DIF0/DSDSEL0 DCKS/HPFE DP IC PS/CAD0-SP OVFRST/TDM OVFFUNC/TDM0 DIF/DSDSEL DIF0/DSDSEL0 TP AVDD VREFL VREFH SD/PMOD TP SLOW/DCK TP CKS/CAD AVDD AIN-P0 AIN-N0 AINN AINP AVDD A AINP AINN TP CKS/SCL/CCLK TP0 CKS/CAD0-IC/CSN TP9 CKS0/SDA/CDTI TP8 OVF TP7 SDTO/DSDOR TP SDTO/DSDOL TP07 AVDD R09 VREFH VREFL TP5 TDMIN/DSDOR TP LRCK/DSDOL TP ICK/DCLK C09 : CapDipopenpinSocket (MCLK Cap) C : CapDipopenpinSocket (PDN Cap) AINN AINP R 0 R 0 R9 0 R7 0 R00 (short) R0 NC VREFL VREFH AINN 8 7 AINP TEST 5 LDOE SD/PMOD 5 SLOW/DCK CKS/CAD R 0 R5 0 R 0 AIN-N0 TP0 AIN-P0 TP0 R50 (short) R07 R0 (short) C0 0u R5 (short) AINN AINP AVDD A NC NC U AK555 CKS/SCL/CCLK CKS/CAD0_IC/CSN CKS0/SDA/CDTI 0 OVF NC 9 8 SDTO/DSDOL R 5 CKS/SCL/CCLK R 5 CKS/CAD0-IC/CSN R 5 CKS0/SDA/CDTI R0 0 OVF R9 5 SDTO/DSDOR R8 5 SDTO/DSDOL C0 0 NC NC TDMIN/DSDOR LRCK/DSDOL 7 TP09 NC ICK/DCLK NC NC TEST MCLK TVDD D VDD8 PDN PW0 PW PW MSN R8 (short) C5 0.05u R7 (short) R 0 R5 0 R 0 R 0 R0 0 R8 0 TP00 C00 00u C0 0.u DCKS/HPFE DP IC PS/CAD0_SP 0 OVFRST/TDM 9 OVFFUNC/TDM0 8 DIF/DSDSEL 7 DIF0/DSDSEL0 TP0 TP0 TP05 TP0 R0 R05 (short) R0 C05 R08 C0 0.05u R0 (short) C0 0.u R5 (short) TP08 R C07 R5 (short) R5 (short) R0 TP R55 (short) R R5 (short) C08 R R 0 C09 open R 0 C 0.u C0 0u R7 C 0.u C.7u R8 R9 0 R0 0 C R 0 R 0 R 0 R 0 AIN-N0 TP0 AIN-P0 TP TEST TP MCLK TP TVDD TP TP5 VDD8 TP PDN TP7 PW0 TP8 PW TP9 PW TP0 MSN TP A A Title <AKD555-> Size Document Number Rev A AK555 Tuesday, August 8, 08 Date: Sheet of 8

47 5 VOP R0.7k D J0 AIN- R00.7k C00 7u C0 0.0u U00 NC -IN IN V- NJM55 NC 8 V OUT 7 NC 5 C0 0.0u C0 7u R0 R open R open R5 open C05 00u AIN(x)/AIN(x) J00 C0 00u AINN open AINP VOP- VOP- R0.k IAS C07 0u C50 00p C08 0.0u R05 0 C n U0 NC NC 8 -IN V 7 IN OUT V- NC 5 NJM55 R07 0 C 0.0u C 0u R09 0 C7 00p AIN-P0 D VIAS R0 0 C 0k R0 R0 C0 0k 0u IAS C0 0.0u VOP- R0.k IAS C09 0u C5 00p C0 0.0u C n U0 NC NC 8 -IN V 7 IN OUT V- NC 5 NJM55 R08 0 C5 0.0u C 0u R0 0 C8 00p AIN-N0 C VOP R.7k J0 AIN- VOP- R.7k C9 7u C0 0.0u U0 NC -IN IN V- NJM55 NC 8 V OUT 7 NC 5 C 0.0u C 7u R R open R open R7 open open C 00u AINP AIN(x)/AIN(x) J0 C5 00u AINN VOP- R.k IAS C 0u C5 00p C7 0.0u R8 0 C0 n U0 NC NC 8 -IN V 7 IN OUT V- NC 5 NJM55 R0 0 C 0.0u C 0u R 0 C 00p AIN-P0 VIAS R9 0 0k R R5 C 0k 0u IAS C 0.0u VOP- R7.k IAS C8 0u C5 00p C9 0.0u C n U05 NC NC 8 -IN V 7 IN OUT V- NC 5 NJM55 R 0 C 0.0u C5 0u R 0 C7 00p AIN-N0 A A 5-7- Title <AKD555-> Size Document Number Rev A Analog Input AIN & AIN Date: Tuesday, August 8, 08 Sheet of 8

48 5 VOP R0 D J0 AIN- R00 C00 C0 U00 NC -IN IN V- NC 8 V OUT 7 NC 5 C0 C0 R0 R open R open R5 open C05 AIN(x)/non(x) J00 C0 open AINP AINN VOP- VOP- R0 IAS C08 C07 C50 R05 C U0 NC NC 8 -IN V 7 IN OUT V- NC 5 R07 C C R09 C7 AIN-P0 D VIAS R0 C R0 R0 C0 IAS C0 VOP- R0 IAS C5 C0 C09 C U0 NC NC 8 -IN V 7 IN OUT V- NC 5 R08 C5 C R0 C8 AIN-N0 C VOP R J0 AIN- VOP- R C9 C0 U0 NC -IN IN V- NC 8 V OUT 7 NC 5 C C R open R open R open R7 open C AINP AIN(x)/non(x) J0 C5 AINN VOP- R IAS C7 C C5 R8 C0 U0 NC NC 8 -IN V 7 IN OUT V- NC 5 R0 R C C C AIN-P0 VIAS R9 R R5 C IAS C VOP- R7 IAS C9 C8 C5 C U05 NC NC 8 -IN V 7 IN OUT V- NC 5 R C C5 R C7 AIN-N0 A A 5-8- Title <AKD555-> Size Document Number Rev A Analog Input AIN & AIN Date: Tuesday, August 8, 08 Sheet of 8

49 5 C0 R00 C0 0.7u 0u C0 0.0u 0k DV D 8 RX 7 RX 5 TEST RX NC RX0 VCOM 0 R 9 AVDD 8 7 INT D IPS0/RX INT0 DV NC OCKS0/CSN/CAD0 5 OCKS0-T H SW00 OCKS-T L 5 DIF0/RX5 OCKS/CCLK/SCL TEST CM/CDTI/SDA DV C DIF DIF DIF0 R0 7k OCKS OCKS0 R0 7k R0 7k R0 7k R05 7k OCKS0-T OCKS-T DIF/RX DIF/RX7 IPS/IIC P/SN U AK8A CM0/CDTO/CAD XTI PDN JP0 0 EXT XTL EXTMCLK-SEL XTO 9 DAUX 8 C08 X00.88MHz C09 DAUX-8A-T 5p 5p PDN0 EXT-MCLK-T X00 Frequency Check ->.88MHz pin Socket (AK8 Xtal) DAUX-8A-T C 0 XTL0 MCKO 7 XTL ICK ICK-8A-T ICK-8A-T VIN/GP0 TVDD NC/GP TX0/GP TX/GP OUT/GP COUT/GP5 UOUT/GP 5 VOUT/GP7 DVDD MCKO 0 LRCK SDTO 5 LRCK-8A-T LRCK-8A-T C0 0.0u C0 0.0u MCLK-8A-T MCLK-8A-T DV C05 0u C07 0u PORT00 TX-OPT IN VCC GND TP00 TX-OPT C00 0.0u DV JP00 OPT COAX TXDATA-SEL A T00 DA-0F A J00 TX-COAX 5 5 C0 0.0u R07 50 R Title <AKD555-> Size Document Number Rev A AK8A-DIT Date: Tuesday, August 8, 08 Sheet of 8

50 5 D D DV R50 00k C u TVDD PCA90DP U500 C R500 0k R50 0k R50 0k R5 0k R SCL/CCLK EN VREF SCL GND VREF SCL C5 0.0u SCL/CCLK R508 R509 0k 0k SCL/CCLK C R50 70 SDA/CDTI 5 SDA SDA SDA/CDTI SDA/CDTI CSN SCL/CCLK SDA/CDTI R507 00k C50 0.0u PCA90DP U50 TVDD PORT CSN CSN-0PIN CCLK/SCLSCL/CCLK-0PIN CDTI/SDA SDA/CDTI-0PIN R CSN EN VREF SCL SDA GND VREF SCL SDA C5 0.0u CSN R50 R5 0k 0k CSN 0pin-CTRL A A Title <AKD555-> Size Document Number Rev A PC-IF Date: Tuesday, August 8, 08 Sheet 5 of 8

51 5 ICK-8A-T PORT800-ICK PORT05 DIT PORT GND PORT07 ICK-PHASE THR INV R00 0 ICK-T D C PORT00 MCLK ICK LRCK SDTO SDTO PCM-PORT PORT0 TDMIN-PORT TDMIN PORT800-MCLK PORT800-ICK PORT800-LRCK PORT80-SDTO PORT80-SDTO PORT80-TDMIN LRCK-8A-T DAUX-8A-T MCLK-8A-T PORT800-MCLK EXT-T 5 J00 R 5 JP00 EXT-T PORT800-LRCK PORT80-SDTO PORT80-SDTO PORT80-TDMIN ICK-SEL ICK-T-THR ICK-T-INV PORT0 DIT PORT GND LRCK-SEL SDTO-SEL DIT R 0 R 0 R PORT09 TDMIN-SEL PORT PORT0 MCLK-SEL DIT PORT EXT GND PORT08 SDTO-SEL SDTO SDTO R0 0 LRCK-T R0 0 SDTO-T R0 SDTO-T R0 0 TDMIN-T R05 0 MCLK-T R 0 EXT-MCLK-T DV K A L SW00 PDN D00 HSU9 H H L R5 0k 5 0 TEST PW0 PW PW MSN DV SW00-PDN C00 0.0u CAD0-SPI CAD0-IC CAD L SW0 PDN-T K A H TVDD SW0 SW DIP-8 D0 HSU9 CAD CAD0-IC CAD0-SPI MSN PW PW PW0 TEST R 0k SW0-PDN SW00-PDN C0 0.0u CAD CAD0-IC CAD0-SPI MSN PW PW PW0 TEST H L 5 0 CKS0 CKS CKS CKS DIF0/DSDSEL0 U00 A VCC Y A A Y 5 Y 5A A 5Y 0 7 Y A 9 GND Y 8 7HC 9 DIF/DSDSEL SLOW/DCK SD/PMOD TVDD SW0 SW DIP-8 ICK-T-INV ICK-T-THR R7 SW0-PDN PDN0 PDN0 k OVF- LE00 OVF SD/PMOD SLOW/DCK SD/PMOD DIF/DSDSEL SLOW/DCK DIF0/DSDSEL0 DIF/DSDSEL CKS DIF0/DSDSEL0 CKS CKS CKS CKS CKS0 CKS CKS0 DV C0 0.0u D C PORT0 DCLK DSDOL DSDOR DSDOL DSDOR DSD-PORT PORT80-DCLK PORT80-DSDOL PORT80-DSDOR PORT80-DSDOL PORT80-DSDOR PORT80-DCLK PORT80-DSDOL PORT80-DSDOR PORT80-DSDOL PORT80-DSDOR R0 0 R07 0 R08 0 R09 0 R0 0 DCLK-T DSDOL-T DSDOR-T DSDOL-T DSDOR-T R8 7k R9 7k R0 7k 5 0 TVDD SW0 SW DIP-8 R 7k R 7k R 7k 9 R 7k R 7k R 7k R5 7k R7 7k R8 7k R9 7k R0 7k R 7k R 7k A Open EXT-T 5 J0 R Open CLKIN JP0 EXT-T DV Open C0 Open U0 0 CLK Q Q RST Q Q Q5 Q Q7 Q8 Q9 Q0 8 VD Q DGND Q Open 9 IN/ 7 IN/ IN/8 5 IN/ IN/ IN/ IN/8 IN/5 IN/5 IN/0 5 IN/08 IN/09 Open PORT USER-CLK Open PORT CLK-SEL Open EXT-T 5 J0 R Open CLKIN JP0 EXT-T DV Open C0 Open U0 0 CLK Q Q RST Q Q Q5 Q Q7 Q8 Q9 Q0 8 VD Q DGND Q Open 9 IN/ 7 IN/ IN/8 5 IN/ IN/ IN/ IN/8 IN/5 IN/5 IN/0 5 IN/08 IN/09 Open PORT USER-CLK Open PORT CLK-SEL LDOE TEST TDM0 TDM R 7k R5 7k PS IC R 7k DP HPFE/DCKS R7 7k R8 7k R9 7k R0 7k HPFE/DCKS DP HPFE/DCKS IC DP PS IC TDM PS TDM0 TDM/OVFRST TEST TDM0/OVFFUNC LDOE TEST LDOE R 7k A 5-5- Title <AKD555-> Size Document Number Rev A LOGIC Date: Tuesday, August 8, 08 Sheet of 8

52 5 D ICK-T LRCK-T R700 5 R70 5 R70 0 R70 0 MSN-DP-PP TVDD C u DV -> TVDD U700 5 A Y 9 A Y 8 A Y A Y OE 0 OE OE OE 7 VCC GND 7VCX5 TVDD -> DV U70 Y A 5 8 Y A 9 Y A Y A OE OE OE 0 OE VCC GND 7 7VCX5 R70 5 R70 0 R707 0 MSN-DP-NP DV C70 0.0u U709 IN OUT GND NFLSP70 R705 5 ICK/DCLK LRCK/DSDOL ICK/DCLK LRCK/DSDOL TDMIN-T SDTO-T SDTO-T R7 5 R75 R70 0 R7 0 R7 0 R7 0 DP0-P TVDD C70 0.0u TVDD -> DV U70 Y A 5 8 Y A 9 Y A Y A OE OE OE 0 OE 7VCX5 DV -> TVDD U70 5 A Y 9 A Y 8 A Y A Y OE 0 OE OE OE 7 VCC GND VCC GND 7 7VCX5 R78 0 R79 0 DP0-P DV C70 0.0u R750 SDTO/DSDOL R7 0 SDTO/DSDOR R77 R7 0 (short) TDMIN/DSDOR SDTO/DSDOL SDTO/DSDOR TDMIN/DSDOR D C MCLK-T PDN0 R708 5 R7 5 R709 0 R70 0 TVDD C70 0.0u DV -> TVDD U70 5 A Y 9 A Y 8 A Y A Y OE 0 OE OE OE 7 VCC GND 7VCX5 R7 5 U70 IN OUT GND NFLSP70 R7 0 MCLK PDN DSDOL-T DSDOR-T DSDOL-T DSDOR-T R75 5 R7 5 R77 5 R78 5 DCLK-T R79 5 DV U705 (uffer) 0pin= C705 0pin=DV 0.0u for U705 7VCX5 TVDD -> DV U Y A Y A 5 Y A 5 Y A Y5 A5 7 Y A 8 Y7 A7 9 Y8 A8 7VCX5 G 9 G R7 0 R75 0 R7 0 DP0-N DP0-N R75 R75 LRCK/DSDOL R70 0 TDMIN/DSDOR R7 0 SDTO/DSDOL R7 SDTO/DSDOR R7 R77 0 (short) (short) ICK/DCLK LRCK/DSDOL TDMIN/DSDOR SDTO/DSDOL SDTO/DSDOR ICK/DCLK C DP MSN OVF R78 0 R79 0 R70 5 R7 0 DV C70 0.0u TVDD -> DV U70 5 A Y 9 A Y 8 A Y A Y OE 0 OE OE OE 7 VCC GND 7VCX5 R7 5 R7 5 R7 0 OVF- DP0 MSN0 U707 A 5 A 9 A A 5A A 7VCX Y Y Y Y 8 5Y 0 Y U707 (INV) 7pin= pin=dv DV C u DP0-P MSN0-P DP0-N MSN0-N for U707 7VCX CAD0-IC CSN CAD0-IC CSN CKS0 CKS0 CKS0 SDA/CDTI SDA/CDTI SDA/CDTI JP700 CKS CKS CAD0-IC CKS CAD0-IC/CSN CAD0-IC/CSN CSN JP70 JP70 PS-SEL CKS CKS CKS SCL/CCLK SCL/CCLK SCL/CCLK JP70 PS-SEL PS-SEL PS-SEL CKS0/SDA/CDTI CKS/CAD0-IC/CSN CKS/SCL/CCLK A MSN0-N DP0-N MSN0-P DP0-N R75 0 R7 0 R DV C u U708 A 5 A 9 0 A A 7VCX00 Y Y Y 8 Y U708 (NAND) 7pin= pin=dv MSN-DP-PP MSN-DP-NP CKS CAD PS CAD0-SPI CKS CKS CAD CAD JP70 PS PS CAD0-SPI CAD0-SPI JP705 PS-SEL5 PS-SEL CKS/CAD PS/CAD0-SPI A for U708 7VCX Title <AKD555-> Size Document Number Rev A LOGIC Date: Tuesday, August 8, 08 Sheet 7 of 8

53 5 5V D J800 5V J80-5V J80 5V -5V C800 7u C80 0.0u 5V-->5V T NJM78M05FA IN GND OUT L800 0 C80 0.0u C80 7u J80 AVDD R807 0 R808 open R800 0 VOP AVDD D R809 0 R80 0 VIAS -5V C8 7u J805 VIAS R80 open C80 7u L80 0 VOP- C85 7u 5V 5V-->5V T NJM78M05FA C C805 7u C80 0.0u IN GND OUT C u C808 7u J809 VCC R8 0 R8 open R80 0 R80 0 VCC VCC C C809 7u 5V-->.V T LT9AEST-. IN GND OUT.V.8V C8 7u JP800 TVDD-VSEL J80 TVDD JP80 TVDD-SEL REG R80 0 JACK TP800 TVDD TVDD VCC C80 0.0u C8 0.0u C8 7u C8 7u C85 0.0u 5V-->.8V T LT9AEST-.8 IN GND OUT C8 0.0u C87 7u C8 7u J807 VDD8 JP80 VDD8-SEL REG R805 0 JACK TP80 VDD8 VDD8 C88 7u A C80 0.0u 5V-->.V T5 LT9AEST-. IN GND OUT C8 0.0u C8 7u J808 D.V JP80 DV-SEL REG R80 0 JACK TP80 DV DV A VCC C89 7u 5-5- C8 7u Title <AKD555-> Size Document Number Rev A Power Supply Date: Tuesday, August 8, 08 Sheet 8 of 8

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