Universal Class D UCD 150W IP Cell. Switch Driver. Switch Driver

Transcription

1 Universal Class D UCD 50W IP Cell Features Ultrahigh-Fidelity Sound Extremely Low Output Impedance Large, Load-Independent Bandwidth Low Noise and Distortion All-Discrete Construction Fully Passive Signal path / No Analog Amplification. Differential Input Pop-Free Stop Mode Short-Circuit Detection UCD is a class D amplifier circuit designed to unite price, performance and versatility requirements at a point not seen before in the field of audio power amplifiers. A new control/feedback system is used to obtain low output impedance and low distortion, with all active components in the signal path operating in onoff mode (i.e. without linear amplification), insuring maximum sonic transparency. The all-discrete construction of the circuit results in very high quality. Applications Home Theatre Systems Active Loudspeakers Miniature Component Systems. Block Diagram In+ In- Control Circuit Switch Driver Switch Driver Out

2 2. Specifications 2.. Absolute Maximum Ratings Property Symbol Limit Unit Conditions/Notes Power supply voltage VDD-VSS 20 V Output current IO 6 A (rms) Continuous output power PO,C 20 W Tamb=40ºC 2.2. Performance specifications Normal Operating Conditions: Vdd-Vss=90V. Measurement Bandwidth=20k Property Symbol Min Typ Max Unit Conditions/Notes Rated output power Pr W ZL=8Ω, THD<% W ZL=6Ω, THD<% W ZL=6Ω, THD=0% W ZL=4Ω, THD<% Distortion and noise THD % 0W, 20-20k N Signal-to-noise ratio SNR db Unwtd DC offset VDC -50m - +50m V Frequency Response BW k - +0/-3dB (3Ω<ZL< ) Power Bandwidth PBW k - -3dB Output impedance ZO Ω DC-k Ω 0k Ω 20k Idle losses P W Power stage and coil only Efficiency η % 00W, 6Ω Gain AV V/V Input impedance Zi.7k.8k.9k Ω Inverting input 9.5k 0k 0.5k Noninverting input Common-Mode Rejection CMRR 30 db Power supply ripple PSRR db rejection Idle switching rate fsw,0 420k 440k 460k Frequency modulation fsw fsw,0 (-M) 4 M=Modulation Index. -<M< 2.3. Construction Technology Preferred construction is FR4 two-layer board material with 35µ (oz/ft 2 ) copper. All SMDs are mounted on the bottom side for wave soldering Dimensions (one mono-channel cell) Width: 50mm Depth: 60mm Height: 40mm (includes PCB and lead-outs) Distance between pin 6 of JP and pin of JP2: 0.2mm

3 3. Connections Hypex Electronics The demonstration boards have two male JST XH connectors for mating with JQ counterparts for PCB mounting or female XH cable connectors (see JP: Power and Control Pin Name Description /ENA Enable line. Pull to GND to operate amplifier. Should be driven by an open collector output. This line floats to +VB in mute position (47kΩ). Allow s between power-up and driving /ENA for pop-free operation. 2 VDR Supply for MOS gate drivers. Internally regulated to -VB+0V. Connect to GND or to -VB+5V. 3 +VB Positive power supply rail. Nominally +45V. 4 GND Ground. Power supply ground in case a star grounding scheme is employed. 5 -VB Negative power supply rail. Nominally 45V. 6 /ERR Error output. This line is pulled down to VB when an overcurrent in either power MOSFET is detected. External control circuitry should respond by releasing /ENA for one second. Response time of this external circuit must be below 50µs JP2: Audio I/O Pin Name Description IN+ Noninverting audio input 2 IN- Inverting audio input 3,4,5 GND Output ground 6,7,8 OUT Speaker output 4. Typical Performance Graphs Measurement conditions: Test lead set as in section 5.. Unregulated power supply of +/-45V with 2x4700mF storage. Load impedance=6w. 4.. Frequency Response at, 6 and 3W d B k 2k 5k 0k 20k 50k 00k Frequency response is a st order low-pass characteristic with a corner frequency of 50k and is independent of load. All fully digital amplifiers and most analog class D amplifiers exhibit a frequency response which can deviate by as much as 0dB from the nominal-load response under common load conditions.

4 4.2. Output Impedance O h m s m 200m 00m 50m 20m 0m k 2k 5k 0k 20k 50k 00k The upper trace shows the output impedance of the output filter, input (=switching node) shorted to ground. This is typical of the output impedance found on fully digital amplifiers and on analog class D s without post-filter feedback. Clearly visible are the parallel resonant frequency and the DC resistance of the coil. The bottom trace is the output impedance of the same circuit, but with the amplifier operating. It is very evident that the feedback loop has full control over the output, with the resonant peak completely gone and the DC resistance lowered. The rise with frequency corresponds with an inductance of 560nH, much lower than the inductances commonly inserted at the output of linear amplifiers to decouple capacitive loads THD versus Power at k % m 2m 5m 0m 20m 50m 00m 500m W Measurement filter=aes7 (20k).

5 4.4. THD versus Frequency at, 30, 70 and 00W % W 30W W 70W k 2k 5k 0k 20k Measurement filter=30k. THD is essentially independent of frequency. Minor thermal modulation is evident at lower frequencies Alternative Modulator Settings The unusual flexibility of UCD allows different optimizations of the modulator/control circuit. Shown below is a plot of the same circuit board, where only the passive control network is modified. One setting offers best THD at moderate power levels (typical listening levels) and mild clipping behaviour, whereas the other setting yields better linearity up to full rated power % m 2m 5m 0m 20m 50m 00m 500m W

6 4.6. Noise Floor FFT d B r A k 4k 6k 8k 0k 2k 4k 6k 8k 20k Shown is a 6k point FFT (at 44.k) of the noise floor of an UCD module (inputs shorted) with 0dB=00W. At a noise gain of + A V =5.55 this noise level corresponds to an input voltage noise of 20nV/ at the comparator input. Indeed, only the input pair contributes to noise even the /f noise corner is visible. 5. Application notes 5.. Minimal Test Connection Performance and EMC measurements can be carried out with cable connections directly made to the module. Refer to 5.2 for proper connections for listening tests. Sonic performance using this minimal test connection will be compromised. To AP test set generator out (low-z output setting) 2 3 To AP analyzer input 3 2 IN- IN+ GND GND GND OUT OUT OUT Test load ENA VDR VB+ GND VB- ERR To PSU 2x2200u (if not included on PSU)

7 5.2. Preferred audio connections R A R A R B R A A V R B A V A =A (2 +) V,TOT V R A R B A =A ( +) V,TOT V R A R B The traditional star ground concept, while offering a solution to LF ground loops, has been proven to be unworkable in environments where high-frequency performance is also an issue. This is the case with applications containg digital and switching power circuits, and with all applications when irradiation sensitivity is concerned. The physical loops that are inevitably created when a signal and its return follow different paths, are radiating and receiving antennae for (electro-) magnetic fields. These HF problems are readily solved by using an unbroken ground plane, but this again potentially have the problems addressed by star-grounding. For this reason, the UCD cell is equipped with differential inputs. These are used either to receive the input signal with reference to the local ground of the preamplifier circuit (right), or to build a fully balanced input in instrumentation amplifier fashion (left). Even if the input is unbalanced, the balanced circuit shown left offers a significant sonic improvement over the unbalanced buffer/preamp circuit. Suitable op-amps are, depending on budgetary and sonic requirements, OPA627, OPAx34 and TL07x, as well as many discrete preamplifier circuits, provided they have a low output impedance EMC and AM Tuner Compatibility Even without shielding the circuit, together with its board lay-out, meets most common legal radiation limits (including EN5503/CISPR3, FCC part 5 class B) by a generous margin. In a properly designed application UCD will not interfere with FM radio reception. In audio systems comprising an AM tuner, interference-free reception requires the use of multiple fixed switching frequencies. Under normal condition, switching frequency is set by the control loop characteristics and is variable with modulation. The switching frequency automatically synchronises to a reference clock mixed with the input signal. The frequency can then be chosen such that no harmonics are near the tuning frequency or its mirror. In practice, two frequency settings suffice. While the audio performance in frequency-locked mode is more than sufficient for AM radio, the amplifier is best left unlocked in other conditions Mutual Interference Frequently with the application of unsynchronised class D amplifiers, interference from one channel into another is a concern. The effect shows up as whistles (tones) corresponding to the frequency difference of the channels involved, and harmonics thereof. In the design of UCD, special care has been taken to avoid these problems. First and foremost, radiation and conducted interference are kept to a minimum by onboard measures. Secondly, the input stage supports a differential input that is very insensitive to HF noise. Below is a compound noise FFT of all six channels of an application board using the demonstration modules shown on the front page. This board does not contain any specific EMC measures. Nearly no disturbance component exceeds the 20dB limit. In any real application this means the disturbances are well below the noise floor.

8 d B -80 r k 4k 6k 8k 0k 2k 4k 6k 8k 20k 5.5. Adapted Versions This data sheet outlines the properties of a specific prototype implementation. Being a discrete circuit UCD can be customised to suit specific customer requirements. This is readily done during the industrialisation phase of the application. Relatively minor circuit modifications are: Lower power versions at reduced cost Added clock input for AM mode sync Cost optimisation by using more tightly specified passives Higher audio performance through better gate drive parts Different sonic preference (selected passive components) Major redesigns open up a wider range of options. This includes high-power versions (200W kw), fullbridge versions for single supply operation and higher power, and IC integration.