FAN102 Primary-Side-Control PWM Controller

Transcription

1 FAN0 PrimarySideControl PWM Controller Features ConstantVoltage (CV) and ConstantCurrent (CC) Control without SecondaryFeedback Circuitry Green Mode: Frequency Reduction at Light Load Fixed PWM Frequency at 4kHz with Frequency Hopping to Reduce EMI Cable Voltage Drop Compensation in CV Mode Low Startup Current: 0μA Low Operating Current: 3.5mA PeakCurrentMode Control in CV Mode CyclebyCycle Current Limiting V DD OverVoltage Protection with AutoRestart V DD UnderVoltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 8V Fixed OverTemperature Protection with Auto Restart SOP8 Package Available Description April 009 The primaryside PWM controller significantly simplifies power supply design that requires CV and CC regulation capabilities. The FAN0 controls the output voltage and current precisely with the information in the primary side of the power supply, not only removing the output current sensing loss, but eliminating all secondary feedback circuitry. The greenmode function with a low startup current (0µA) maximizes the lightload efficiency so the power supply can meet stringent standby power regulations. Compared with a conventional secondaryside regulation approach, the FAN0 can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. A typical output CV/CC characteristic envelope is shown in Figure. Applications Battery Chargers for Cellular Phones, Cordless Phones, PDA, Digital Cameras, Power Tools Replaces Linear Transformer and RCC SMPS Offline High Brightness (HB) LED Drivers Figure. Typical Output VI Characteristic Ordering Information Part Number Operating Temperature Range Eco Status Package Packing Method FAN0MY 40 C to 05 C Green 8Lead, Small Outline Package (SOP8) Tape & Reel For Fairchild s definition of Eco Status, please visit: FAN0 Rev..0.3

2 Application Diagram R COMR C COMR C COMI R COMI Bridge Rectifier Diode AC Line C DL CS COMR 3 COMI 4 COMV C COMV R COMV V DL FAN0 GATE VDD SGND VS R START R SN C SN D SN D DD C DD R GATE R CS C S N P N A R S R S C SN R SN D R N S C O I O V O Figure. Typical Application Internal Block Diagram VDD 7 6V/5V Internal Bias V DD Good 8V OTP S Q R Q Protection Reset SoftDriver V DD 8 Gate OSC with Frequency Hopping PWM Comparator PWM Comparator S R Q Q.3V PWM Comparator Slope Compensation LeadingEdge Blanking CS I O Estimator GND 6 Green Mode Controller EA_V EA_I.5V Cable Drop Compensation Temperature Compensation t DIS Detector V O Estimator Brownout Protection 5 VS 3 COMI 4 COMV COMR Figure 3. Functional Block Diagram FAN0 Rev..0.3

3 Marking Information Pin Configuration Figure 4. Top Mark F Fairchild Logo Z Plant Code X Digit Year Code Y Digit Week Code TT Digit Die Run Code T Package Type (M=SOP) P Z: Pb Free, Y: Green Package M Manufacture Flow Code Figure 5. Pin Configuration Pin Definitions Pin # Name Description CS COMR 3 COMI 4 COMV Current Sense. This pin connects a currentsense resistor to sense the MOSFET current for peakcurrentmode control in CV mode and provides for outputcurrent regulation in CC mode. Cable Compensation. This pin is connects a capacitor between COMR and GND for compensation voltage drop due to output cable loss in CV mode. Constant Current Loop Compensation. This pin is connects a capacitor and a resistor between COMI and GND for compensation current loop gain. Constant Voltage Loop Compensation. This pin is connects a capacitor and a resistor between COMV and GND for compensation voltage loop gain. 5 VS Voltage Sense. This pin detects the output voltage information and discharges time base on voltage of auxiliary winding. This pin connects two divider resistors and one capacitor. 6 GND Ground. 7 VDD 8 GATE Power Supply. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external V DD capacitor (typically 0μF). The threshold voltages for startup and turnoff are 6V and 5V, respectively. PWM Signal Output. This pin outputs PWM signal and includes the internal totempole output driver to drive the external power MOSFET. The clamped gate output voltage is 8V. FAN0 Rev

4 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V DD DC Supply Voltage (,) 30 V V VS VS Pin Input Voltage V V CS CS Pin Input Voltage V V COMV Voltage Error Amplifier Output Voltage V V COMI Voltage Error Amplifier Output Voltage V P D Power Dissipation (T A<50 C) 660 mw Θ JA Thermal Resistance (JunctiontoAir) 50 C /W Θ JC Thermal Resistance (JunctiontoCase) 39 C /W T J Operating Junction Temperature 50 C T STG Storage Temperature Range C T L Lead Temperature (Wave Soldering or IR, 0 Seconds) 60 C ESD Electrostatic Discharge Capability, Human Body Model, JEDEC JESD_A4 4.5 kv Electrostatic Discharge Capability, Charged Device Model, JEDEC JESD_C0 50 V Notes:. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Typ. Max. Unit T A Operating Ambient Temperature C FAN0 Rev

5 Electrical Characteristics V DD=5V and T A=5 C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units V DD Section V OP Continuously Operating Voltage 5 V V DDON TurnOn Threshold Voltage V V DDOFF TurnOff Threshold Voltage V I DDOP Operating Current V DD=0V, f s=f OSC, V VS=V, V CS=3V, C L=nF ma I DDST Startup Current 0< V DD < V DDON0.6V μa I DDGREEN V DDOVP t DVDDOVP Oscillator Section GreenMode Operating Supply Current V DD OverVoltage Protection Level V DD OverVoltage Protection Debounce Time f OSC Frequency Frequency Hopping Range V DD=0V, V VS=.7V f S=f OSCNMIN, V CS=0V C L=nF, V COMV=0V ma V CS=3V, V VS=.3V V f s=f OSC, V VS=.3V μs Center Frequency T A=5 C T A=5 C ±.8 ±.6 ±3.6 t FHR Frequency Hopping Period T A=5 C 3 ms f OSCNMIN Minimum Frequency at No Load V VS=.7V, V COMV=0V 550 Hz f OSCCMMIN Minimum Frequency at CCM V VS=.3V, V CS=0.5V 0 KHz KHz f DV f DT Frequency Variation vs. V DD Deviation Frequency Variation vs. Temperature Deviation VoltageSense Section I VSUVP Sink Current for Brownout Protection V DD=0V to 5V 5 % T A=40 C to 05 C 5 % R VS=0KΩ 80 μa I tc IC Compensation Bias Current 9.5 μa V BIASCOMV Adaptive Bias Voltage Dominated by V COMV CurrentSense Section t PD t MINN Propagation Delay to GATE Output Minimum On Time at No Load V COMV=0V, T A=5 C, R VS=0KΩ V VS=0.8V, R S=KΩ, V COMV=V.4 V ns 00 ns t MINCC Minimum On Time in CC Mode V VS=0V, V COMV=V 400 ns V TH Threshold Voltage for Current Limit.3 V Continued on the following page FAN0 Rev

6 Electrical Characteristics V DD=5V and T A=5 C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VoltageErrorAmplifier Section V VR Reference Voltage V V N V G Green Mode Starting Voltage on COMV Pin Green Mode Ending Voltage on COMV Pin f S=f OSCKHz, V VS=.3V.8 V f S=KHz 0.8 V I VSINK Output Sink Current V VS=3V, V COMV=.5V 90 μa I VSOURCE Output Source Current V VS=V, V COMV=.5V 90 μa V VHGH Output High Voltage V VS=.3V 4.5 V CurrentErrorAmplifier Section V IR Reference Voltage V I ISINK Output Sink Current V CS=3V, V COMI=.5V 55 μa I ISOURCE Output Source Current V CS=0V, V COMI=.5V 55 μa V IHGH Output High Voltage V CS=0V 4.5 V Cable Compensation Section V COMR Gate Section Variation Test Voltage on COMR Pin for Cable Compensation R COMR=00KΩ V DCY MAX Maximum Duty Cycle 75 % V OL Output Voltage LOW V DD=0V, I O=0mA.5 V V OH Output Voltage HIGH V DD=8V, I O=mA 5 V V OH_MIN Output Voltage HIGH V DD=5.5V, I O=mA 4 V t r Rising Time V DD=0V, C L=nF ns t f Falling Time V DD=0V, C L=nF ns V CLAMP Output Clamp Voltage V DD=5V 5 8 V OverTemperatureProtection Section T OTP Threshold Temperature for (3) OTP 40 C Note: 3. When overtemperature protection is activated, the power system enters auto restart mode and output is disabled. FAN0 Rev

7 Typical Performance Characteristics VDDON (V) Figure TurnOn Threshold Voltage (V DDON) VDDOFF (V) Figure TurnOff Threshold Voltage (V DDOFF) IDDOP (ma) fosc (KHz) Figure 8. Operating Current (I DDOP) Figure 9. Center Frequency (f OSC) VVR (V) VIR (V) Figure 0. Reference Voltage (V VR) Figure. Reference Voltage (V IR) FAN0 Rev

8 Typical Performance Characteristics foscnmin (Hz) Figure. Minimum Frequency at No Load (f OSCNMIN) 30 5 fosccmmin (KHz) Figure 3. Minimum Frequency at CCM (f OSCCMMIN) SG (KHz/V) tminn (ns) Figure 4. Green Mode Frequency Decreasing Rate (S G) Figure 5. Minimum On Time at No Load (t MINN) 3 VN (V) VG (V) Figure 6. Green Mode Starting Voltage on COMV Pin (V N) Figure 7. Green Mode Ending Voltage on COMV Pin (V G) FAN0 Rev

9 Typical Performance Characteristics IVSINK (µa) Figure 8. Output Sink Current (I VSINK) IVSOURCE (µa) Figure 9. Output Source Current (I VSOURCE) IISINK (µa) IISOURCE (µa) Figure 0. Output Sink Current (I ISINK) Figure. Output Source Current (I ISOURCE) VCOMR (V). 0.8 DCYMAX (%) Figure. Variation Test Voltage on COMR Pin for Cable Compensation (V COMR) Figure 3. Maximum Duty Cycle (DCY MAX) FAN0 Rev

10 Functional Description Figure 4 shows the basic circuit diagram of primaryside regulated flyback converter with typical waveforms shown in Figure 5. Generally, discontinuous conduction mode (DCM) operation is preferred for primaryside regulation since it allows better output regulation. The operation principles of DCM flyback converter are as follows: During the MOSFET ON time (t ON), input voltage (V DL) is applied across the primaryside inductor (L m). Then MOSFET current (I ds) increases linearly from zero to the peak value (I pk). During this time, the energy is drawn from the input and stored in the inductor. When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to turn on. While the diode is conducting, the output voltage (V o), together with diode forward voltage drop (V F), are applied across the secondaryside inductor (L m N s / N p ) and the diode current (I D) decreases linearly from the peak value (I pk N p/n s) to zero. At the end of inductor current discharge time (t DIS), all the energy stored in the inductor has been delivered to the output. When the diode current reaches zero, the transformer auxiliary winding voltage (V W) begins to oscillate by the resonance between the primaryside inductor (L m) and the effective capacitor loaded across MOSFET. During the inductor current discharge time, the sum of output voltage and diode forward voltage drop is reflected to the auxiliary winding side as (V OV F) N A/N S. Since the diode forward voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero. By sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate error voltage (V COMV), which determines the duty cycle of the MOSFET in CV mode. Meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time since output current is same as average of the diode current in steady state. The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (t DIS) and switching period (t S). The output information is compared with internal precise reference to generate error voltage (V COMI), which determines the duty cycle of the MOSFET in CC mode. Among the two error voltages, V COMV and V COMI, the smaller actually determines the duty cycle. During constant voltage regulation mode, V COMV determines the duty cycle while V COMI is saturated to high. During constant current regulation mode, V COMI determines the duty cycle while V COMV is saturated to HIGH. V AC Gate V COMI Ref PWM Control V COMV EA_I I o Estimator t DIS Detector V o Estimator EA_V Ref PrimarySide Regulation Controller V DL CS V S V DD R S R S R CS N p :N s I D I o D L m V O V F I ds N A V w Figure 4. Simplified PSR Flyback Converter Circuit I ds (MOSFET DraintoSource Current) I D (Diode Current) V W (Auxiliary Winding Voltage) N VF N A S t ON I pk t S I pk N VO N t DIS NP N A S I Davg. = I Figure 5. Key Waveforms of DCM Flyback Converter S o L O A D FAN0 Rev

11 Cable Voltage Drop Compensation When it comes to cellular phone charger applications, the actual battery is located at the end of cable, which causes typically several percent of voltage drop on the actual battery voltage. FAN0 has a programmable cable voltage drop compensation, which provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of voltage regulation error amplifier. The amount of compensation is programmed by the resistor on the COMR pin. The relationship between the amount of compensation and COMR resistor is shown in Figure 6. Compensation Percentage (%) Switching Frequen cy 4kHz 550Hz Deep Green Mode 0.8V Green Mode.8V Normal Mode V COMV Figure 7. Switching Frequency in Green Mode Frequency Hopping EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FAN0 has an internal frequency hopping circuit that changes the switching frequency between 39.4kHz and 44.6kHz with a period of 3ms, as shown in Figure 8. Gate Drive Signal R COMR (k ) Figure 6. Cable Voltage Drop Compensation t s Temperature Compensation Builtin temperature compensation provides constant voltage regulation over a wide range of temperature variation. This internal compensation current compensates the forwardvoltage drop variation of the secondaryside rectifier diode. GreenMode Operation The FAN0 uses voltage regulation error amplifier output (V COMV) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 7, such that the switching frequency decreases as load decreases. In heavy load conditions, the switching frequency is fixed at 4KHz. Once V COMV decreases below.8v, the PWM frequency starts to linearly decrease from 4KHz to 550Hz to reduce the switching losses. As V COMV decreases below 0.8V, the switching frequency is fixed at 550Hz and FAN0 enters deep green mode, where the operating current reduces to ma, further reducing the standby power consumption. 44.6kHz 4.0kHz 39.4kHz t s t s f s 44.6kHz 3ms Figure 8. Frequency Hopping t FAN0 Rev..0.3

12 LeadingEdge Blanking (LEB) At the instant the MOSFET is turned on, a highcurrent spike occurs through the MOSFET, caused by primaryside capacitance and secondaryside rectifier reverse recovery. Excessive voltage across the R CS resistor can lead to premature turnoff of MOSFET. FAN0 employs an internal leadingedge blanking (LEB) circuit. To inhibit the PWM comparator for a short time after the MOSFET is turned on. Thus, external RC filtering is not required. Startup Figure 9 shows the typical startup circuit and transformer auxiliary winding for a FAN0 application. Before FAN0 begins switching, it consumes only startup current (typically 0µA) and the current supplied through the startup resistor charges the V DD capacitor (C DD). When V DD reaches turnon voltage of 6V (V DD ON), FAN0 begins switching and the current consumed by FAN0 increases to 3.5mA. Then, the power required for FAN0 is supplied from the transformer auxiliary winding. The large hysteresis of V DD provides more holdup time, which allows using a small capacitor for V DD. operation. In this manner, the autorestart alternately enables and disables the switching of the MOSFET until the fault condition is eliminated (see Figure 30 ). V DS V DD 6V 5V 3.5mA 0µA Power On Operating Current Fault Occurs Fault Removed AC Line 3 4 CS COMR COMI COMV C DL FAN0 Protections GATE 8 7 VDD 6 SGND 5 VS V DL R STAR T C DD D DD Figure 9. Startup Circuit The FAN0 has several selfprotective functions, such as OverVoltage Protection (OVP), OverTemperature Protection (OTP) and brownout protection. All the protections are implemented as autorestart mode. Once the fault condition occurs, switching is terminated and the MOSFET remains off. This causes V DD to fall. When V DD reaches the V DD turnoff voltage of 5V, the current consumed by FAN0 reduces to the startup current (typically 0µA) and the current supplied startup resistor charges the V DD capacitor. When V DD reaches the turnon voltage of 6V, FAN0 resumes normal Np N A R S R S Normal Fault Normal Operation Situation Operation Figure 30. AutoRestart Operation V DD OverVoltage Protection (OVP) V DD overvoltage protection prevents damage from overvoltage conditions. If the V DD voltage exceeds 8V by open feedback condition, OVP is triggered. The OVP has a debounce time (typcal 50µs) to prevent false trigger by switching noise. It also protects other switching devices from over voltage. OverTemperature Protection (OTP) A builtin temperaturesensing circuit shuts down PWM output if the junction temperature exceeds 40 C. Brownout Protection FAN0 detects the line voltage using auxiliary winding voltage since the auxiliary winding voltage reflects the input voltage when the MOSFET is turned on. The VS pin is clamped at.5v while the MOSFET is turned on and brownout protection is triggered if the current out of the VS pin is less than I VSUVP (typical 80µA) during the MOSFET conduction. PulsebyPulse Current Limit When the sensing voltage across the current sense resistor exceeds the internal threshold of.4v, the MOSFET is turned off for the remainder of switching cycle. In normal operation, the pulsebypulse current limit is not triggered since the peak current is limited by the control loop. FAN0 Rev..0.3

13 Typical Application Circuit (PrimarySide Regulated Flyback Charger) Application Fairchild Devices Input Voltage Range Output Cell Phone Charger FAN0 90~65V AC 5V/0.78A (3.9W) Features High efficiency (>68% at full load) meeting Energy Star SM V.0 and CEC regulation with enough margin Low standby power consumption (Pin=0.087W for 5V AC and Pin=0.3W for 30V) Tight output regulation (CV:±5%, CC:±7%) Efficiency (%) V50Hz (68.3% avg) 5V60Hz (70.7% avg) 66.3% : Energy Star V.0 (Nov. 008) Output Voltage (V) AC90V AC30V AC0V AC64V % : CEC (008) Load (%) Figure 3. Measured Efficiency and Output Regulation Output Current (ma) nf C SN 30Ω R SN mh L P 5µH I O V O N4007 N4007 N4007 N4007 C DL 4.7µF kω CDL 4.7µF VDL R START MΩ R SN 00kΩ R DAMP 70Ω C SN nf D SN N N3 D R SB60 C O C P 470µF 0µF R PL kω D DD N4007 N4007 AC Line C DD 0µF N R COMR CCOMR 8kΩ µf 3 4 FAN0 CS GATE COMR VDD COMI SGND COMV VS R GATE 00Ω R CS.6Ω Q MOS FET FQUN60C R S 5kΩ R S 4.9kΩ 0nF 68nF C COMI 00kΩ R COMI C COMV R COMV 43kΩ C S 47pF Figure 3. Schematic of Typical Application Circuit FAN0 Rev

14 Typical Application Circuit (Continued) Transformer specification Core: EE6 Bobbin: EE6 Pin Specification Remark PrimarySide Inductance 3.3mH ± 5% 00kHz, V PrimarySide Effective Leakage 8 65μH ± 5%. Short one of the secondary windings FAN0 Rev

15 Physical Dimensions PIN ONE INDICATOR (0.33) A 0.5 M B C BA LAND PATTERN RECOMMENDATION.75 MAX R0.0 R (.04) DETAIL A SCALE: : C x SEATING PLANE 0.0 C GAGE PLANE 0.36 SEE DETAIL A OPTION A BEVEL EDGE OPTION B NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS0, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC7P600X758M. E) DRAWING FILENAME: M08AREV3 Figure 33. 8Lead, Small Outline Package (SOP8) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN0 Rev

16 FAN0 Rev