SG6742ML/MR Highly Integrated Green-Mode PWM Controller

Transcription

1 SG67ML/MR Highly Integrated Green-Mode PWM Controller Features High-Voltage Startup Low Operating Current:.7mA Linearly Decreasing PWM Frequency to KHz Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 6KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking Synchronized Slope Compensation Internal Open-Loop Protection GATE Output Maximum Voltage Clamp: 8V V DD Under-Voltage Lockout (UVLO) V DD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Internal Latch Circuit (OVP, OTP) Internal Sense Short-Circuit Protection Build-in ms Soft-Start Function Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis Applications General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS Description June 009 The highly integrated SG67ML/MR PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above KHz. The green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. To further reduce power consumption, SG67ML/MR is manufactured using the BiCMOS process, which allows an operating current of only.7ma. SG67ML/MR integrates a frequency-hopping function that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary, internal line compensation ensures constant output power limit over a wide AC input voltage range, from 90V AC to 6V AC. SG67ML/MR provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. PWM output is disabled until V DD drops below the UVLO lower limit, when the controller starts up again. As long as V DD exceeds ~6V, the internal OVP circuit is triggered. SG67ML/MR is available in an 8-pin SOP package. SG67ML/MR Highly Integrated Green-Mode PWM Controller Ordering Information Part Number Operating Temperature Range OLP Function Package Eco Status Packing Method SG67MLSY -0 to +0 C Latch 8-Lead Small Outline Package (SOP) Green Tape & Reel SG67MRSY -0 to +0 C Restart 8-Lead Small Outline Package (SOP) Green Tape & Reel For Fairchild s definition of Eco Status, please visit: Fairchild Semiconductor Corporation SG67ML/MR Rev..0.

2 Application Diagram Internal Block Diagram Figure. Typical Application SG67ML/MR Highly Integrated Green-Mode PWM Controller SG67ML SG67MR Figure. Functional Block Diagram 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0.

3 Marking Information ZXYTT 67MR TPM Pin Configuration GND FB NC HV ZXYTT 67ML TPM Figure. Top Mark SOP GATE VDD SENSE RT F- Fairchild Logo Z- Plant Code X- Digit Year Code Y- Digit week Code TT: Digits Die Run Code T: Package Type (D=DIP, S=SOP) P: Y: Green Package M: Manufacture Flow Code SG67ML/MR Highly Integrated Green-Mode PWM Controller Figure. Pin Configuration (Top View) Pin Definitions Pin # Name Description GND Ground. FB NC No connection. The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on the SENSE pin. HV For startup, this pin is pulled high to the line input or bulk capacitor via resistors. RT 6 SENSE For over-temperature protection, an external NTC thermistor is connected from this pin to the GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below a fixed limit, PWM output is latched. Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. 7 VDD Power supply. The internal protection circuit disables PWM output as long as V DD exceeds the OVP trigger point. 8 GATE The totem-pole output driver. Soft driving waveform is implemented for improved EMI. 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0.

4 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V VDD DC Supply Voltage (, ) 0 V V FB FB Pin Input Voltage V V SENSE SENSE Pin Input Voltage V V RT RT Pin Input Voltage V V HV HV Pin Input Voltage 00 V P D Power Dissipation (T A<0 C) 00 mw Θ JA Thermal Resistance (Junction-to-Air) C/W T J Operating Junction Temperature -0 + C T STG Storage Temperature Range - +0 C T L Lead Temperature (Wave Soldering or IR, 0 Seconds) +60 C ESD Electrostatic Discharge Capability, Human Body Model, JESD-A All Pins Except HV Pin kv Electrostatic Discharge Capability, Machine Model, JESD-A All Pins Except HV Pin 00 V Notes:. All voltage values, except differential voltages, are given with respect to the network ground terminal.. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. SG67ML/MR Highly Integrated Green-Mode PWM Controller 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0.

5 Electrical Characteristics V DD=V and T A= C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units V DD Section V OP Continuously Operating Voltage V V DD-ON Start Threshold Voltage.. 6. V V DD-OFF Minimum Operating Voltage V I DD-ST Startup Current V DD-ON 0.6V 0 µa I DD-OP Operating Supply Current V DD=V, GATE Open.7.7 ma I DD-OLP Internal Sink Current V TH-OLP+0.V µa V TH-OLP I DD-OLP Off Voltage V V DD-OVP V DD Over-Voltage Protection 6 7 V t D-VDDOVP HV Section I HV I HV-LC Oscillator Section f OSC V DD Over-Voltage Protection Debounce Time Supply Current from HV Pin Leakage Current After Startup Frequency in Normal Mode V AC=90V (V DC=0V), V DD=0µF HV=00V, V DD=V DD- OFF+V 7 00 µs... ma 0 µa Center Frequency Hopping Range ±.7 ±. ±.7 t HOP Hopping Period.9..9 ms f OSC-G Green-Mode Frequency 8 KHz KHz SG67ML/MR Highly Integrated Green-Mode PWM Controller f DV f DT Frequency Variation vs. V DD Deviation Frequency Variation vs. Temperature Deviation V DD=V to V % T A=-0 to 0 C % Continued on the following page PWM Frequency f OSC f OSC-G V FB-ZDC V FB-G V FB-N V FB Figure. V FB vs. PWM Frequency 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0.

6 Electrical Characteristics (Continued) V DD=V and T A= C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Feedback Input Section A V Input Voltage to Current-Sense Attenuation /. /.0 /. V/V Z FB Input Impedance 7 kω V FB-OPEN Output High Voltage FB Pin Open. V V FB-OLP FB Open-Loop Trigger Level V t D-OLP Delay Time of FB Pin Open-Loop Protection ms V FB-N Green-Mode Entry FB Voltage.8.0. V V FB-G Green-Mode Ending FB Voltage V FB-N-0.6 V V FB-ZDC Zero Duty-Cycle Input Voltage.6 V Current-Sense Section Z SENSE Input Impedance KΩ V STHFL Current Limit Flatten Threshold Voltage V V STHVA Current Limit Valley Threshold Voltage V STHFL V STHVA V t PD Delay to Output ns t LEB Leading-Edge Blanking Time ns V S-SCP Threshold Voltage for SENSE Short-Circuit Protection V t D-SSCP Delay Time for SENSE Short-Circuit Protection V SENSE<0.V µs t SS Period During Soft-Startup Time Startup Time ms GATE Section DCY MAX Maximum Duty Cycle % V GATE-L Gate Low Voltage V DD=V, I O=0mA. V V GATE-H Gate High Voltage V DD=V, I O=0mA 8 V t r Gate Rising Time V DD=V, C L=nF ns t f Gate Falling Time V DD=V, C L=nF ns SG67ML/MR Highly Integrated Green-Mode PWM Controller I GATE- SOURCE Gate Source Current V DD=V, GATE=6V 0 ma V GATE- CLAMP Gate Output Clamping Voltage V DD=V 8 V RT Section I RT Output Current from RT Pin µa V RTTH 0.7V < V RT <.0V, After ms V Over-Temperature Protection Threshold Voltage Latch Off V RTTH V RT < 0.7V, After 00µs Latch Off V t D-OTP V RTTH < V RT < Over-Temperature Latch-off Debounce V RTTH 8 6 ms t D-OTP V RT< V RTTH µs Over-Temperature Protection Section (OTP) T OTP Protection Junction Temperature () + C T Restart Restart Junction Temperature () T OTP- C Notes:. When activated, the output is disabled and the latch is turned off.. The threshold temperature for enabling the output again and resetting the latch after OTP has been activated. 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0. 6

7 Typical Performance Characteristics IDD_ST (μa) Figure 6. Startup Current (I DD-ST) VDD-ON (V) Figure 8. Start Threshold Voltage (V DD-ON) IDD-OP (ma) VDD-OFF (V) Figure 7. Operation Supply Current (I DD-OP) Figure 9. Minimum Operating Voltage (V DD-OFF) 0 8 SG67ML/MR Highly Integrated Green-Mode PWM Controller IHV (ma) IHV-LC (μa) Figure 0. Supply Current Drawn from HV Pin (I HV) 70 Figure. HV Pin Leakage Current After Startup (I HV-LC) fosc (khz) 66 6 DCYMAX (%) Figure. Frequency in Normal Mode (f OSC) Figure. Maximum Duty Cycle (DCY MAX) 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0. 7

8 Typical Performance Characteristics VFB-OLP (V) Figure. FB Open-Loop Trigger Level (V FB-OLP) VS-SCP (V) Figure 6. Threshold Voltage for SENSE Short-Circuit Protection (V S-SCP). td-olp (ms) Figure. Delay Time of FB Pin Open-Loop Protection (t D-OLP) IRT (μa) Figure 7. Output Current from RT Pin (I RT) 0.9 SG67ML/MR Highly Integrated Green-Mode PWM Controller. 0.8 VRTTH (V) VRTTH (V) Figure 8. Over-Temperature Protection Threshold Voltage (V RTTH) Figure 9. Over-Temperature Protection Threshold Voltage (V RTTH) 7 6. VDD-OVP (V) Figure 0. V DD Over-Voltage Protection (V DD-OVP) 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0. 8

9 Functional Description Startup Current For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, R HV, (N007 / 00KΩ recommended). Typical startup current drawn from the HV pin is.ma and charges the hold-up capacitor through the diode and resistor. When the V DD capacitor level reaches V DD-ON, the startup current switches off. At this moment, the V DD capacitor only supplies the SG67ML/MR to keep the V DD before the auxiliary winding of the main transformer provides the operating current. Operating Current Operating current is around.7ma. The low operating current enables better efficiency and reduces the requirement of V DD hold-up capacitance. Green-Mode Operation The proprietary green-mode function provides off-time modulation to reduce the switching frequency in lightload and no-load conditions. The on time is limited for better abnormal or brownout protection. V FB, which is derived from the voltage feedback loop, is taken as the reference. Once V FB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency of around KHz. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and V FB, the feedback voltage. When the voltage on SENSE pin reaches around V COMP=(V FB 0.6)/, the switch cycle is terminated immediately. V COMP is internally clamped to a variable voltage around 0.8V for output power limit. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at.v and 9.V. During startup, the hold-up capacitor must be charged to.v through the startup resistor to enable the IC. The hold-up capacitor continues to supply V DD before the energy can be delivered from auxiliary winding of the main transformer. V DD must not drop below 9.V during startup. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply V DD during startup. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 8V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. Built-in Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. SG67ML/MR inserts a synchronized, positive-going, ramp at every switching cycle. Constant Output Power Limit When the SENSE voltage across sense resistor R S reaches the threshold voltage, around 0.9V, the output GATE drive is turned off after a small delay, t PD. This delay introduces an additional current proportional to t PD V IN / L P. Since the delay is nearly constant regardless of the input voltage V IN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a sawtooth power-limiter is designed to solve the unequal powerlimit problem. The power limiter is designed as a positive ramp signal fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. V DD Over-Voltage Protection (OVP) V DD over-voltage protection is built in to prevent damage due to abnormal conditions. If the V DD voltage is over the over-voltage protection voltage (V DD-OVP) and lasts for t D-VDDOVP, the PWM pulses are disabled until the V DD voltage drops below the UVLO, then starts again. Over-voltage conditions are usually caused by open feedback loops. Thermal Protection An NTC thermistor, R NTC, in series with resistor R A, can be connected from the RT pin to ground. A constant current I RT is output from the RT pin. The voltage on the RT pin can be expressed as V RT=I RT (R NTC + R A), where I RT is 00µA. At high ambient temperatures, R NTC is smaller, such that V RT decreases. When V RT is less than.0v (V RTTH), the PWM turns off after ms (t D-OTP). If V RT is less than 0.7V (V RTTH), PWM turns off after 00µs (t D-OTP). SG67ML/MR Highly Integrated Green-Mode PWM Controller 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0. 9

10 Functional Description (Continued) Limited Power Control The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than t D-OLP, PWM output is turned off. As PWM output is turned off, V DD begins decreasing. When V DD goes below the turn-off threshold (~9.V) the controller is totally shut down. V DD is charged up to the turn-on threshold voltage of.v through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. When V RT is less than.0v (V RTTH), the PWM is turned off after ms (t D-OTP). If V RT is less than 0.7V (V RTTH), PWM is turned off after 00µs (t D-OTP). Noise Immunity Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the SG67ML/MR, and increasing the power MOS gate resistance improve performance. SG67ML/MR Highly Integrated Green-Mode PWM Controller 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0. 0

11 Applications Information CN CN BOM F L C C T R U GND FB NC HV C D SG67MR GATE VDD SENSE RT VZ R6 C + C9 THER D BD C0 R R U U + C A K R9 D R8 C Q R7 R0 R 6 T 8 7 Figure. 60W Flyback V/A Application Circuit C R VO+ R Q C6 + C7 L Designator Part Type Designator Part Type BD BD A/600V L Inductor (900µH) R VO+ + C8 L D VO+ VO- SG67ML/MR Highly Integrated Green-Mode PWM Controller C XC 0.68µF/00V Q STP0-00CT C XC 0.µF/00V Q MOS 7A/600V C YC 00pF/Y R R 00KΩ /W C EC 0µF/00V R R 7Ω /W C CC 0.0µF/00V R R 00KΩ /W C6 CC 000pF/00V R R.7Ω /8W C7 EC 000µF/V R R 00Ω /8W C8 EC 70µF/V R6, R9 R.7KΩ /8W C9 EC µf/0v R7 R 0.Ω W C0 CC 7pF/0V R8 R 680Ω /8W C CC 00pF/0V R0 R 0KΩ /8W C CC 0.0µF/0V R R 9KΩ /8W D Zener Diode V /W (option) THER Thermistor TTC0 D BYV9C T 0mH D FR0 T 600µH(PQ60) D N007 U IC SG67 F FUSE A/0V U IC PC87 L Inductor (900µH) U IC TL L Inductor (µh) VZ VZ 9G 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0.

12 Physical Dimensions PIN ONE INDICATOR (0.).7 MAX R0.0 R (.0) DETAIL A SCALE: :.7 0. C A M x 0. B SEATING PLANE C BA 0.0 C GAGE PLANE LAND PATTERN RECOMMENDATION SEE DETAIL A OPTION A - BEVEL EDGE OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED.60 A) THIS PACKAGE CONFORMS TO JEDEC MS-0, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC7P600X7-8M. E) DRAWING FILENAME: M08AREV SG67ML/MR Highly Integrated Green-Mode PWM Controller Figure. 8-Pin Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Fairchild Semiconductor Corporation SG67ML/MR Rev..0.

13 008 Fairchild Semiconductor Corporation SG67ML/MR Rev..0. SG67ML/MR Highly Integrated Green-Mode PWM Controller