Five Output Power System for Zynq-7020 All Programmable SoC FEATURES

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1 Five Output Power System for Zynq-700 All Programmable SoC June 06 GENERAL DESCRIPTION This reference design is a complete five-output power system designed to power a Xilinx Zynq-700 All Programmable (AP) SoC and associated DDR memory in Industrial Ethernet applications. This reference design is focused on Industrial Ethernet applications leveraging HMS s Anybus IP on Xilinx. Although the power requirements of the core system building blocks remain relatively constant, the flexibility of Exar s Universal PMICs provides a power solution that can power the wider system requirements, whether a motor control board or human interface module. The power system provides VCCPINT, VCCINT and VCCBRAM.00V, VCCO_DDR programmable to./.5/.5v, VTT 0.60/0.675/0.75V, VCCAUX and VCCADC.8V and VCCO programmable from.8v to.v. The entire power system fits in less than one square inch. The order and ramp rates for each supply are programmed to accommodate Zynq-700 sequencing requirements. All power supply operations can be controlled over an IC interface. Faults, output voltages and currents can also be monitored. GPIO signals are available and can be programmed to provide the status of power good signals, enables, and faults. The board is supported by PowerArchitectTM.x and connects to the Exar Communications Module (XR77XXEVB-XCM-V80). Exar Corporation 870 Kato Road, Fremont CA 958, USA Rev..0. FEATURES Xilinx Zynq-700 All Programmable SoC Power System Channel Power System using XRP77 Programmable Digital PWM Switching Controller VCCPINT, VCCINT and VCCBRAM.0V VCCO_DDR programmable to./.5/.5v VTT 0.60/0.675/0.75V VCCO programmable to from.8v to.v VCCAUX and VCCADC.8V IC Interface Programming Monitoring Control Tel Fax

2 ZYNQ-700 AP SOC POWER SOLUTION The Zynq-700 AP SoC power reference design provides output voltages. The order and ramp rates for each output are programmed to accommodate Zynq-700 AP SoC sequencing requirements. The power system was designed to operate at 650kHz as a good trade-off between space and efficiency. Output /Channel Configuration Channel is designed to provide V to VCCINT, VCCBRAM and VCCPINT Zynq-700 AP SoC rails at.0a. However, the hardware is capable of supporting output currents up to Amps. Output /Channel Configuration Channel provides.5v to Zynq-700 AP SoC IO banks (VCCO) and peripherals in the system. The channel is configured for a.5a output, but the hardware is capable of supporting up to a Amp load. Output /Channel Configuration Output /Channel Configuration Channel provides.5v to the DDR SDRAM subsystem as well as the DDR block inside the Zynq-700 AP SoC. In addition, it sources the XRP997 DDR Bus Termination Regulator which provides termination voltage for the DDR SDRAM signals. The channel is configured for a.0a output, but the hardware is capable of supporting up to a Amp load. Channel is designed to provide.8v to VCCAUX and VCCADC Zynq-700 AP SoC rails at 0.5A. The channel is configured for a 0.5A output, but the hardware is capable of supporting up to a.5amp load. 06 Exar Corporation / Rev..0.

3 LDOOUT LDOOUT is routed to XRP997 control pin enabling the device. CHANNEL SEQUENCING The XRP77 sequencing has been designed to meet the Zynq-700 AP SoC power up sequencing requirements. Power-On Sequencing..0V supply with 0.077V/msec ramp rate..8v supply with 0.V/msec ramp rate..5v and.5v supplies - the.5v supply with 0.5V/msec ramp rate reaching the target level at the same time as the.5v supply with 0.9V/msec ramp rate. Power-Down Sequencing..5V and.5v supplies the.5v supply following 0.875V/msec ramp down rate; the.5v supply following 0.5V/msec ramp down rate. Both channels regulate down to the shutdown threshold of 00mV before switching stops...0v and.8v supplies the.0v supply following 0.5V/msec ramp down rate; the.8v supply following 0.5V/msec ramp down rate. Both channels regulate down to the shutdown threshold of 00mV before switching stops. 06 Exar Corporation / Rev..0.

4 ZYNQ-700 AP SOC POWER ON RESET XRP77 will generate a power on reset signal on GPIO to the Zynq-700 AP SoC 00ms after the last rail is in regulation. POWERING UP THE BOARD The board hardware is provided capable of supporting an input voltage range of 5.5V to 5V with power connected directly to J5 (VIN) and J6 (GND). I C Interface The Zynq-700 AP SoC power reference design schematic shows an I C interface connector (HDR) to connect the Exar Communications Module (XR77XXEVB-XCM-V80 which has its own users guide available). This provides an interface with PowerArchitect TM.x allowing programming of the board. Ensure the XCM is configured to use the on board pull-up resistors (check jumper settings). If communication between Zynq-700 AP SoC and XRP77 is desired, ensure that the Zynq-700 AP SoC system board has pull-up resistors installed. For more information how to implement power subsystem control and monitoring via I C bus refer to ANP-. Configuring the Board The board is typically delivered with a XRP77 which has not yet had its OTP memory burned with a specific configuration. This allows the user to select a different VIO voltage or DDR memory voltage than the one used in the default configuration file available from Exar s web site Exar Corporation / Rev..0.

5 TYPICAL PERFORMANCE CHARACTERISTICS All data taken at VIN = V, fsw=650khz, TJ = TA = 5 C, unless otherwise specified Fig. : Channel,.0V Efficiency Fig. : Channel,.5V Efficiency Fig. : Channel,.5V Efficiency Fig. : Channel,.8V Efficiency Fig. 5: Channel,.0V Load Regulation Fig. 6: Channel,.5V Load Regulation 06 Exar Corporation 5/ Rev..0.

6 Fig. 7: Channel,.5V Load Regulation Fig. 8: Channel,.8V Load Regulation Fig. 9: Channel,.0V Load Transient 5% - 75% 5A/us Fig. 0: Channel,.5V Load Transient 5% - 75% 5A/us Fig. : Channel,.5V Load Transient 5% - 75% 5A/us Fig. : Channel,.8V Load Transient 5% - 75% 5A/us 06 Exar Corporation 6/ Rev..0.

7 Fig. : Channel,.0V Full Load Output Ripple Fig. : Channel,.5VV Full Load Output Ripple Fig. 5: Channel,.5V Full Load Output Ripple Fig. 6: Channel,.8V Full Load Output Ripple Fig. 7: Input Cap Ripple 06 Exar Corporation 7/ Rev..0.

8 5 J5 D C V TP _V 0mA GPIOs can be configured for External Clk Sync, Enables, Pwr Good, O/C warnign/fault, Over temp, Over voltage, etc HDR Pin Header (IC) TP TP VCCA C5.7uF, 6V 0805 C8.7uF, 6V 0805 TP0 R 68k C7.7uF, 6V 0805 LDO_OUT C Vin VCCA.uF C L uF, 6V.5uH C CAP06 QB GH DMN050LFDB.7uF, 6V 5 C 0805 LX 00uF, 6,V C6 GL CAP06 GL GH 0.uF SD0AWS QA 00 D VCCD DMN050LFDB Vout Vin LX 7 C7 6 C0 PAD L.7uF, 6V CAP06.5uH R 7uF, 0V QB 00k 0.% 0 AVDD GL GH DMN050LFDB GL C9 CAP06 5 GL 9 68uF DVDD LX LX CAP06 C 8 0.uF R GPIO0 GH GH 00 D SD0AWS 00k 0.% C 7 VCCD GPIO VCCD U BST.uF GPIO VCCD 6 C5 C.uF 0805 D R 6 XRP77 5 GPIO BST VCCA SD0AWS LX 7 QA C6 Vout GPIO_SDA GH GH 0.uF Vin DMN00UFL GPIO5_SCL LX LX 9 Exposed Pad: AGND L ENABLE GL GL.7uH C8 0.7uF, 6V QB DGND PGND GH CAP06 DMN00UFL C9 GL 5 uf, 6.V CAP06 0 LDOOUT 9 VIN 8 VIN VCCA 7 AGND VOUT VOUT VOUT 6 PGND VOUT 5 GL PGND LX GL GH LX BST GH PGND BST LX QA DMN050LFDB Vout 7uF, 0V CAP06 Vout Vout U XRP997 VIN NC 8 GND NC 7 VREF VCNTL 6 VOUT NC 5 PAD 9 Vout LDO_OUT VoutTerm V A C 7uF, 0V CAP06 _5V 5V A 0_75V_0_675V.5A _8V 0.5A D C B Vout Vout 5 6 Vout Vout GH GL C0 0.uF 00 D VCCD SD0AWS LX Vin C.7uF, 6V CAP06 GH GL QA LX DMN050LFDB L.7uH QB DMN050LFDB Vout C 7uF, 0V CAP06 Vout TP _V 5V 8V.5A B PS_POR_B J Vout Vout J Vout Vout J Vout Vout J Vout Vout J6 A Notes: ) Meets all Zynq seq and dependency constraints ) All higher value ceramics can be built out of multiples of uf to decrease cost. ) All system requiremetns (eg Seq, O/C, O/V, O/T, enables, power good, etc) are configurable ) Realtime readout of Vin, Vout, Iout, etc available via IC 5) Output current can be programmed up to approx.5a/ch 6) Vout options programmable 7) PS_POR_B is correctly timed. J7 J8 J9 J0 J5 J6 VoutTerm Title Exar Xilinx Ind Enet V0.9 Version Size Document Number Rev B.0 A Date: Monday, June, 06 Sheet of 5

9 BILL OF MATERIAL Ref. Qty Manufacturer Part Number Size Component PCB Exar XRP77EVB_IND_V09_VER U Exar XR77ILB-F U Exar XRP997IDBTR-F SOICD B08 Q,Q,Q Diodes, Inc. DMN050LFDB U-DFN00-6 Q Diodes, Inc. DMN00UFL X-DFN0-6 A, DDR I/II/II Bus Term. Regulator Dual N-Ch. MOSFET, 0V,.5A, 5mOhm Dual N-Ch. MOSFET, 0V,.A, 95mOhm D,D,D,D Diodes, Inc. SD0AWS SOD- SMT Barrier Diode, 60V, 5mA L,L L,L Wurth Elektronik Wurth Elektronik X6.8MM X.8MM C,C9,C MURATA GRMCR60J07ME9L 06 C0, C, C5, C9 MURATA GRMCR6A76KE5L 06 C,C7,C8,C MURATA GRMCR7H75KAL 06 C,C5,C8,C7 MURATA GRMBR7E75KA7L 0805 C,C,C MURATA GRMBR7C5KAL 0805 C6,C,C6,C0 MURATA GRM55R7E0KED 00 R,R PANASONIC ERA-AEB0V 060 R PANASONIC ERJ-EKF680V 060 R PANASONIC ERJ-RQFR0V 060 J7,J,J8,J,J,J9,J0,J,J6,J5,J6,J5 TP,TP0,TP,TP,TP 5 -SCL,GND,SDA Vector Electronics Wurth Electronics Wurth Electronics SMD Inductor.5uH,.A,.0 mohm SMD Inductor.7uH,.A, 5.0 mohm CERAMIC CAP. 00uF, 6.V, X5R, 0% CERAMIC CER, 7uF, 0V, X5R, 0% CERAMIC CAP.,.7uF, 50V, X7R, 0% CERAMIC CAP.,.7uF, 5V, X7R, 0% CERAMIC CAP.,.uF, 6V, X7R, 0% CERAMIC CAP., 0.uF, 5V, X7R, 0% Resistor 00.0K Ohm, 0.% /0W, SMD Resistor 68.0K Ohm, /0W,%,SMD Resistor.0 Ohm, /0W,%,SMD Vector Electronics.0" Hole PCB Pin 600 Test Point Test Point 600 Test Point PIN HEADER 06 Exar Corporation 9/ Rev..0.

10 EVALUATION BOARD LAYOUT (FOR REFERENCE) Figure : Component Placement Top Side Figure : Top Layer 06 Exar Corporation 0/ Rev..0.

11 Figure 5: Ground Plane Figure 6: Mid-Layer 06 Exar Corporation / Rev..0.

12 Figure 7: Mid-Layer Figure 8: Mid-Layer 06 Exar Corporation / Rev..0.

13 Figure 9: Bottom Layer 06 Exar Corporation / Rev..0.

14 DOCUMENT REVISION HISTORY Revision Date Description //06 Initial release of document.0. 07/9/06 Added electrical characteristic curves FOR FURTHER ASSISTANCE Exar Technical Documentation: EXAR CORPORATION HEADQUARTERS AND SALES OFFICES 870 Kato Road Fremont, CA 958 USA Tel.: + (50) Fax: + (50) NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 06 Exar Corporation / Rev..0.