XR77103-A1R0. Universal PMIC 3-Output Buck Regulator. Description

Transcription

1 XR773-AR Universal PMIC 3-Output Buck Regulator Description The XR773-AR universal PMIC features three A synchronous high-efficiency, buck regulators with integrated power switches. They can operate in 5V, 9V and V powered systems with minimal required external component thus providing the smallest size solution possible. Two of the outputs may be paralleled for output currents up to 5A peak with steady state current of up to 4A. The output voltage of each converter can be adjusted by external resistor divider down to voltage as low as.8v. With a nominal switching frequency of MHz, the regulators can also be synchronized to an external clock in applications where EMI control is critical. XR773-AR features a supervisor circuit that monitors each converter output. PGOOD pin is asserted once sequencing is done, outputs are reported in regulation and the reset timer expires. The polarity of the signal is active high. A pulse skipping mode (PSM) reduces switching losses maintaining high efficiency when the system is unloaded or in standby mode. FEATURES 4.5V to 4V wide input supply voltage range Built-in MOSFET and synchronous rectifier.8v, high accuracy reference (%) Current-mode control with simple compensation circuit External synchronization Power good Protection Thermal shutdown Overvoltage transient protection Overcurrent protection 3-pin 4mm x 4mm TQFN package APPLICATIONS FPGA and DSP supplies Video processor supplies Applications processor power /9

2 XR773-AR Typical Application PGOOD 8 4 VIN VIN 6 4 VCC PGOOD Start-up BGR Internal Supply PGOOD OSC SY 5 VIN = 5.5 to 4V VIN BST 9 5 VIN LX 3 VIN3 BUCK LX VOUT =.8 to 6V VOUT3 =.8 to 6V 3 BST3 3 LX3 9 LX3 VFB3 COMP3 BUCK3 BUCK VFB 8 COMP 7 BST VFB 7 VOUT =.8 to 6V XR773-AR EN 6 COMP AGND DGND GND EP 8 Figure. Typical Application /9

3 XR773-AR Absolute Maximum Ratings These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. V IN, V IN, V IN3, LX,, LX V to 8V EN, V CC V to 7V PGOOD, SY V to 7V BST# to LX# V to 7V AGND, DGND to GND V to.3v Storage temperature C to 5 C Junction temperature... 5 C Power dissipation... Internally Limited Lead temperature (soldering, seconds)... 6 C CDM... 7V ESD rating (HBM human body model)... kv Operating Conditions V IN...4.5V to 4V V CC...4.5V to 5.5V LX#...-.3V to 4V () Junction temperature range (T J ) C to 5 C XR773 package power dissipation max at 5 C W XR773 thermal resistance θ JA... 3 C/W NOTE:. LX# pins DC range is from -.3V, transient -V for less than ns. Electrical Characteristics T A = 5 C, V IN = V, EN = V CC, f SW = MHz, unless otherwise specified. Limits applying over the full operating temperature range are denoted by a. Symbol Parameter Conditions Min Typ Max Units Power Supply Characteristics V IN Input voltage range V V IN Input voltage range V CC tied to V IN V V UVLO UVLO threshold V IN rising/falling 4./4. V UVLO DEGLITCH UVLO deglitch Rising/falling µs I VIN EN = GND 5 µa V IN supply current I VINQ EN = high, no load.6 ma Internal Supply Voltage V CC Internal biasing supply I LOAD = ma V I VCC Internal biasing supply current V IN = V ma V UVLO UVLO threshold for V CC V CC rising 3.8 V V CC falling 3.6 V UVLO DEGLITCH UVLO deglitch for V CC Falling edge µs 3/9

4 Electrical Characteristics (Continued) XR773-AR T A = 5 C, V IN = V, EN = V CC, f SW = MHz, unless otherwise specified. Limits applying over the full operating temperature range are denoted by a. Symbol Parameter Conditions Min Typ Max Units Protections T SD Thermal shutdown temperature Temperature rising, Non-latch off. 6 C T SD release threshold, HY TSD Thermal shutdown hysteresis temperature = T SD -HY TSD C T SD_DEGLITCH Thermal shutdown deglitch µs V OVBUCK Threshold voltage for buck overvoltage Output rising (HS FET will be forced off) Output falling (HS FET will be allowed to switch) 9 % 7 % Buck Converter f SW Switching frequency MHz t SS Soft-start period 3 ms I LIMx Peak inductor current limit 3.5 A R ON_HSx HS switch on-resistance V IN = V mω R ON_LS LS switch on-resistance of Buck V IN = V 6 mω R ON_LS/3 LS switch on-resistance of Buck/3 V IN = V 8 mω I Ox Output current capability Continuous loading () A D MAX Maximum duty cycle 95 % t ON MIN Minimum on time ns Line regulation (ΔV OX /ΔV INX ) V INX = 5.5 to 4V, I OX = A.5 %V O Load regulation (ΔV OX /ΔI OX ) I O = to 9%, I O = MAX.5 %V O /A Output voltage accuracy V IN = V - Normal 5.5V V IN 4V - Normal % SY FREQ Synchronization frequency.5 MHz SY D_MIN SY D_MAX Synchronization signal minimum duty cycle Synchronization signal maximum duty cycle 4 % 6 % NOTE:. Subject to thermal derating. Design must not exceed the package thermal rating. 4/9

5 XR773-AR Electrical Characteristics (Continued) T A = 5 C, V IN = V, EN = V CC, f SW = MHz, unless otherwise specified. Limits applying over the full operating temperature range are denoted by a. Symbol Parameter Conditions Min Typ Max Units Power Good Reset Generator V UVBUCK Threshold voltage for buck under voltage Output falling, (disabled after t ON_HICCUP ) Output rising, (PG will be asserted) 9 85 % t PG_DEGLITCH Deglitch time Rising and falling ms t ON_HICCUP Hiccup mode on time V UVBUCKX asserted ms t OFF_HICCUP Hiccup mode off time Once t OFF_HICCUP elapses, all converters will start up again 5 ms t RP Minimum reset period s R PG Power good pull-down on resistance Input Threshold (SY, EN) 4 5 Ω V IH Input threshold high V INPUT rising.7.53 V V IL Input threshold low V INPUT falling V 5/9

6 XR773-AR Pin Configuration BST SY VFB3 4 PGOOD COMP GND COMP 7 8 VFB VIN LX VIN BST BST3 VIN3 LX3 LX3 VIN AGND EN VIN VCC DGND COMP VFB LX Pin Functions Pin Number Pin Name Description VFB3 Buck 3 feedback pin. COMP3 Compensation pin for Buck 3. Connect a series RC circuit to this pin for compensation. 3 No connect. 4 VIN IC supply pin. Connect a capacitor as close as possible to this pin. 5 GND Ground. 6 VCC Internal supply. Connect a ceramic capacitor from this pin to ground. 7 COMP Compensation pin for Buck. Connect a series RC circuit to this pin for compensation. 8 VFB Buck feedback pin. 9 BST Bootstrap capacitor for Buck. Connect a bootstrap capacitor from this pin to LX. VIN Input supply for Buck. Connect a capacitor as close as possible to this pin. LX Switching node for Buck. LX Switching node for Buck. 3 Switching node for Buck. 4 Switching node for Buck. 5 VIN Input supply for Buck. Connect a capacitor as close as possible to this pin. 6 BST Bootstrap capacitor for Buck. Connect a bootstrap capacitor from this pin to. 7 VFB Buck feedback pin. 8 COMP Compensation pin for Buck. Connect a series RC circuit to this pin for compensation. 9 DGND Digital ground. No connect. 6/9

7 XR773-AR Pin Functions (Continued) Pin Number Pin Name Description No connect. No connect. 3 No connect. 4 PGOOD Power good output. Open drain output asserted after all converters are sequenced and within regulation. 5 SY External clock input pin. Connect to signal ground when unused. 6 EN Enable control input. Set EN high to enable converters. 7 AGND Analog ground. 8 VIN IC supply pin. Connect a capacitor as close as possible to this pin. 9 LX3 Switching node for Buck 3. 3 LX3 Switching node for Buck 3. 3 VIN3 Input supply for Buck 3. Connect a capacitor as close as possible to this pin. 3 BST3 Bootstrap capacitor for Buck 3. Connect a bootstrap capacitor from this pin to LX3. - E-PAD Connect to power ground. 7/9

8 XR773-AR Typical Performance Characteristics All data taken at f SW = MHz, T A = 5 C, no airflow, unless otherwise specified. VOUT/VOUT (%) VOUT/VOUT (%) Figure. Load Regulation Channel, V IN, 3.3V OUT Figure 3. Load Regulation Channel, 5V IN, 3.3V OUT VOUT/VOUT (%) VOUT/VOUT (%) Figure 4. Load Regulation Channel, V IN,.8V OUT Figure 5. Load Regulation Channel, 5V IN,.8V OUT VOUT/VOUT (%) VOUT/VOUT (%) Figure 6. Load Regulation Channel 3, V IN,.5V OUT Figure 7. Load Regulation Channel 3, 5V IN,.V OUT 8/9

9 XR773-AR Typical Performance Characteristics (Continued) All data taken at fsw = MHz, TA = 5 C, no airflow, unless otherwise specified. VOUT AC MHz Enable Channel 3 76.mV -64.mV Channel IOUT Channel Di/Dt.5A/μs Figure 8. Power-up Sequence VOUT AC MHz Figure 9. VIN, 5.VOUT Transient Response,.5A to.a 3.mV VOUT AC MHz -.mv -48.mV IOUT IOUT Di/Dt.5A/μs Di/Dt.5A/μs Figure. VIN,.8VOUT Transient Response,.5A to.a Figure. VIN, 3.3VOUT Transient Response,.5A to.a VOUT AC MHz 49.mV 57.mV 36.mV VOUT AC MHz -36.mV -55.mV IOUT IOUT Di/Dt.5A/μs Di/Dt.5A/μs Figure. 5VIN, 3.3VOUT Transient Response,.5A to.a Figure 3. 5VIN,.8VOUT Transient Response,.5A to.a 9/9

10 XR773-AR Typical Performance Characteristics (Continued) Efficiency f SW = MHz, T A = 5 C, no airflow, only individual channel operating, inductor losses are included. Efficiency (%) Efficiency (%) Figure 4. Efficiency Channel, V IN 3.3V OUT Figure 5. Efficiency Channel, 5V IN 3.3V OUT Efficiency (%) Efficiency (%) Figure 6. Efficiency Channel, V IN.8V OUT Figure 7. Efficiency Channel, 5V IN.8V OUT Efficiency (%) Efficiency (%) Figure 8. Efficiency Channel 3, V IN.5V OUT Figure 9. Efficiency Channel 3, 5V IN.V OUT /9

11 XR773-AR Typical Performance Characteristics (Continued) Thermal Characteristics Power Dissipation in Package (W) TAMBIENT ( C) Figure. Package Thermal Derating Power Loss (W) V.5V 3.3V Figure. Channel Power Loss at f SW = MHz, V IN = V, No Airflow Power Loss (W) V.5V 3.3V Power Loss (W) V.5V 3.3V Figure. Channel Power Loss at f SW = MHz, V IN = V, No Airflow Figure 3. Channel 3 Power Loss at f SW = MHz, V IN = V, No Airflow Power Loss (W) V.8V.5V 3.3V Power Loss (W) V.8V.5V 3.3V Figure 4. Channel Power Loss at f SW = MHz, V IN = 5V, No Airflow Figure 5. Channel Power Loss at f SW = MHz, V IN = 5V, No Airflow /9

12 XR773-AR Typical Performance Characteristics (Continued) Thermal Characteristics Power Loss (W) V.8V.5V 3.3V Figure 6. Channel 3 Power Loss at f SW = MHz, V IN = 5V, No Airflow /9

13 XR773-AR Functional Block Diagram 8 4 VIN VIN 6 4 VCC PGOOD Start-up BGR Internal Supply PGOOD OSC SY VIN VIN VIN3 BST3 LX3 LX3 VFB3 COMP3 BUCK3 BUCK BUCK BST LX LX VFB COMP BST VFB COMP XR773-AR EN 6 AGND DGND GND EP Figure 7. Functional Block Diagram 3/9

14 XR773-AR Applications Information Operation XR773-AR is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. XR773-AR can support 4.5V to 4V input supply, high load current, MHz clocking. The buck converters have a PSM mode which can improve power dissipation during light loads. Alternatively, the device implements a constant frequency mode. The SY pin also provides a means to synchronize the power converter to an external signal. Input ripple is reduced by 8 degree out-of-phase operation among converters. All three buck converters have peak current mode control which simplifies external frequency compensation. Each buck converter has peak inductor current limit of 3.5A. The device has a power good comparator monitoring the output voltage. Soft-start for each converter is 3ms. All outputs start up once EN pin is set high. Output Voltage Setting Output voltage is set externally using an external resistor divider. Output voltage is determined by the following equation. VOUTX =.8V x + R R XR773-AR VOUTX R R Figure 8. Output Voltage Setting This can make the device applicable to AVS (automatic voltage scaling) system. Output voltage can be adjusted automatically by external DC voltage. Figure 9 shows application circuit of supply for AVS system. XR773-AR VFBX VOUTX R R RDAC VDAC Figure 9. AVS Control AVS SUPPLY PVT MNT SOC Frequency Compensation In order to properly frequency compensate the device, the following component selection is recommended. V IN (V) V OUT (V) L (μh) C OUT (µf) R COMP (kω) C COMP (nf) x x x 4.7 / x 4.7 / x 4.7 / x x 4.7 Synchronization The status of the SY pin will be ignored during start-up and the XR773-AR s control will only synchronize to an external signal after the PGOOD signal is asserted. When synchronization is applied, the sync pulse frequency must be higher than the PWM oscillator frequency (.5MHz) to allow the external signal trumping the oscillator pulse reliably. When synchronization is not applied, the SY pin should be connected to signal ground. Although the device can lock to external clock running up to.3mhz, doing this will alter the timing characteristics and degrade thermal performance. 4/9

15 XR773-AR Applications Information (Continued) Out-of-Phase Operation Channels and operate in phase while channel 3 operates 8 degrees out-of-phase with the other two converters (see Figure 3). This enables the system, having less input ripple, to lower component cost, save board space and reduce EMI. LX LX3 Figure 3. Out-of-Phase Operation Two Buck Regulators in Parallel Operation (Current Sharing) The XR773-AR can be used in parallel operation to increase output current capacity. To enable this, a user needs: To connect V OUT and V OUT3 together. To connect COMP and COMP3 together. Regulate the channels and 3 to the same V OUT. Then, the channels and 3 will run in parallel and load current is shared in average. BUCK BUCK3 VFB COMP COMP3 LX3 LX3 VFB3 Figure 3. Parallel Operation VOUT Power Good The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all three buck converters outputs are more than 9% of their nominal output voltage and the PGOOD reset timer expires. The polarity of the PGOOD is active high. The PGOOD reset time is s. Thermal Design Proper thermal design is critical in controlling device temperatures and in achieving robust designs. There are a number of factors that affect the thermal performance. One key factor is the temperature rise of the devices in the package, which is a function of the thermal resistances of the devices inside the package and the power being dissipated. The thermal resistance of the XR773-AR (3 C/W) is specified in the Operating Conditions section of this datasheet. The θ JA thermal resistance specification is based on the XR773-AR evaluation board operating without forced airflow. Since the actual board design in the final application will be different, the thermal resistances in the final design may be different from those specified. The package thermal derating and power loss curves are shown in Figures through 6. These correspond to input voltages of V and 5V. Layout Guidelines Proper PCB layout is crucial in order to obtain a good thermal and electrical performance. For thermal considerations it is essential to use a number of thermal vias to connect the central thermal pad to the ground layer(s). In order to achieve good electrical and noise performance following steps are recommended: Place the output inductor close to the LX pins and minimize the area of the connection. Doing this on the top layer is advisable. Central thermal pad shall be connected to the power ground connections to as many layers as possible. Output filtering capacitor shall share the same power ground connection as the input filtering capacitor. Connection to the signal ground plane shall be done with vias placed at the output filtering capacitors. AC current loops formed by input filtering capacitors, output filtering capacitors, output inductors, and the regulator pins shall be minimized. GND, AGND, DGND pins shall be connected to the signal ground plane. Compensation networks shall be placed close to the pins and referenced to the signal ground. V CC bypass capacitor shall be placed close to the pin. 5/9

16 XR773-AR Applications Information (Continued) Typical Applications V OUT3 L OUT _CH3 V IN V IN RT_CH3 RB_CH3 FB3 C OUT _CH3 C IN _CH3 V IN3 CBST_CH3 C_IN EN SY C_IN RGND V IN3 V CC RC_CH3 CP_CH3 CP_CH CC_CH3 C VCC FB3 V CC V IN E-PAD 33 BST3 3 VIN3 3 LX3 3 LX3 9 VIN 8 AGND 7 EN 6 SY 5 VFB3 COMP3 VIN GND VCC COMP VFB XR773-AR PGOOD 4 3 DGND 9 COMP 8 VFB 7 RPG PG CP_CH RC_CH CC_CH BST VIN LX LX VIN BST CC_CH RC_CH FB FB V IN V IN V IN V IN C IN _CH C IN _CH V OUT L OUT _CH CBST_CH CBST_CH L OUT _CH V OUT RT_CH C OUT _CH C OUT _CH RT_CH FB FB RB_CH RB_CH Figure 3. Typical Applications Schematic 6/9

17 XR773-AR Mechanical Dimensions TOP VIEW BOTTOM VIEW SIDE VIEW TERMINAL DETAILS Drawing No.: POD-79 Revision: C 7/9

18 XR773-AR Recommended Land Pattern and Stencil TYPICAL RECOMMENDED LAND PATTERN TYPICAL RECOMMENDED STEIL Drawing No.: POD-79 Revision: C 8/9

19 XR773-AR Order Information () Part Number Operating Temperature Range Lead-Free Package Packaging Quantity XR773ELB-AR XR773ELBTR-AR XR773EVB-AR -4 C T J 5 C Yes () 3-pin, 4mm x 4mm TQFN package XR773-AR evaluation board Bulk Tape and Reel NOTE:. Refer to www/exar.com/xr773-ar for most up-to-date Ordering Information.. Visit for additional information on Environmental Rating. Revision History Revision Date Description A 3/9/6 Initial Release B //7 Added MaxLinear logo. Updated format and ordering information format. Changed Packaging Description section name to Mechanical Dimensions and Recommended Land Pattern and Stencil. Corrected typo on Mechanical Dimensions, dimension A. Added revision history. Corporate Headquarters: 5966 La Place Court Suite Carlsbad, CA 98 Tel.:+ (76) 69-7 Fax: + (76) High Performance Analog: 6 Rincon Circle San Jose, CA 953 Tel.: + (669) 65-6 Fax: + (669) powertechsupport@exar.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc. Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances. MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these patents, trademarks, copyrights, or other intellectual property. Company and product names may be registered trademarks or trademarks of the respective owners with which they are associated. 6-7 MaxLinear, Inc. All rights reserved XR773-AR_DS_7 9/9