AN1610 APPLICATION NOTE POWER LOGIC 8-BIT ADDRESSABLE

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1 AN161 APPLICATION NOTE POWER LOGIC 8-BIT ADDRESSABLE S. Lupo 1. ABSTRACT The aim of this work is to give a clear and exhaustive overview of the operation of STPIC6A259. From the applications point of view, particular attention is given to the thermal behavior and both the values of the junction-ambient thermal resistance (Qja) and the maximum dissipation power (Pd) are verified. These values are obtained as a function of the maximum reachable temperature of the DIE (15 C) and the geometry of cooling fin on the PCB. This application note involves the realization of an inner virtual thermometer and that of boards with cooling fins of different dimensions. This last point is necessary to determine the optimal geometry that defines the maximum dissipation power operating in the same conditions. 2. SHORT REFERENCE: - 3: STPIC6A : Description 2-3.2: Characteristics 3-3.3: Operation modes 4-4: OPERATING MODE 4-4.1: Dissipation power 4-4.2: Internal thermometer 5-4.3: Dissipation power and cooling fin 6-4.4: Used instrumentation 7-4.5: Measures 8-4.6: Thermal resistance 13-5: CONCLUSION: 14-6: APPENDIX: STPIC6A259 STPIC6A259 is "8-bit addressable latch" power logic that controls open drain DMOS transistor outputs. It is a multifunctional device capable of operating as eight addressable latches or an 8-line demultiplexer with active-low DMOS outputs. STPIC6A259 is generally designed for storage applications in digital systems. Specific uses include working registers, serial-holding registers and decoders or demultiplexers. November 22 1/16

2 3.1 DESCRIPTION To make clear the structure and the operation of STPIC6A259, the following figures show a block diagram configuration and a functional logic scheme: Figure 1: Block Diagram VCC LGND PGND PGND S S1 S2 D Decode Logic Current limit + Chargepump G CLR PWM Control PGND PGND Figure 2: Power Logic 8-bit Addressable Latch 2/16

3 STPIC6A259 has six input pins: three (S, S1, S2) are used to address one or more outputs; one is the data pin (D) and the remaining two pins are used to select the operating mode of this device (G, CLR). The other pins present in STPIC6A259 are supply pins, power ground pin, used for heat dissipation, and output pins (see Fig. 1). Fundamental part of this device is the "Decode logic block" (see fig 1). Current limit and PWM (Pulse Wide Modulation) characterize the short circuit protection, while the charge pump and the 8 DMOS represent the output block of the device. The Decode logic block sends the information on the D input pin to one or more of the 8 DMOS (see Fig.1), by means of the 3 pins addressed S, S1, S2 using the control pins to select the operating mode (see Fig.2). The operating logic of this block is described in the following table: Table 1: Operating Logic Output addressed Output not addressed Function Input CLR G D H L H H L L H H X L H Old configuration Old configuration Addressed Old configuration Memory Condition L L H L L L L H X L H H (output latch to zero) H (outputs latch to zero) H c 8-line demultiplexer Reset This control logic is based on the use of eight D-type latches. Current limit is a static protection; it fixes the maximum current value that flows in each channel (DMOS) at 8mA. When it is active, simultaneously, an alarm signal for the PWM is generated. This is a dynamic protection because it drives the gates of the DMOS in fault condition with a low duty-cycle pulse train that switches it on and off until that condition persists. In this way the device limits the power dissipation. An innovation of the STPIC6A259 is the output block. It is realized with DMOS transistors driven by a charge pump. This is because it is possible to obtain an R DSon = 1Ω driving the gate of the DMOS with a voltage ( 9.8 V) twice that of power supply. 3.2 CHARACTERISTICS Peculiar characteristics of such a device are: - Low RDSon (1Ω typical) - Output Short-circuit protection (PWM+current limit) - Eight 35mA DMOS outputs - Low power consumption - Four distinct function modes Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system flexibility. All PGND terminals are internally connected, and each of them must be externally 3/16

4 connected to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND and PGND must be made externally in such a way that cross-talk between the logic and the load circuits is reduced. The STPIC6A259 is offered in a thermally enhanced SO-24 batwing package. The STPIC6A259 has an operating case temperature range of -4 C to 125 C. 3.3 OPERATION MODES It is possible to choose from four distinct operation modes controlling the clear (CLR) and enable (G) inputs. In the addressable latch mode (CLR=1; G=), the data is written into the addressed latch. The addressed DMOS-transistor output inverts the data input, while all unaddressed DMOS-transistor outputs remain in their previous state. In the memory mode (CLR=1; G=1), the MOS-transistor outputs remain in their previous states and are unaffected by the data or addressed inputs. To eliminate the possibility of entering erroneous data in the latch, enable G should be held high (inactive) while the address lines change. In the 8-line demultiplexer mode (CLR=; G=), the addressed output is inverted with respect to the D input and all the other outputs are high (more input one output). In the clear mode (CLR=; G=), all outputs are high and unaffected by the address and data inputs. 4. OPERATING MODE Purpose of this chapter is to verify the value of the junction-ambient thermal resistance (Θja) and the maximum power dissipation (Pd) in relation to the maximum reachable temperature of the DIE and the type of cooling fin used. 4.1 POWER DISSIPATION Whenever current flows in a device, work is done, and power is dissipated. This power is the result of the product of the current that flows in it and the drop voltage on its end. For the energy conservation principle the absorbed power is transformed into heat causing an inner warm-up of the device. Attention must be paid to the fact that this warm-up can cause the destruction of the device if the rise in temperature is excessive. This phenomenon depends on the dissipation capacity of the heat developed into external environment. For this purpose, the thermal resistance concept, which measures the heat difficulty to propagate outside, is introduced. It is measured in C/W and represents the increase in C of the temperature with respect to ambient temperature for each W of dissipated power. For example: if the thermal resistance is 5 C/W, the junction temperature increases of 5 C when the dissipated power of the device is one watt. Fixed Tj as junction temperature, it will be equal to the ambient temperature Ta if no voltage is applied to the device; alternatively, a proportional term for the dissipated power could be considered. So: where Θ is the thermal resistance. Tj = Ta + Θ x Pd [4.1] 4/16

5 Θ can be considerate as sum of two terms: Θ = Θ i + Θ e where Θ i is the inner thermal resistance of the junction to the case, and Θ e is the external thermal resistance between the case and the ambient. The inner thermal resistance depends on the geometry and the construction of the semiconductor element, on the material interposed between the semiconductor element and the case, and on the material used for the case. The external thermal resistance, instead, depends on how the heat is taken away from the case. This happens simultaneously through: - Radiation - Conduction (through the terminal or the contact between some parts of the case with other larger size metals) - Convection of surrounding air in contact with the case. As a result, to determine the junction ambient thermal resistance is necessary to define the internal temperature of the device. 4.2 INTERNAL THERMOMETER It is possible to check the inner temperature using the voltage-current relation of the diode. This relation depends implicitly on the temperature, so the following relation for constant current is valid: dv/dt~ - 2.mV/ C: increasing the temperature causes the voltage on the diode to decrease in a linear mode. If there is no power dissipation in the device, forcing a very small current (1µA) in the diode, it is possible (see formula 4.1) to ignore the ΘxP d term obtaining Tj = Ta. The protection diode placed on the D data input pin has been used for the temperature measurement. Thermal inductive system (see 4.4) is used to condition the ambient temperature of the device. Figure 3: Virtual Inner Thermometer Vdiode (mv) Temperature 5/16

Table 2: Virtual Inner Thermoter Tj = Ta ( C) Vdiode (mv) -4 744 1 634 25 64 3 594 4

the device operating on the external thermal resistance, that is, on the mode to

How does the STPIC6A259 behavior change in relation to a different geometry and to a

6 Table 2: Virtual Inner Thermoter Tj = Ta ( C) Vdiode (mv) DISSIPATION POWER AND COOLING FIN It is possible to improve the thermal behavior of the device operating on the external thermal resistance, that is, on the mode to dissipate the heat outside. This mode is based on the use of appropriate cooling fins. How does the STPIC6A259 behavior change in relation to a different geometry and to a different surface of the cooling fin? The following figures represent the different boards used for the study of the device with the relative fins. Figure 4: Demoboards 6/16

7 The study has been focused on three dimensions:.5 cm 2, 3 cm 2 and 6cm 2. These values try to incorporate the best and the worst case scenarios concerning the effects on dissipation (note: the dissipate effect does not change over a certain value of the fin surface). In relation to the intermediate measure (3cm 2 ) it has been realized a study on a different geometry considering a different fin part under the package. The results of this study will show that a larger fin under the package considerably improves the behavior of the device, due to the conductive effect present under the package, which helps dissipation from the fin to the air. 4.4 USED INSTRUMENTATION - Thermal Inducing Systems: TEMPTRONIC The TP43A model, a high power, full-featured air stream system, delivers controlled temperature with speed and precision to small and large devices, modules, PCBs and assemblies for thermal cycling, profiling and testing. Temperature Range: -8 to +225 C - Model 242 High-Current Source Meter/Measurements up to 6V and 3A, 6W Power Output: KEITHLEY The 242 High Voltage Source Meter model is a 6W instrument designed to source and measure voltage from ±5µV (source) and ±1µV (measure) to ±6V and current from ±1pA to ±3A. It has.12% basic accuracy with 5-1/2-digit resolution for precise measurements. - Tektronix PS2521G Power Supply PS2521G is provided with triple outputs; these output Power Supplies are versatile supplies suitable for many applications. The PS2521G has a single supply providing a maximum of 6 V and 3 A and two supplies providing a maximum of 36 V and 1.5 A. The supplies can be used in one of the following modes: independent, series or parallel. In the independent mode, the output voltage and current of each supply are controlled independently. In the two tracking modes, the variable outputs are connected either in series or in parallel; the control of the master power supply adjusts the voltage or current of both power supplies. 7/16

8 4.5 MEASURES The following figures show the representation of the chosen instruments connection and the relative electric scheme. Figure 5: Instruments Connectionl POWER C PC SMU V Sense GND Vcc GND SMU +32 mv S S1 S2 D CLR G GND Interface card Board under test Figure 6: Electric Sheme VCC DRAIN DATE SENSE SMU V SMU Note: It is necessary to guarantee a flow of air under the board. 8/16

9 In order to force a current above the limit fixed by the instrumentation (3 A) it has been realized a SMU using a KEYTHLEY power supply (228A voltage/current source 1V/1 A) and a voltmeter in parallel to it (see fig. 6). Using the measure bench (see fig. 5) and an oscilloscope to verify the triggering of the PWM protection and a thermal inducing system to simulate the working ambient conditions of the device, it has been possible to obtain the relative information on the drop voltage of the diode, as well as put in protection for the data pin and drains when active. Figure 7: Dissipated Power by the device with 8 active channels: Ta = 25 C, cooling fin.5cm2 2,5 2, 1,5 1, Vdrain (mv) Pd (mw) Idrain (A) - Maximum dissipated power of the device changing active channels number and work ambient temperature (cooling fin.5cm 2 ): Figure 8: Maximum Dissipated Power increasing the channels number Pd (W) Ta=25 C Ta=85 C Ta=125 C N of channels 9/16

10 Figure 9: Dissipated Power for every single channel Pd (W) N of channels Ta=25 C Ta=85 C Ta=125 C Note: Decreasing the channels number, if the short-circuit protection is activated, the maximum dissipated power indicates the limit value reached before the device protection is on. As the channels number rises, the capacity to draw current increases, whilst the total drop voltage decreases due to the drop in internal resistance when the 8 MOS devices are connected in parallel. Consequently, the dissipated power decreases when the number of active channels increases. Every channel is current limited, giving both passive and active protection. Therefore if the device is not able to dissipate the power, the protection activates itself before achieving the test condition (Tj=15 ). - Maximum dissipated power of the device changing the active channels number and the work ambient temperature (cooling fin 3cm 2 1): Figure 1: Maximum dissipated power increasing the channels number Pd (W) Ta=25 C Ta=85 C Ta=125 C N of CHANNELS 1/16

11 Figure 11: Dissipated power for every single channel Pd (W) Ta=25 C Ta=85 C Ta=125 C N of Channels Figure 12: Comparison between maximum dissipated power of the device changing the active channels number and the cooling fin under test (6cm 2 // 3 cm 2 2). Pd (W) N of CHANNELS Ta=25 C 6cm² Ta=125 C 6cm² Ta=25 C 3cm² (2) Ta=125 C 3cm² (2) This chart shows that there is no difference in the behaviour of the cooling fin (3cm 2 // 6cm 2 ). It is very important to use a large cooling fin under the package. 11/16

12 - Comparison between each board Figure 13: Dissipated power increasing the channels number and operating under the same condition for each channel and board Pd (W) N of CHANNELS 3cm² (1) 3cm² (2) 6cm² Figure 14: Thermal behaviour for each board Ta ( C) Pd (W) 3cm2 (1) 3cm2 (2) 6cm2 These charts show that when forcing the same current into each channel, the power dissipation is the same, but if different cooling fins are used the thermal behavior changes: the internal temperature decreases if the surface of cooling fin increases. 12/16

13 4.6 THERMAL RESISTANCE The relative data for this measure are reported below: Table 3: Data referring to the measures applied (Ta=25 C) N CH I forz. (A) Vdrain (V) V diode (mv) T j P diss (W) Θ ja Derating Coeff. (mw/ C) Table 4: Data referring to the measures applied (Ta=125 C) N CH I forz. (A) Vdrain (V) V diode (mv) T j P diss (W) Θ ja Table 5: Data referring to the measures applied (Ta=85 C) N CH I forz. (A) Vdrain (V) V diode (mv) T j P diss (W) Θ ja Derating Coeff. (mw/ C) /16

14 Figure 15: Thermal Resistance Θja ( C/W) Ta=125 C Ta=85 C Ta=25 C N of CHANNELS This chart shows the pattern of the thermal resistance when the channels number and the ambient temperature are changed. At Ta=25 or 85 C, these patterns are not linear, because the device with one or two channels is not able to reach the maximum measurement condition (Tj=15 C). The device protection is active. These tables show the derating coefficient as well. This value allows us to calculate the maximum dissipation power of the device if the ambient temperature is increased with respect to "nominal" value (25 C or 85 C). The derating coefficient is measured in W/ C. Derating Coeff. = Pd / (Tamax-Tamin) For each ambient temperature step (one Celsius-degree) the maximum power dissipation is obtained as showed below: Pd(Tx)= Pd(25 C) + Der.Coeff. x (Tx-25 C) Table 1 shows the derating coefficient relative to Ta min/max =25 85 C. Table 2 shows the derating coefficient relative to Ta min/max = C. Those intervals are necessary because the coefficient is not linear. 5. CONCLUSION STPIC6A259 is a power logic device that allows us to address, to maintain and to demultiplexer data, using 8 MOS connected in parallel. Maximum dissipated power is: 898mW with eight active channels, Ta = 25 C and without cooling fin (.5cm 2 ). It is not necessary to use a very large cooling fin but it is important to use a greater portion of cooling fin under the package. The derating coefficient for the thermal resistance has been calculated as: 25 C / 85 C, 8 active channels 14.96mW/ C 85 C / 125 C, 8 active channels 6.93mW/ C 14/16

15 6. APPENDIX Cooling fin dimensions 1.5c m 2 = 2mm x 5mm 1 = 4mm x 5mm c m 2 (1) = 2mm x 6mm 1 = 3.4mm x 5mm 2 = 2.3mm x 1mm 3 = 4mm x 23mm cm 2 (2) = 12mm x 5.5mm 1 = 3.7mm x 5mm 2 = 2.2mm x 1mm 3 = 3mm x 25.5mm c m 2 = 12mm x 5.5mm 1 = 3.7mm x 5mm 2 = 3.65mm x 1mm 3 = 7mm x 3.6mm 15/16

16 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 22 STMicroelectronics - Printed in Italy - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 16/16

M74HC259TTR 8 BIT ADDRESSABLE LATCH

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