Design of a QR Adapter with Improved Efficiency and Low Standby Power

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Hilary Theresa Davidson
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1 Design of a QR Adapter with Improved Efficiency and Low Standby Power

2 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

3 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

4 What is Quasi-Square Wave Resonance? MOSFET turns on when V DS (t) reaches its minimum value. Minimizes switching losses Improves the EMI signature valley MOSFET turns on in first valley MOSFET turns on in second valley

5 Quasi-Resonance Operation In DCM, V DS must drop from (V in + V reflect )to V in Because of L p -C lump network oscillations appear Oscillation half period: t = π L C x p lump Vin Lp Cout Rload 1 : N Vout V DS V in + V reflect Vin V in VDS SW Clump

6 A Need to Limit the Switching Frequency In a self-oscillating QR, F sw increases as the load decreases Higher losses at light load if F sw is not limited 2 methods to limit F sw : Frequency clamp with frequency foldback Changing valley with valley lockout

7 Frequency Clamp in QR Converters QR mode Second valley First valley In light load, frequency increases and hits clamp Multiple valley jumps Jumps occur at audible range Creates signal instability

8 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

9 The Valley Lockout As the load decreases, the controller changes valley (1 st to 4 th valley in NCP1380) The controller stays locked in a valley until the output power changes significantly. No valley jumping noise Natural switching frequency limitation VCO mode SWITCHING FREQUENCY (Hz) th 3 rd 2 nd 1 st QR operation VCO mode OUTPUT POWER (W)

10 The Valley Lockout FB comparators select the valley and pass the information to a counter. The hysteresis of FB comparators locks the valley. 2 possible operating set points for a given FB voltage. VCO 4 th 3 rd 2 nd 1 st V FB (V) V FB increases (P OUT increases) V FB decreases (P OUT decreases)

11 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

12 Operating modes: NCP1379/1380 Features QR current-mode with valley lockout for noise immunity VCO mode in light load for improved efficiency Protections Over power protection Soft-start Short circuit protection Over voltage protection Over temperature protection Brown-Out Rzcd2 Czcd Rzcd1 ZCD / OPP FB CS GND HV-bulk Ct NCP1380 C/D OVP/BO 7 Vcc 6 Rstart DRV Ct Cvcc Rbou Dovp Rbol Mass production: Q4 2009

13 QR Mode with Valley Lockout Operating principle: Locks the controller into a valley (up to the 4 th ) according to FB voltage. Peak current adjusts according to FB voltage to deliver the necessary output power. VCO mode 1.40E E+05 VCO mode Fsw (Pout) for a 60 W adapter QR operation 1.00E Fsw (Hz) 8.00E E E E E+00 4 th 3 rd 2 nd Pout (W) 1 st Advantages Solves the valley jumping instability in QR converters Achieves higher min F sw and lower max F sw than in traditional QR converters Reduce the transformer size

14 VCO Mode Occurs when V FB < 0.8 V (P out decreasing) or V FB < 1.4 V (P out increasing) Fixed peak current (17.5% of I pk,max ), variable frequency set by the FB loop. I pk max Constant peak current (17.5% of I pk max) F P out1 F P out2 P out1 > P out2

15 Combined ZCD and OPP Zero-Crossing Detection (ZCD) and Over Power Protection (OPP) are achieved by reading the Aux. winding voltage ZCD function used during the off-time of MOSFET (positive voltage). OPP function used during the on-time of MOSFET (negative voltage) Rzcd 1 Aux Ropu Ropl ZCD/OPP 1 ESD protection + CS 0.8 V + Vopp 0.8 V + - IpFlag 0 V 50 mv V ZCD + Possible restarts for ZCD V OPP - Demag Vth DRV leakage blanking Tblank V DRV 2

16 NCP1380 Versions 4 versions of NCP1380: A, B, C and D OTP OVP BO Auto-Recovery Over current protection Latched Over current protection NCP1380 / A X X X NCP1380 / B X X X NCP1380 / C X X X NCP1380 / D X X X OTP: Over Temperature Protection OVP: Over Voltage Protection BO: Bown-Out

17 Short-Circuit Protection Internal 80 ms timer for short-circuit validation. Additional CS comparator with reduced LEB to detect winding short-circuit. V CS(stop) = 1.5 * V ILIMIT S Q Q DRV R CS LEB1 + PWMreset Rsense FB/4 - Down ZCD/OPP OPP IpFlag Up TIMER Reset Stop controller Laux LEB2 V ILIMIT + CsStop grand reset - V CS(stop)

18 Short-Circuit Protection (A and C versions) A and C versions: the fault is latched. V CC is pulled down to 5 V and waits for ac removal. S Q DRV Q Vdd R aux latch VCC management Vcc CS after LEB1 + FB/4 V ILIMIT + V OPP CS after LEB PWMreset IpFlag CSstop Down Up CSstop TIMER Reset S Q Q fault grand reset VCCstop SCR delatches when I CC < ICC LATCH - t LEB2 < t LEB1 V CS(stop) grand reset R

Short Circuit Protection (B and D) Auto-recovery short circuit protection: the controller tries to restart Auto-recovery imposes a low burst in fault mode.

19 Short Circuit Protection (B and D) Auto-recovery short circuit protection: the controller tries to restart Auto-recovery imposes a low burst in fault mode. Low average input power in fault condition S Q Q to DRV stage Vdd aux R VCC management Vcc CS after LEB1 FB/4 V ILIMIT + V OPP PWMreset IpFlag Down Up grand reset TIMER Reset fault grand reset VCCstop V CC CS after LEB2 + CSstop V DS V CS(stop) - t LEB2 < t LEB1

20 Fault Pin Combinations OVP / OTP NCP1380 A & B versions V Fault OVP / BO NCP1380 C & D versions, NCP1379 V Fault Latch! Latch! OK OK Latch! time BO time OVP and OTP or OVP and BO combined on one pin. Less external components needed.

21 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

22 Step by Step Design Procedure Calculating the QR transformer Predicting the switching frequency Implementing Over Power Compensation Improving the efficiency at light load with the VCO mode Choosing the startup resistors Implementing synchronous rectification

23 Design Example Power supply specification: V out = 19 V P out = 60 W F sw,min = 45 khz (at V in = 100 Vdc) 600 V MOSFET V in = 85 ~ 265 Vrms Standby power consumption < Vrms Vbulk T1.. Vout Gnd

24 Turns Ratio Calculation Derate maximum MOSFET BV dss : V = BV k ds, max dss D k D : derating factor For a maximum bulk voltage, select the clamping voltage: BV dss V ds,max V os 15% derating V = V V V clamp ds, max in, max os V reflect V clamp V os : diode overshoot V bulk,max Deduce turns ratio: N ps N s = = N p k ( V + V ) c out f V clamp k c : clamping coef. k c = V clamp / V reflect )

25 How to Choose k c k c choice dependant of L leak (leakage inductance of the transformer) k c value can be chosen to equilibrate MOS conduction losses and clamping resistor losses. 3 P Rclamp 600-V MOSFET 2 P V in,min P loss (W) 1 P tot 2.5 W k leak =0.01 k leak =0.008 k leak =0.005 P P Rclamp Pout kc = kleak η kc 1 2 4P out 1 kc = Rdson + 3η V, V, BV k V, V MOS, on k c in min in min dss D in max os Curves plotted for: R dson = 0.77 Ω at T j = 110 C P out = 60 W V in,min = 100 Vdc

26 Primary Peak Current and Inductance 1 2 Pout = LpriIpri, peak Fswη 2 DCM I pri,peak 0 t on t off t v t on t off t v T I L I L N pri, peak pri pri, peak pri ps sw = + +π LpriClump Vin, min Vout + Vf C oss contribution alone. I pri, peak P 1 N 2P C F out = π η Vin,min Vout V + f η ps out lump sw L pri = I 2P out 2 pri, peak F η sw

27 RMS Current Calculate maximum duty-cycle at maximum P out and minimum V in : d max = I pri, peak V L in, min pri F sw, min Deduce primary and secondary RMS current value: I = I pri, rms pri, peak d 3 max I sec, rms = I pri, peak N ps 1 d 3 max I pri,rms and I sec,rms Losses calculation

28 Design Example Based on equations from slides 11 to 14: Turns ratio: N ps kc ( Vout + Vf ) 1.3 ( ) = = Nps 0.25 B k V V Vdss D in, max os Peak current: Inductance: Max. duty-cycle: I pri, peak 2P 1 N 2P C F out = + + π η Vin,min Vout V + f η ps out lump sw p 45k = + + π Ipri, peak = 3.32 A P 2 60 Lpri = = L pri = 285µH I F k 0.85 out 2 2 pri, peak swη I L µ d = F = 45 k d = 0.43 pri, peak pri max sw, min max Vin, min 100 dmax 0.43 Primary rms current: Ipri, rms = Ipri, peak = 3.32 Ipri, rms = 1.26A 3 3 Secondary rms current: I 1 d I = = I = 5.8 A pri, peak max sec, rms sec, rms N ps

Design of a QR Adapter with Improved Efficiency and Low Standby Power

Design of a QR Adapter with Improved Efficiency and Low Standby Power Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/1380 4. Step by Step Design Procedure 5.