LD5718AC 09/22/2016. Primary-Side Quasi-Resonant Controller, Operating in CV/CC Mode. Features. General Description. Applications. Typical Application

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1 REV. 00 General Description Primary-Side Quasi-Resonant Controller, The is a primary-side Quasi-Resonant controller capable of operating in CV/CC mode for small to medium power AC/DC charger and adapter. When paired with LD8108A, the will support speedy charger design for MediaTek Pump Express Plus based and Qualcomm Quick Charge 2.0 based protocol. Using Leadtrend Speedy Charge technology, it will be easy to minimize the component counts. The can be programmed constant voltage output which only require single photo-coupler by LD8108. Also, the features external/internal OTP (Over Temperature Protection), wide-range and output voltage level OVP (Over Voltage Protection) etc., to prevent the circuit from being damaged under abnormal conditions. The is available in a SOP8 package. Typical Application Operating in CV/CC Mode Features Speedy Charge technology Normally 5V output Programming output voltage from 5V to 12V Meet DoE level-vi CoC V5 tier2 efficiency Specificated constant current control Adjustable load regulation compensation Built-in HV start-up control for depletion NMOS Ultra-low start-up current 1.5 A Max. LEB (Leading-Edge Blanking) on Pin OVP (Over Voltage Protection) on Applications AC/DC Speedy Charger for Smart Phone and Tablet (5V-12V, 1A-2A) AC Input AC Input EMI Filter ST OPTO/ OTP NTC Traditional PSR Charger and Adaptor Design -DS-00 September

2 AC Input AC Input EMI Filter OPTO/ OTP ST DIS DET LD8107 NTC MediaTek Pump Express Plus Charger Combined with LD8107 which is a Secondary-Side Discharging IC AC Input AC Input EMI Filter OPTO/ OTP ST NTC DIS LD8108A DET D+ OPTOD OTD D-- NTC Qualcomm Quick Charge 2.0 Combined with LD8108A which is a Secondary-Side Controller -DS-00 September

3 ST OPTO/ OTP Pin Configuration SOP-8 (TOP VIEW) TOP MARK YYWWPP YY: Year code (D:2004, E2005 ) WW: Week code PP: Production code Ordering Information Part number Max. output current limit ratio Min. Frequency Max. Frequency Package Top Mark Shipping 5V 1 GS 9V 1 12V 1 800Hz 100kHz SOP-8 GS 2500 /tape & reel The series are ROHS compliant/ Green Packaged. Protection Mode Part number _OVP UVP OSCP OTP Auto Auto Auto Auto Pin Descriptions Pin NAME FUNCTION 1 ST HV startup driver 2 Output of the error amplifier for voltage compensation 3 (1) Output Voltage Feedback, (2)QRD Detection 4 OPTO/OTP (1) External OTP, (2)Output Regulation Setting Interface 5 Current Sense Pin, connect to sense the MOSFET current 6 Gate Driver 7 Ground 8 Supply voltage pin with OVP function -DS-00 September

4 Block Diagram UVLO On/Off OVP Startup Control PG ST LDO PG Protection Gate Driver Out Internal Supply Max. Fsw and Green Mode PWM Logic Protection Load Compensatio n Vref GM V CV Control V S/H UVP Protection CC compensatio n QRD CC Control LEB OPTP /OTP Vref up/down control Vref + - Int. OTP Ex. OTP Protection -DS-00 September

5 Absolute Maximum Ratings Supply Voltage, ST, -0.3V ~ 30V -0.3V ~ 30V,, OPTO/OTP, -0.3V ~ 4.0V (AC current 1mA) -0.7V ~ 4.0V Maximum Junction Temperature Storage Temperature Range Package Thermal Resistance (SOP-8, JA) Power Dissipation (SOP-8, at Ambient Temperature = 85 C) Lead temperature (Soldering, 10sec) ESD Voltage Protection, Human Body Model ESD Voltage Protection, Machine Model Gate Output Current 150 C -65 C ~ 150 C 160 C/W 250mW 260 C 2.5kV 250V +120mA/-200mA Caution: Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stress above Recommended Operating Conditions may affect device reliability. Recommended Operating Conditions Item Min. Max. Unit Operating Junction Temperature C Capacitor F Pin Capacitor pf Note: 1. It s essential to connect pin with a SMD ceramic capacitor (0.1 F ~ 0.47 F) to filter out the undesired switching noise for stable operation. This capacitor should be placed close to IC pin as possible 2. Connecting a capacitor to pin is also essential to filter out the undesired switching noise for stable operation. 3. The small signal components should be placed to IC pin as possible. -DS-00 September

6 Electrical Characteristics (T A = +25 C unless otherwise stated, =12.0V) PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS Supply Voltage ( Pin) Startup Current =UVLO(ON) - 50mV I CC_ST A Operating Current V =0V, =open, =2V I CC_OP ma OVP/ UVP tripped, =0V I CC_OPA ma UVLO(OFF) V CC_OFF V UVLO(ON) V CC_ON V OVP Level V CC_OVP V Error Amplifier ( Pin) Reference Voltage, V REF For 5V output V REF_5V V For 9V output V REF_9V V Load Compensation Current V =2.5V I LOAD_ A Current Sensing ( Pin) Maximum Input Voltage, V -OFF V _MAX V Minimum V -OFF V < 0.45V V _MIN V Leading Edge Blanking Time T LEB ns QRD (Quasi Resonant Detection, Pin) QRD Trip Level Oscillator for Switching Frequency * V QRD mv Hysteresis,* V QRD_HYS mv Maximum Frequency F SW_MAX khz Minimum Frequency F SW_MIN khz Output Drive ( Pin) Maximum On Time T ON_MAX s Under Voltage Protection (UVP, Pin) Under Voltage Level for 5Vo V _UVP5VO V UVP Delay Time After soft start,* T D_UVP 100 ms On Chip OTP (Over Temperature) OTP Level * T INOTP C OTP Hysteresis * T INOTP_HYS C -DS-00 September

7 PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS OPTO/OTP Pin OTP Pin Source Current I OTP µa Over Temperature Threshold * V OTP V Over Temperature Release Threshold * V OTP_R V *: Guaranteed by design. -DS-00 September

8 Typical Performance Characteristics -DS-00 September

9 -DS-00 September

10 Application Information Operation Overview The is an excellent primary side feedback controller with Quasi-Resonant operation to provide high efficiency and better EMI performance. The removes the need for secondary feedback circuits while achieving excellent line and load regulation. They meet the Green Power requirements and are intended for the use in those modern switching power suppliers and linear adaptors that demand higher power efficiency and power-saving. They integrate with more functions to reduce the external component counts and the size. Their major features are described as below. Under Voltage Lockout (UVLO) An UVLO comparator is implemented to detect the voltage across pin. It would assure the supply voltage high enough to turn on the PWM controller and further to drive the power MOS. As shown in Fig. 11, a hysteresis is built in to prevent shutdown from voltage drop during startup. Therefore, the current through R1 will be used to charge the capacitor C1. Until the is fully charged to enable the and to deliver the drive-out signal, the auxiliary winding will provide the supply current instead. If PWM controller requires more current to start up, it can use external depletion NMOS, M1, which is controlled by ST pin and will provide ~ma to reduce the start-up time. For cost saving, user can skip the depletion MOS, M1, and let the ST pin be floating. By using CMOS process and some unique circuits design, the themself require only 1.5 A max to start up without using external depletion MOS. Higher resistance of R1 will spend much more time to start up. To save BOM cost, user is recommended to select proper value of R1 and C1 to optimize the power consumption and startup time. AC input EMI Filter Cbulk R1 M1 D1 C1 UVLO(ON) UVLO(OFF) I() operating current (~ ma) t ST Fig. 12 Startup current (depends ext. MOS) Principle of CV Operation Fig. 11 HV Startup Current and Circuit The typical HV startup circuit generates of the is shown in Fig. 12. During startup, the sinks below the UVLO threshold, so there s no pulse delivering out from to drive the power MOS. t In the DCM Flyback converter, it senses the output voltage by auxiliary winding. samples the auxiliary winding on the primary-side to regulate the output voltage, as shown in the Fig. 13. The voltage induced in the auxiliary winding is a reflection of the secondary winding voltage while the power MOS is in off state. Via a resistor divider connected between the -DS-00 September

11 auxiliary winding and pin, the auxiliary voltage is sampled after a sample delay time and will be hold until the next sampling. The sampled voltage is compared with internal reference V REF and the error will be amplified. The error amplifier output reflects the load condition and controls the duty cycle to regulate the output voltage, thus constant output voltage can be achieved. The output voltage is given as: V Ra Ns 1.0V (1 )( ) Rb Na V F where V F indicates the voltage drop of the output diode, Ra and Rb are top and bottom feedback resistor values, Ns and Na are the turns of transformer secondary and auxiliary windings. In case that the output voltage is sensed through the auxiliary winding; the leakage inductance will induce ringing to affect output regulation. To optimize the collector voltage clamp circuit will minimize the high frequency ringing and achieve the best regulation. Fig. 14 shows the desired collector voltage waveform in compare to those with large undershoot due to leakage inductance induced ring (Fig. 15). This will make the sample error and cause poor performance for output voltage regulation. A proper selection for resistor RS, in series with the RC filter, may reduce any large undershoot. supports Pump Express Plus TM fast charge agreement, the MCU can send current pattern to increase the charger output voltage, as shown in the Fig. 16. This method can achieve the effect of fast charging time. Ra Rb Na VIN VREF + - S/H V DS V DS Driver Fig. 13 Np The overshoot here is minor Fig. 14 Ns The undershoot would make the sample error. Fig. 15 supports Speedy Charge TM, it can receive digital signal form secondary side controller (ex: LD8108A) to set output voltage to 5V, 9V, 12V, as shown in the Fig 16. OPTO/ OTP Vcc LD8108A OPTO D+ D- Fig. 16 -DS-00 September

12 Load Regulation Compensation implements load regulation compensation circuit to compensate the cable voltage droop and achieve a better voltage regulation. The offset voltage is created across pin by an internal sink current source which feeds out the pin during the sampling period. The internal sink current source is proportional to the value of V, as shown in Fig. 17. As a result, the drop due to the cable loss can be compensated. So that, the offset voltage decreases as the V decreases in condition from full-load to no-load. It can also be programmed by adjusting the resistance of the divider to compensate the drop for various cable lines used. The equation of internal sink current source is shown as below. I ( V 0.45)*20 ( A) The percentage of maximum compensation is shown as below. 20 V I (Ra //Rb) 100% Vo 2 I ( A) Fig. 17 Quasi-Resonant Mode Detection V (V) The employs quasi-resonant (QR) switching scheme to switch valley-mode either in CV or CC operation. This property feature greatly reduces the switching loss and dv/dt in the entire operating range for the power supply. The QR detection block will detect auxiliary winding signal to drive power MOS as pin voltage drops below 0.1V. The QR comparator would not operate if pin voltage remains above 0.3V. The 4ms of time-out-2 generates a power MOS turn-on signal as the driver output drops to low level for more than 4ms with the falling edge of the driver output. Multi-Mode Operation The is a QR controller operating in multi-modes. The controller changes its operation modes according to line voltages and load conditions. At heavy-load (V >1.6V, Fig. 18), there might be two situations to meet. If the system AC input is in low line, the will turn on in first valley. If in high line, the switching frequency will increase till over the clamp of 100kHz and skips the first valley to turn on in 2 nd valley. The switching frequency would vary depending on the line voltage and the load conditions when the system is operated in QR mode. At medium or light load conditions, the frequency clamp is reduced to 25 khz maximum as V down to V SG1. However, the valley switching characteristic behaves as well in these conditions. The will jump to turn on in 3 rd, 4 th. Valley. That is, when load decreases, the system automatically skip more valleys and the switching frequency is thus reduced. In such way, a smooth frequency fold back is realized and high power efficiency is achieved. At zero load or very light load conditions (V <0.3), the system operates in green mode for power saving. In green mode, the system modulates the frequency according to the load and V conditions. Once V is lower than V SG2, the switching frequency starts to linearly decrease from 25 khz to 800 Hz. -DS-00 September

13 fs 100kHz V IN 0.8kHz 25kHz Green Mode Discontinuous with valley switching (2 nd,3 rd,4 th... Valley) Quasi Resonant (First Valley) V Fig. 18 Current Sensing and Leading-edge Blanking The typical current mode of PWM controller feedbacks both current signal and voltage signal to close the control loop and achieve regulation. As shown in Fig. 19, the detects the primary power MOS current from the pin, which is not only for the peak current mode control but also for the pulse-by-pulse current limit. The maximum voltage threshold of the current sensing pin is set at 1V. From above, the power MOS peak current can be obtained as below. 1V IPEAK (MAX ) RS A leading-edge blanking (LEB) time is included in the input of pin to prevent the false-trigger from the current spike. can deliver more constant current at high input voltage than at low input voltage. To compensate this, an offset voltage is added to the RS signal by an internal current source (I CC) and an external resistor (R 1) in series between the sense resistor (Rs) and the pin, By selecting a proper value of the resistor in series with the pin, the amount of compensation can be adjusted. The value of I CC (300μA) depends on the voltage(v >0.9V). The equation of I CC (300μA) is decreased as: V V S 300 A R ) ( 1 Ra Rb Na Fig. 19 V Principle of CC Operation R 1 Np R S Ns LEB time The primary side control scheme is applied to eliminate secondary feedback circuit or opto-coupler, which will reduce the system cost. The switching waveforms are shown in Fig. 20. The output current Io can be expressed as: 1 is,pk TDIS Io 2 TS 1 NP T i DIS P,PK 2 NS Ts 1 NP V T DIS 2 NS RS TS The primary peak current i P,PK, inductor current discharge time (T DIS) and switching period (T S) can be detected by the IC. The ratio of V *T DIS/T S will be modulated as a constant (EX:V *T DIS/T S =1/2). I O can be induced finally by Io N N N N P S P S V R S T T 1 1 R 2 However this is an approximate equation. The user S DIS may fine-tune it according to the experiment result. S -DS-00 September

14 Out switching of the power MOS until the next UVLO(ON) T S arrives. The UVP function in is an auto-recovery type protection. The Fig. 22 shows its i P operation. The UVP is disabled during the soft start. i P,PK When is regulated to some other voltages, like T ON T DIS 9Vo and 12Vo, the UVP level is set to 6.5V which i S,PK i S complies with the Qualcomm QC2.0 recommended values while the 7Vo UVP is set to 5V. is also built-in the debounce time for hundred millisecond to Fig. 20 avoid miss triggering. OVP (Over Voltage Protection) on Auto Recovery UVLO(ON) implements OVP function over pin. UVLO(OFF) As the voltage rises over the OVP threshold voltage, the output drive circuit will be shutdown simultaneously Short t thus to stop the switching of the power MOS until the next UVP Tripped UVLO(ON) arrives. The OVP function of UVP Level is an auto-recovery type protection. The Fig. 21 shows its operation. On the other hand, if the OVP condition is removed, the Vcc level will get back to normal level and the output will automatically return to the normal operation. Switching UVP Delay Time Non-Switching t Soft Start + UVP Delay Time Switching t OVP Level OVP Tripped Fig. 22 UVLO(ON) UVLO(OFF) t Switching Non-Switching Switching t Fig. 21 Under Voltage Protection ( UVP) Auto Recovery implements the UVP function over pin. If the voltage falls below 0.55V for over the delay time of UVP, the protection will be activated to stop the -DS-00 September

15 Package Information SOP-8 Symbols Dimensions in Millimeters Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ Important Notice Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should verify the datasheets are current and complete before placing order. -DS-00 September

16 Revision History REV. Date Change Notice 00 Original Specification -DS-00 September