SocketSLIC. Developer Guide. Model MTIFM. Analog Telephony Interface Module

Transcription

1 SocketSLIC Analog Telephony Interface Module Model MTIFM Developer Guide

2 Copyright and Technical Support SocketSLIC Developer Guide Analog Telephony Interface Module Model MTIFM PN S288D, Version D Copyright This publication may not be reproduced, in whole or in part, without prior expressed written permission from MultiTech Systems, Inc. All rights reserved. Copyright 27 2 by MultiTech Systems, Inc. MultiTech Systems, Inc. makes no representations or warranty with respect to the contents hereof and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, MultiTech Systems, Inc. reserves the right to revise this publication and to make changes from time to time in the content hereof without obligation of MultiTech Systems, Inc. to notify any person or organization of such revisions or changes. Check MultiTech s Web site for current versions of our product documentation. Revisions Revision Date Description A 3/7/3 First release. B 6/5/7 Updated tech support listing and repair information. C 3/26/9 Added the mechanical drawing, block diagram, developer board schematics, and Tip and Ring drawing. Changed the FCC compliance to Class A. Updated the requirement for a PolySwitch. Updated recommended components. Updated Ring voltage levels and Telecom voltage levels. Added a Regulatory and Compliance appendix. Added a list of the Developer Kit contents. Removed references to EEPROM. Added a table of SPI Access Restrictions. D 3/29/ Add new Mechanical Drawing. Trademarks The MultiTech logo and SocketSLIC are registered trademarks of MultiTech Systems, Inc. AutoWINK is a trademark of CTPX Telecommunications, Inc. All other trademarks are the property of their respective owners. Contacting MultiTech Support MultiTech Online Support Portal In order to better serve our customers, manage support requests and shorten resolution times, we have created the online web portal allowing you to submit questions regarding MultiTech products directly to our technical support team. Get answers to your most complex questions, ranging from implementation, troubleshooting, product configuration, firmware upgrades and much more. To create an account and submit a Support Case on the Portal, visit Knowledge Base and Support Services: The Knowledge Base provides immediate answers to your questions and gives you access to support resolutions for all MultiTech products. Visit our support area on the website for other support services. Technical Support Country By By Phone Europe, Middle East, Africa: support@multitech.co.uk +(44) U.S., Canada, all others: support@multitech.com (8) or (763) Warranty Warranty information can found at: World Headquarters MultiTech Systems, Inc. 225 Woodale Drive Mounds View, Minnesota 552 Phone: or ; Fax: Internet Address: MultiTech Systems, Inc. SocketSLIC Developer's Guide 2

3 Table of Contents Table of Contents Chapter Introduction... 6 Product Description... 6 Features... 7 Benefits... 8 Safety... 9 Handling Precautions... 9 Electrostatic Discharge (ESD) Caution... 9 Safety Instructions... 9 Telecom Safety Warning... 9 SocketSLIC Mechanical Drawing... Pin Description... Chapter 2 Functions and Ports... 2 Telephony Functions... 2 Analog Interface Port... 3 Digital Interface Port... 4 Control Interface Port... 5 UART Operation... 6 SPI Operation... 7 More Serial Peripheral Interface Information... 7 Special Functions... 8 Caller ID Processing... 8 Pass Loop Disconnect... 8 Autowink Operation... 8 FlashToAnswer Supervision... 8 Originate Loop Disconnect... 8 Chapter 3 Interfaces... 9 Interface With LoopStart Supervision... 9 Connection... 9 States... 9 Voltage Diagram... 9 CAS Bit Mapping... 9 Sequence of Events... 2 Foreign Exchange Subscriber LoopStart Port... 2 Foreign Exchange Office LoopStart Port Interface With ReverseBattery Supervision Sequence of Events Foreign Exchange Subscriber ReverseBattery Port Foreign Exchange Office ReverseBattery Port Interface With GroundStart Supervision Sequence of Events Foreign Exchange Subscriber GroundStart Port Foreign Exchange Office GroundStart Port... 3 Interface With LoopReverseBattery Supervision... 3 Sequence of Events Dial Pulse Terminating Port Dial Pulse Originating Port Interface With E and M Lead Supervision Sequence of Events Interface Diagrams E and M Port Pulse Link Repeater Port... 4 MultiTech Systems, Inc. SocketSLIC Developer s Guide 3

4 Table of Contents Interface With No Supervision... 4 TransmissionOnly Port Equalized TransmissionOnly Port Chapter 4 Module Registers Factory Defaults Value Ranges Individual Register Details Module Mode Register Telephony Error Register CAS Bit Status Register CAS Bit Manipulation Register CAS Bit Receive Declaration Register... 5 CAS Bit Transmit Declaration Register... 5 Interface Selection Register... 5 Ring Pattern Register Ring Frequency Register Ring Voltage Register Telecom Voltage Register Upper Ring Frequency Detection Limit Register Lower Ring Frequency Detection Limit Register... 6 Special Function Register Codec Control Register Receive Gain Register Transmit Gain Register HybridBalance Registers Receive TimeSlot Register Transmit TimeSlot Register Delay Dial Register SPI Control Register Wink Delay Register Answer Delay Register... 8 Reset Count Register Chapter 5 System Design Considerations Electromagnetic Interference (EMI) Considerations Electrostatic Discharge Control Phone Line Warning Statement for the Developer Board Chapter 6 Power Considerations Power Supply Power Dissipation Power Management PowerUp ShutDown Reset Inactive PowerOff Chapter 7 Port HookUps Chapter 8 Specifications Technical Data Characteristics Absolute Maximum Ratings Facility Interface Codes MultiTech Systems, Inc. SocketSLIC Developer s Guide 4

5 Table of Contents Appendix A SocketSLIC Developer Board SocketSLIC Developer Kit Contents LED Descriptions Dip Switches Appendix B SocketSLIC Developer Board Schematics and Recommended Parts... Developer Board Schematics... 2 Developer Board Schematics... 3 Developer Board Schematics... 4 Recommended Parts... 5 Appendix C Tip and Ring Interface... 6 Appendix D Regulatory and Compliance Statements... 7 EMC Compliance and Requirements... 7 Waste Electrical and Electronic Equipment Statement... 9 Restriction of the Use of Hazardous Substances (RoHS)... Information on HS/TS Substances According to Chinese Standards... Information on HS/TS Substances According to Chinese Standards (in Chinese)... 2 MultiTech Systems, Inc. SocketSLIC Developer s Guide 5

6 Chapter Introduction Chapter Introduction Product Description The SocketSLIC (SLIC: Subscriber Line Interface Circuit) interface module is a complete, single circuit, full featured, flexible, isolated and programmable, ready to integrate analogtopcm interface. It allows the user to choose the appropriate telephony interface when the system is configured either in manufacturing or in the field. This flexibility adds convenience, low cost and quick time to market to designing modern communication systems or updating existing telephony systems. The SocketSLIC interface module takes care of the many standard analog interfaces allowing the designer to focus on the digital design. The SocketSLIC consists of three module Interface (I/F) ports: Analog Digital Control SPI UART Control To DSP or TDM I/F Port To LOOP or Backplane Digital Analog E and M Signaling A&BCAS pins I/F Port I/F Port Facility Field Programmable Telephony interface Module The analog interface port connects to analog telephony Loop, E and M, or Dry signaling facilities. The digital interface port connects to a TDM backplane with A/Bbit signaling access for digital telephony interfaces. The control interface port connects to a synchronous Serial Peripheral Interface (SPI) or serial Universal Asynchronous Receiver and Transmitter (UART) interface. These three module interface ports allow the designer and user to choose the appropriate telephony interface when the system is configured either in manufacturing or in the field. This flexibility adds convenience, low cost, and quick time to market to designing modern communication systems or updating existing telephony systems. MTIFM takes care of the many interfaces allowing the designer to focus on other design aspects of the project. The Field Programmable Telephony interface Module MTIFM performs the functions of the following devices: Data Access Arrangements (DAA) Subscriber Line Interface Circuits (SLIC) Analog Station Cards/Trunk Line Cards (ASC/TLC) The SocketSLIC converts analog payload like voice, data, and Fax to digital Pulse Code Modulation (PCM) and converts analog telephony signaling to digital Channel Associated Signaling (CAS). The module is transparent for the following signals, tones, and modes: Addressing Signals (Dial Pulse, DTMF, MF, MFR, MFR2, MFC) Call Progress Tones (Dial Tone, Ring Back Tone, etc.) StartModes (WinkStart, ImmediateStart, DelayDial) Supervisory Signals (Seizure, Flash, Wink, Disconnect) MultiTech Systems, Inc. SocketSLIC Developer s Guide 6

7 Chapter Introduction Features Programmable Answer Delay Timing CAS Bit Signaling Manipulations Hybrid Balances TDM Bit Clocks TDM Companding Modes TDM Framing Modes TDM Loopback Modes Receive Gains Ring Frequencies Ring Patterns Ring Voltages Special Functions Telecom Voltages Telephony Interfaces Timeslot Assignments Transmit Gains Wink Delay Timing Status and Diagnostics Capability Telephony Lead Wiring Error Status TDM Loopback Function Internal Reset Counter Supports LoopStart, GroundStart and DirectInwardDialing (DID) Supports FXO, FXS, DPO, DPT, E&M, PLR, ETO, TO E&M Type I, II, III, IV, V Signaling TwoWire and FourWire Transmissions Loop Disconnect Signals Caller ID and Other Class Services MultiTech Systems, Inc. SocketSLIC Developer s Guide 7

8 Chapter Introduction Benefits Acts as a Universal Analog Trunk/Line Card AutoWink TM Signaling Caller ID Processing CMOS/TTL Compatible Inputs And Outputs Dielectric Barrier separating Digital (logic) and Analog (telephony) Ports Direct A and B Signaling Bit Access Pins Fast Digital Ring Detection Algorithm Flash Memory for Firmware Updates Fully Electrically Isolated Analog Telephony Interface Global Homologation FlashtoAnswer Supervision InSystem Programmability Supported Internal 24 Wire Conversion Low Noise Design Low Power Consumption Low RFI Emissions No DIP Switches. No Jumpers (None on the SocketSLIC. The Developer Board has Dip Switches) OnBoard Ring Generator OnBoard Telecom Battery Power Supply Originate LoopDisconnect Signal Pass LoopDisconnect Signals PC Operating System Independent Telephone Trunk/Line Status Reporting Serial Peripheral Interface (SPI) Short Circuit Tolerant Analog Telephony Port Terminals Single Voltage Power Supply Input Small DualInLine Package Footprint Transparent Interface Conversion Operation Universal Asynchronous Receiver and Transmitter (UART) Interface Works Without the need for Constant Host Processor Supervision MultiTech Systems, Inc. SocketSLIC Developer s Guide 8

9 Chapter Introduction Safety Handling Precautions Proper care must be taken when handling and installing this product:. Observe the absolute maximum ratings 2. Avoid exposure to electrostatic discharge (ESD) 3. Prevent the application of reverse polarity to the power pins 4. Provide filtered power to the module 5. Never plug or unplug this product while powered Electrostatic Discharge (ESD) Caution Static electricity can destroy some sensitive components on this product. To prevent damage to the product due to an electrostatic discharge, always connect yourself to ground using a ground strap before touching the product. Handle product only by the edges and always store the product in anti static bags. Safety Instructions When using your telephone equipment, basic safety precautions should always be followed to reduce the risk of fire, electric shock, and injury to persons, including the following:. Read and understand all instructions 2. Follow all warnings and instructions 3. Unplug the equipment from the telecom connector before cleaning 4. Use a damp cloth for cleaning 5. Do not use liquid cleansers or aerosol cleaners 6. Do not use this product near water 7. When installing this product into your system, please make sure that the earth ground pin is securely connected to the systems chassis or telecom reference conductor terminal and that the system is plugged into a grounded threeprong outlet. Incorrect grounding can result in harmful or fatal electrical shock or component damage. Telecom Safety Warning. Never install telephone wiring during a lightning storm. 2. Never install a telephone jack in wet locations unless the jack is specifically designed for wet locations. 3. This product is to be used with UL and cul listed computers. 4. Never touch uninsulated telephone wires or terminals unless the telephone line has been disconnected at the network interface. 5. Use caution when installing or modifying telephone lines. 6. Avoid using a telephone during an electrical storm. There may be a remote risk of electrical shock from lightning. 7. Do not use a telephone in the vicinity of a gas leak. 8. To reduce the risk of fire, use only 26 AWG or larger telecommunication line cord. 9. This product must be disconnected from its power source and telephone network interface when servicing. MultiTech Systems, Inc. SocketSLIC Developer s Guide 9

10 SocketSLIC Mechanical Drawing Chapter Introduction MultiTech Systems, Inc. SocketSLIC Developer s Guide

11 Chapter Introduction Pin Description Pin Symbol Type Name/Description SB I/O SIGNAL BATTERY LEAD. This pin is the signalbattery lead for type II, III, and IV interface arrangements for 2wire and 4wire E and M signaling facilities. This is not a power pin! 2 SG I/O SIGNAL GROUND LEAD. This pin is the signalground lead for type II, III, and IV interface arrangements for 2wire and 4wire E and M signaling facilities. This is not a power pin! 3 T I/O TLEAD. This pin is the Tlead for 2wire E&M transmit and receive talkpath and 4wire E&M receive talkpath only. 4 E/TIP I/O ELEAD. This pin is the Elead in 2wire and 4wire E and M signaling facilities. This pin is also the Tiplead for all 2wire LOOP signaling facilities. 5 M/RING I/O MLEAD. This pin is the Mlead in 2 wire and 4wire E and M signaling facilities. This pin is also the RingLead for all 2wire LOOP signaling facilities. 6 R I/O RLEAD. This pin is the Rlead for 2wire E&M transmit and receive talkpath and 4wire E&M receive talkpath only. 7 TRC I/O TELECOM REFERENCE CONDUCTOR. This pin is the telecom ground lead that connects the module s internal power supply to an external earth ground. 8 R O RLEAD. This output pin is the Rlead for the 4wire E&M transmit talkpath only. 9 T O TLEAD. This output pin is the Tlead for the 4wire E&M transmit talkpath only. DIELECTRIC ISOLATION BARRIER XSIG O TRANSMIT SIGNALING. This output pin indicates the incoming analog signaling state (active high). ARCV I A RECEIVE CAS BIT. This input pin receives bit A for channel associated signaling. 2 BRCV I B RECEIVE CAS BIT. This input pin receives bit B for channel associated signaling. 3 AXMT O A TRANSMIT CAS BIT. This output pin transmits bit A for channel associated signaling. 4 BXMT O B TRANSMIT CAS BIT. This output pin transmits bit B for channel associated signaling. 5 CS I CHIP SELECT. This input pin receives the chip select signal for the SPI and UART ports 6 MOSI I SPI SLAVE INPUT. This input pin receives the input data for the SPI port. 7 MISO O SPI SLAVE OUTPUT. This output pin transmits the output data for the SPI port. 8 SCK I SPI CLOCK. This input pin receives the shift clock for the SPI port. 9 RST I RESET. This input pin must be pulled low for normal operation. When pulled momentarily high for at least us, all programmable registers in the device are reset to the states specified under powerup initialization. 2 RXD I RECEIVE DATA. This input pin receives the input data for the UART. 2 TXD O TRANSMIT DATA. This output pin transmits the output data for the UART. 22 TSX O TRANSMIT TIMESLOT. This open drain output pin is floating in a highimpedance state. When a timeslot is active on the DX output, the TSX output pulls low to indicate a valid timeslot and to enable a backplane line driver. 23 DX O TRANSMIT TDM. This output pin remains in the high impedance state except during the assigned timeslot, when the transmit TDM data byte is shifted out on the rising edges of BCLK. 24 BCLK I BIT CLOCK. This input pin shifts TDM data into and out of the DR and DX pins. It must be.536 MHz,.544 MHz, 2.48 MHz, or 4.96 MHz. 25 DR I RECEIVE TDM. This input pin is inactive except during the assigned timeslot when the receive TDM data byte is shifted in on the falling edges of BCLK. 26 FS I FRAMESYNC. This input pin receives a pulse or square waveform with an 8kHz repetition rate is applied to it. This waveform defines the start of the timeslot assigned to this module (in nondelayed frame mode), or the start of the frame (in delayed frame mode using the internal timeslot assignment counter). 27 VDD LOGIC POWER. This pin connects to the +5 Vdc power supply 28 GND LOGIC GROUND. This pin connects to the +5 Vdc power supply return reference. 29 RSIG O RECEIVE SIGNALING. This output pin indicates the outgoing analog signaling state (active high). MultiTech Systems, Inc. SocketSLIC Developer s Guide

12 Chapter 2 Functions and Ports Chapter 2 Functions and Ports Telephony Functions The SocketSLIC provides the following standard BORSCHT telephony functions: Battery Feed Battery Voltage Generation for powering the lines or trunks Loop Current Detection for recognizing line or trunk seizures Overvoltage Protection External fuses (onetime fuse or polyfuse) for Current Limitation are required. External Transient Voltage Suppressors (TVS or MOV) for Overvoltage Protection are required. Ringing Ring Detection Ring Generation Supervision Normal Battery / Reverse Battery OnHook / OffHook Codec AnalogtoDigital (A/D) Conversion with mulaw Or ALaw companding DigitaltoAnalog (D/A) Conversion with mulaw Or ALaw decompanding Hybrid Programmable internal hybrid balance network 2wire To 4wire circuit conversion Testing Internal loopback modes for the digital TDM stream An external relay may be required to provide test access. MultiTech Systems, Inc. SocketSLIC Developer s Guide 2

13 Chapter 2 Functions and Ports Analog Interface Port The SocketSLIC analog interface port can be configured to support the basic analog Public Switched Telephone Network (PSTN) interfaces. Each PSTN interface consists of two sides. One interface port represents one side of the interface. Startmode and addressing information are passed transparently between the analog and digital ports. The SocketSLIC supports the following analog interfaces: Interface with LoopStart Supervision (LS) Interface with ReverseBattery Supervision (RB) Interface with GroundStart Supervision (GS) Interface with LoopReverseBattery Supervision (LRBS) Interface with E and M Lead Supervision (E and M) Interface with no Supervision (NoS) The SocketSLIC supports the following analog interface ports: Foreign Exchange Office (FXO) Foreign Exchange Subscriber (FXS) Dial Pulse Originating (DPO) Dial Pulse Terminating (DPT) E and M (E&M) Pulse Link Repeater (PLR) Transmission Only (TO) Equalized Transmission Only (ETO) The SocketSLIC supports the following transmission types: TwoWire (2W) FourWire (4W) The SocketSLIC supports the following E and M signaling types: Type I (I) Type II (II) Type III (III) Type IV (IV) Type V (V) The SocketSLIC supports the following telecom parameter adjustments: Transmit Gain (TG) Receive Gain (RG) Telecom Voltage (TV) Ring Voltage (RV) Ring Frequency (RF) Ring Pattern (RP) Answer Delay Timing (ADT) Wink Delay Timing (WDT) Lower Ring Frequency Detection Limit (LRFDL) Upper Ring Frequency Detection Limit (URFDL) MultiTech Systems, Inc. SocketSLIC Developer s Guide 3

14 Chapter 2 Functions and Ports Digital Interface Port The SocketSLIC contains a programmable interface for the transmission and reception of digital Time Division Multiplex (TDM). TDM data is shifted into the decoders TDM receive register via the DR pin during the selected timeslot on the falling edges of BCLK. The FS inputs determine the beginning of the 8bit transmit and receive timeslots respectively. They can have any duration from a single cycle of BCLK high to one BCLK low. Two different relationships can be established between the framesync inputs and the actual timeslots on the TDM buses by setting bit 3 in the Codec Control Register (CCR). Nondelayed data mode is similar to longframe timing of other TDM line cards for which timeslots begin nominally coincident with the rising edge of the appropriate FS input. The alternative is to use delayeddata mode (shortframe timing) in which the FS input must be high at least a halfcycle of BCLK earlier than the timeslot. The timeslot assignment circuit on the module can only be used with delayeddata timing. The timeslot assignment capability of the module conforms to the Lucent Technologies Concentration Highway Interface (CHI). The beginning of the first timeslot in a frame is identified by the appropriate FS input. The actual transmit and receive timeslots are then determined by the internal timeslot assignment counters. During each assigned transmit timeslot, the selected DX output shifts the time division multiplex data out from the TDM transmit register on the rising edges of BCLK. TSX also pulls low for the first 7.5 bit times of the timeslot to control the high impedance state enable of a backplane line driver. Serial TDM data is shifted into the selected DR input during each assignment of the receive timeslot on the falling edges of BCLK. The clock rates of.536 MHz, 2.48 MHz, and 4.96 MHz support 24, 32, or 64 time slots respectively. The SocketSLIC supports the following TDM stream settings: Bit Clock (.536 MHz, 2.48 MHz, 4.96 MHz) Companding Law (u255 Law, ALaw) Frame Synchronization (delayed framing, nondelayed framing) Loopback Mode (analog and digital) The SocketSLIC supports the following Channel Associated Signaling controls: CAS bit Status (hardware pin access or register read access) CAS bit Manipulation (invert & swap) CAS bit Declaration (force a specific logic level) MultiTech Systems, Inc. SocketSLIC Developer s Guide 4

15 Chapter 2 Functions and Ports Control Interface Port Control information is written into or read back from the module s registers either via the synchronous SPI or asynchronous UART communication. The user can change the user accessible registers as required by port operation. The userselected values are immediately executed after writing to the register. The module will revert to the default settings after subsequent resets or power ups. The desired modes for all programmable functions can be initialized via the SPI or UART interfaces. The control interface port allows access to the following module functions: Configuration Communication Programming Configuration and communication is accomplished through the following module pin connections: <TXD> <RXD> <CSS> <SCK> <MOSI> <MISO> UART transmit data output from module UART receive date input to module SPI Chip Select input to module SPI Shift Clock input to module SPI Master Output/Slave Input to module SPI Master Input/Slave Output from module MultiTech Systems, Inc. SocketSLIC Developer s Guide 5

16 Chapter 2 Functions and Ports UART Operation The Universal Asynchronous Receiver and Transmitter (UART) provide serial communication access to the module. Asynchronous communication is very common because of the wide spread use of modems. Asynchronous communication follows a defined method or protocol. ASCII characters are transmitted at TTL level into the module with a fixed baud rate of 9.2kbps (transmission speed). The UART consists of receive data input (RXD), transmit data output (TXD) and chip select input. The host may start sending ASCII data ms after asserting the chip select input. Baud Rate: 9.2 kbps Data Bits: 8 Parity Bit: none Stop Bit: Maximum Character Read/Write: 4 (2 x 2 Byte Nibbles) Minimum Character Read/Write: 2 ( x 2 Byte Nibbles) Transmit Data Pin: TXD Receive Data Pin: RXD Module Chip Select Pin: CS Chip Select warmup : ms Example The following is an example of how to set the Telecom Voltage to approximately 6Vdc using the UART interface. Typing/sending 2C, the register address for TVR, the serial port transmits the ASCII characters of 2C into the module. The module converts the ASCII character back to 2C hexadecimal. Typing/sending D, the data byte for 6Vdc, the serial port transmits the ASCII characters of D into the module. Note that the ASCII characters for the module must be capitalized. 2 First register address byte nibble ASCII character C Second register address byte nibble ASCII character First register data byte nibble ASCII character D Second register data byte nibble ASCII character Create a Commented Text File Below is a method of creating a commented text file for configuring the module. The raw text file can be down loaded directly into the module. The module will only accept the following hexadecimal character set (,, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F). Note that the module only accepts capitalized letters from a through f. This way the characters to the right of the semicolon are intended for the module configuration and the characters to the left of the semicolon are intended as a comment line. 6 ; read module version number 22 ; set restore factory defaults 286 ; set port to fxsgs 2FC ; set enable autowink and enable flashtoanswer 3983 ; set rcv timeslot four 3A87 ; set xmt timeslot eight MultiTech Systems, Inc. SocketSLIC Developer s Guide 6

17 Chapter 2 Functions and Ports SPI Operation The SPI consists of the Serial Clock (SCK), the Master Output/Slave Input (MOSI) and Master Input/Slave Output (MISO), and the Chip Select input (CS). The module is configured as the SPI slave. To shift control data into the module, SCK must be pulsed high eight times while CS is low. Data on the MOSI input is shifted into the serial input register on the falling edge of each SCK pulse. Bit 7 of bytes and 2 is always the first bit clocked into or out from the MISO/TXD and MOSI/RXD pins. After all data is shifted in, the contents of the input shift register are decoded and can indicate that a second byte can either be defined by a second bytewide CS pulse or can follow the first contiguously. It is not mandatory for CS to return high between the first and second control bytes. At the end of the eighth SCK pulse in the second control byte, the data is loaded into the appropriate programmable register. CS can remain low continuously when programming successive registers, if desired. However, CS should be set high when no data transfers are in progress. To read back data or status information from the module, the first byte of the appropriate instruction is strobed in during the first CS pulse. CS must then be taken low for a further eight SCK cycles, during which the data is shifted onto the MISO pin on the rising edges of SCK. When CS is high, the MISO pin is in the highimpedance state, enabling the MISO pins of many devices to be multiplexed together. Serial Synchronous Communication Access The SPI provides serial synchronous communication access to the module. Maximum SPI Clock Speed: 256kHz Minimum SPI Byte Spacing: 74µs Transmit Data Pin: MISO Receive Data Pin: MOSI Serial Clock Pin: SCK Module Chip Select Pin: CS SPI Access Restrictions Following a read command, give at least 74µs before the next access. Following a write command, give at least 2.7ms before the next access. Following a factory default command, give at least ms. When doing a two byte read or write command, give 74µs between the register and the value read or written. Example The following is an example of how to set the Telecom Voltage to approximately 6Vdc using the SPI interface. This is accomplished by writing a xd to the Telecom Voltage Register (TVR) which is located at register address x2c: st Byte 2C register address byte 2 nd Byte D register data byte More Serial Peripheral Interface Information The control interface to the SocketSLIC is a 4wire synchronous interface modeled after commonly available microcontroller and serial peripheral devices. The interface consists of a clock (SCK), chip select (SCS), serial data input (MOSI) and serial data output (MISO). Data is transferred a bite at time with each register access consisting of a pair of byte transfers. The first byte of the pair is the command/address byte. The MSB of this byte indicates register read when and a register write when. The remaining seven bits of the command/address byte indicate the address of the register to be accessed. The second byte of the pair is the data byte. During a read operation, the MISO becomes active and the 8bit contents of the register are driven out MSB first. The MISO will be high impedance on either the falling edge of SCLK following the LSB, or the rising of CS whichever comes first. MOSI is a "do not care" during the data portion of read operations. During write operations, data is driven into the SocketSLIC via the MOSI pin MSB first. The MISO pin will remain in the High Impedance State during write operations. Data always transitions on the rising edge. The clock should return to a logic high when no transfer is in progress. There are a number of variations of usage on this fourwire interface: MultiTech Systems, Inc. SocketSLIC Developer s Guide 7

18 Chapter 2 Functions and Ports Special Functions All special functions are based on SocketSLIC proprietary processing methods and can be selected through the Special Function Register (SFR). Caller ID Processing Caller ID processing (CID) applies to FXOLS and FXSLS ports only. The user must select the CID function when the attached telephone equipment is capable of originating or terminating caller ID signals. When selected, the FXSLS or FXOLS audio talkpath is enabled during nonring burst periods for transmission of the caller ID information. The caller ID signal passes through the FXSLS configuration from the digital module side to the analog module side. The caller ID signal passes through the FXOLS configuration from the analog module side to the digital module side. Pass Loop Disconnect Pass Loop Disconnect operation (PLD) applies to the FXOLS and FXSLS port configurations. The user must select the PLD function when the attached telephone equipment is capable of originating or terminating loopdisconnect signals. When selected, the XMT CAS bit that indicates ringing also indicates the remote back to onhook condition while the local connected equipment is still in the offhook condition. The loop disconnect signal eliminates possible locked up trunk conditions between FXOLS and FXSLS interfaces. Some CO/PBX based FXSLS interfaces originate a loop disconnect signal in from of a temporary drop in loop current towards the FXOLS interface. Autowink Operation AutoWINK operation (AW) may be selected for FXS port configurations. The user must select the AWO function when conversion from FXS loop/groundstart to DID/E&M winkstart mode is required. When selected, a wink signal of 2ms duration is issued on the XMT CAS bit after offhook detection of the connected local equipment and after the wink delay timer (WDR) expires. The wink is the goahead or handshake signal for the calling end to release the addressing information or routing digits. FlashToAnswer Supervision FlashtoAnswer supervision (FtA) may be selected for FXS port configurations. The user must select the FTA function to provide proper answersupervision when converting from FXS to DID or E&M interfaces. When selected, an answer supervision condition is issued for the duration of the call on the XMT CAS bit after the detection of the first hookflash from the connected local equipment. If the answer delay timer is enabled, the answer signal is automatically set after the answer delay timer (ADR) expires. The first flash after answer is the goahead or call acceptance signal for the local switch to start the billing process. All subsequent hookflashes are converted and passed normally. Please read the DID information on the FCC Part 68 page in this manual. Originate Loop Disconnect Originate Loop Disconnect (OLD) operation applies to the FXSLS port only. The user must select the OLD function when the attached telephone equipment is capable of terminating (understanding) loopdisconnect signals. When selected, the FXSLS port issues an automatic loop disconnect signal (loop current drop) of about.7 s duration if the local equipment connected to the FXS port remains in the offhook state. The loop disconnect signal does not guarantee that the local connected equipment goes back to the onhook condition. If the local connected equipment does not go back onhook during the loop disconnect signal, the same offhook condition will appear like a new request for service from the local connected equipment. MultiTech Systems, Inc. SocketSLIC Developer s Guide 8

19 Chapter 3 Interfaces Chapter 3 Interfaces Interface With LoopStart Supervision The interface with loopstart supervision is part of the loop signaling facility interface group. This interface is often referred to as PlainOldTelephoneService (POTS). PlainOldTelephoneService is a service provided by the Central Office (CO) for common inbound and outbound call traffic. Loopstart is a form of signaling in which the end office supplies battery between tip and ring conductors. A terminal indicates an offhook state by allowing current to flow. Loop refers to the closing of switch contacts across the tip and ring conductors to allow current to flow in the telephone loop. The interface with loopstart supervision is not polarity sensitive. However, it is good practice to always connect the tiplead from one side to the tiplead of the other side and connect the ringlead from one side to the ringlead from the other side. The two sides of the loopstart interface are the Foreign exchange Office (FXO) and the Foreign exchange Subscriber (FXS) ports. Connection CO Ringing CPE FXS TalkPath Loop States Conditions No Ringing Ringing Open Loop Idle Alerting Closed Loop Seized Talking Voltage Diagram Idle Alerting Answer Talking Flash Disconnect Volt Level OffHook Level OnHook Level CAS Bit Mapping AXMT X ARCV T BXMT Ringing Ringing BRCV T FXO FXS R ARCV Loop Loop AXMT R BRCV X BXMT MultiTech Systems, Inc. SocketSLIC Developer s Guide 9

20 Chapter 3 Interfaces Sequence of Events H High DC resistance loop (greater than 3, Ohms) L Low DC resistance loop ( Ohms to 2,4 Ohms) N Normal battery with the tip at ground potential (+Vdc) and ring at battery potential ( Vdc) O Open circuit condition (Battery and/or ground leads are removed from the circuit) FXSLS INITIATES, FXSLS TERMINATES Line States Interface Conditions Comments FXSLS FXOLS FXS and FXO Idle N H Switch and Phone are waiting for a call FXS Alerting Ringing ((Ringing)) Switch send ringing towards phone FXO Answer N or Ringing H L Phone goes offhook to answer the call FXS and FXS Connect N L Phone and switch have a talkpath connection FXS Disconnects First N O N L Switch issues disconnect signal (optional) FXO Disconnects Next O L H Phone goes onhook FXSLS INITIATES, FXOLS TERMINATES Line States Interface Conditions Comments FXSLS FXSLS FXS and FXO Idle N H Switch and phone are waiting for a call FXS Alerting Ringing ((Ringing)) Switch send ringing towards phone FXO Answers N or Ringing H L Phone goes offhook to answer the call FXS and FXS Connect N L Phone and Switch have a talkpath connection FXO Disconnects First N L H Phone goes onhook FXS Disconnects Next N H Switch assumes idle condition FXOLS INITIATES, FXSLS TERMINATES Line States Interface Conditions Comments FXSLS FXOLS FXO and FXS Idle N H Switch and phone are waiting for a call FXO Seizes N H L Phone goes offhook FXO and FXS Connect N L Phone and switch have a talkpath connection FXS Disconnects First N O N L Switch issues disconnect signal (optional) FXO Disconnects Next N L H Phone goes onhook FXOLS INITIATES, FXOLS TERMINATES Line States Interface Conditions Comments FXSLS FXOLS FXO and FXS Idle N H Switch and phone are waiting for a call FXO Seizes N H L Phone goes offhook FXO and FXS Connect N L Phone and Switch have a talkpath connection FXO Disconnects First N L H Phone goes onhook FXS Disconnects Next N H Switch assumes idle condition MultiTech Systems, Inc. SocketSLIC Developer s Guide 2

21 Chapter 3 Interfaces Foreign Exchange Subscriber LoopStart Port The Foreign Exchange Subscriber LoopStart (FXSLS) port looks like a telephone wall outlet jack. This port is also referred to as the CO side of the loopstart interface. Its counterpart is the FXO port configured for loopstart supervision. Abbreviation: Alerting: CAS Bits: Signaling Type: Start mode: Transmission: Wire terminals: FXSLS RINGING A and B NONE LOOPSTART 2WIRE TIP and RING INTERFACING ARCV = X TIP LEAD RING LEAD ANALOG PORT DIGITAL PORT BRCV = no RINGING AXMT = closed LOOP BXMT = FXSLS PORT CONDITIONS The Analog Port Does What in which state Receives Open LOOP Idle or Alerting Receives Closed LOOP Seized or Answered Transmits No RINGING Idle or Answered Transmits AC RINGING Alerting FXSLS PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port Open LOOP Closed LOOP X No RINGING Open LOOP X AC RINGING Closed LOOP X No RINGING MultiTech Systems, Inc. SocketSLIC Developer s Guide 2

22 Chapter 3 Interfaces Foreign Exchange Office LoopStart Port The Foreign Exchange Office LoopStart (FXOLS) port looks like a regular telephone. This port is also referred to as the CPE side of the loopstart interface. Its counterpart is the FXS port configured for loopstart supervision. Abbreviation: Alerting: CAS Bits: Signaling Type: StartMode: Transmission: Wire terminals: FXOLS RINGING A and B NONE LOOPSTART 2WIRE TIP and RING INTERFACING TIP LEAD ANALOG PORT DIGITAL PORT ARCV = closed LOOP BRCV = X RING LEAD AXMT = BXMT = no ringing CONDITIONS The Analog Port does What in which state Receives No RINGING Idle or Seized Receives AC RINGING Alerting Transmits Open LOOP Idle or Alerting Transmits Closed LOOP Seized or Answered CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port No RINGING AC RINGING X Open LOOP X Closed LOOP MultiTech Systems, Inc. SocketSLIC Developer s Guide 22

23 Chapter 3 Interfaces Interface With ReverseBattery Supervision The interface with reversebattery supervision is part of the loop signaling facility interface group. This interface is capable of ringing and providing battery polarity reversal at the same time. The reverse battery signaling states vary greatly from application to application. Most typically the call waiting indication in a customer loop is performed by reversing the polarity going to the phone receiving the call waiting indication along with a 3 ms burst of the 44 Hz call waiting callprogress tone. The reversebatterysignaling interface is polarity sensitive. It makes a difference which way the tip and ring wires are hooked up to the public switched telephone network. The two sides of the reversebattery interface are the Foreign exchange Office (FXO) and the Foreign exchange Subscriber (FXS) ports. Connection CO Ringing and Battery CPE FXS TalkPath Loop FXO States The reverse battery signaling states are not specified Conditions No Ringing Ringing Open Loop Idle Alerting Closed Loop Seized Talking Voltage Diagram The reverse battery signaling states are not specified Idle Alerting Answer Talking Reverse Battery Flash Disconnect Volt Level OffHook Level OnHook Level CAS Bit Mapping AXMT Battery Battery ARCV T BXMT Ringing Ringing BRCV T FXO FXS R ARCV Loop Loop AXMT R BRCV X BXMT MultiTech Systems, Inc. SocketSLIC Developer s Guide 23

24 Chapter 3 Interfaces Sequence of Events H High DC resistance loop (greater than 3,Ohms) L Low DC resistance loop (Ohms to 2,4Ohms) N Normal battery with the tip at ground potential (+Vdc) and ring at battery potential ( Vdc) R Reverse battery with the tip at battery ( Vdc) and the ring at ground (+Vdc) O Open circuit condition (Battery and/or ground leads are removed from the circuit) FXSRB INITIATES, FXSLS TERMINATES Line States Interface Conditions Comments FXSLS FXOLS FXS and FXO Idle N H Switch and Phone are waiting for a call FXS Alerting Ringing (((Ringing))) Switch sends ringing towards phone FXO Answer N or Ringing H L Phone goes offhook to answer the call FXS and FXS Connect N L Phone and switch have a talkpath connection FXS Reverses Polarity R L Switch issues Call Waiting (CW) signal. FXS Disconnects First N O N L Switch issues disconnect signal (optional) FXO Disconnects Next O L H Phone goes onhook FXSLS INITIATES, FXOLS TERMINATES Line States Interface Conditions Comments FXSLS FXSLS FXS and FXO Idle N H Switch and phone are waiting for a call FXS Alerting Ringing (((Ringing))) Switch sends ringing towards phone FXO Answers N or Ringing H L Phone goes offhook to answer the call FXS and FXS Connect N L Phone and Switch have a talkpath connection FXS Reverses Polarity R L Switch issues Call Waiting (CW) signal. FXO Disconnects First N L H Phone goes onhook FXS Disconnects Next N H Switch assumes idle condition FXOLS INITIATES, FXSLS TERMINATES Line States Interface Conditions Comments FXSLS FXOLS FXO and FXS Idle N H Switch and phone are waiting for a call FXO Seizes N H L Phone goes offhook FXO and FXS Connect N L Phone and switch have a talkpath connection FXS Reverses Polarity R L Switch issues Call Waiting (CW) signal. FXS Disconnects First N O N L Switch issues disconnect signal (optional) FXO Disconnects Next N L H Phone goes onhook FXOLS INITIATES, FXOLS TERMINATES Line States Interface Conditions Comments FXSLS FXOLS FXO and FXS Idle N H Switch and phone are waiting for a call FXO Seizes N H L Phone goes offhook FXO and FXS Connect N L Phone and Switch have a talkpath connection FXS Reverses Polarity R L Switch issues Call Waiting (CW) signal. FXO Disconnects First N L H Phone goes onhook FXS Disconnects Next N H Switch assumes idle condition MultiTech Systems, Inc. SocketSLIC Developer s Guide 24

25 Chapter 3 Interfaces Foreign Exchange Subscriber ReverseBattery Port The Foreign Exchange Subscriber Reverse Battery (FXSRB) port looks like a DirectInwardDialing CO port with ringing capabilities. Its counterpart is the FXO port configured for reversebattery supervision. Abbreviation Alerting CAS Bits Signaling Type Start mode Transmission Wire terminals FXSRB RINGING A and B NONE LOOPSTART 2WIRE TIP and RING FXSRB PORT INTERFACING ARCV = BATTERY BRCV = no RINGING TIP LEAD RING LEAD ANALO GPORT DIGITA LPORT AXMT = closed LOOP BXMT = FXSRB PORT CONDITIONS The Analog Port Does What in which state Receives Open LOOP Idle or Alerting Receives Closed LOOP Seized or Answered Transmits No RINGING Idle or Answered Transmits AC RINGING Alerting Transmits Normal BATTERY Not specified Transmits Reverse BATTERY Not specified FXSRB PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port Open LOOP Closed LOOP X No RINGING Open LOOP X AC RINGING Closed LOOP X No RINGING X X Normal BATTERY X X Reverse BATTERY MultiTech Systems, Inc. SocketSLIC Developer s Guide 25

26 Chapter 3 Interfaces Foreign Exchange Office ReverseBattery Port The Foreign Exchange Office ReverseBattery (FXORB) port looks like a DirectInwardDialing PBX port with ring detection capabilities. Its counterpart is the FXS port configured for reversebattery supervision. Abbreviation: Alerting: CAS Bits: Signaling Type: StartMode: Transmission: Wire terminals: FXORB RINGING A and B NONE LOOPSTART 2WIRE TIP and RING FXORB PORT INTERFACING ARCV = closed LOOP BRCV = X TIP LEAD RING LEAD ANALOG PORT DIGITAL PORT AXMT = BATTERY BXMT = no RINGING FXORB PORT CONDITIONS The Analog Port does What in which state Receives No RINGING Idle or Seized Receives AC RINGING Alerting Receives Normal BATTERY Not Specified Receives Reverse BATTERY Not Specified Transmits Open LOOP Idle or Alerting Transmits Closed LOOP Seized or Answered FXORB PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port No RINGING X AC RINGING X Normal BATTERY X Reverse BATTERY X X Open LOOP X Closed LOOP MultiTech Systems, Inc. SocketSLIC Developer s Guide 26

27 Chapter 3 Interfaces Interface With GroundStart Supervision The interface with groundstart supervision is part of the loop signaling facility interface group. This interface most commonly connects the trunk side of a PBX to the servicing Central Office. Groundstart is a form of signaling in which grounding a wire indicates a request for service by either interface side. The interface with groundstart supervision is polarity sensitive. Always connect the Tlead from one side to the Tlead of the other side and connect the Rlead from one side to the Rlead from the other side. If the Tlead and the Rlead are reversed, the PBX will not be able to initiate outbound calls. The two sides of the groundstart interface are the foreign exchange office and the foreign exchange subscriber ports. Connection CO Tip Ground and Ringing PBX FXS TalkPath FXO Ring Ground & Loop States Conditions No Ringing Ringing No Tip Ground Tip Ground Open Loop PBX Idle CO Alerting CO Idle CO Seized Closed Loop PBX Connected PBX Answered PBX Error PBX Answer No Ring Ground PBX Idle CO Alerting CO Idle CO Seized Ring Ground PBX Seized PBX Error PBX Seized PBX Connected Voltage Diagram Idle Seize Alerting Answer Talking Flash Disconnect Idle Volt Level Level Level OffHook Level OnHook Level CAS Bit Mapping AXMT TGround TGround ARCV T BXMT Ringing Ringing BRCV T FXO FXS R ARCV Loop Loop AXMT R BRCV RGround RGround BXMT MultiTech Systems, Inc. SocketSLIC Developer s Guide 27

28 Chapter 3 Interfaces Sequence of Events H High DC resistance loop (greater than 3, Ohms) L Low DC resistance loop ( Ohms to 2,4 Ohms) N Normal battery with the tip lead at ground (+Vdc) and the ring lead at battery ( Vdc) O Open circuit condition (Battery and/or ground leads are removed from the circuit) FXSGS INITIATES, FXSGS TERMINATES Line States Interface Conditions Comments FXSGS FXOGS FXS and FXO Idle O H CO and PBX are waiting for a call FXS Seizure N (Tip Grounded) H CO lands a call by applying ground to tip lead FXS Alerting Ringing ((Ringing)) CO send ringing towards PBX PBX Answer N or Ringing H L PBX goes offhook to answer the call FXS and FXS Connect N L PBX and CO now have a talkpath connection FXS Disconnects First N O L CO removes ground from tip lead first PBX Disconnects Next O L H PBX goes onhook next FXSGS INITIATES, PBXGS TERMINATES Line States Interface Conditions Comments FXSGS PBXGS FXS and PBX Idle O H CO and PBX are waiting for a call FXS Seizure N (Tip Grounded) H CO lands a call by applying ground to tip lead FXS Alerting Ringing ((Ringing)) CO send ringing towards PBX FXO Answers N or Ringing H L PBX goes offhook to answer the call FXS and FXS Connect N L PBX and CO now have a talkpath connection FXO Disconnects First N L H PBX goes onhook first FXS Disconnects Next N O H CO removes ground from tip lead next FXOGS INITIATES, FXSGS TERMINATES Line States Interface Conditions Comments FXSGS FXOGS FXO and FXS Idle O H PBX and CO are waiting for a call FXO Seizes O H (Ring Grounded) PBX issues the request for service FXS Answers N H CO responds with grounding the tip FXO OffHook N H L PBX goes offhook after seeing ground on tip FXO and FXS Connect N L PBX and CO now have a talkpath connection FXS Disconnects First N O L CO removes ground from tip lead first FXO Disconnects Next O L H PBX goes onhook next FXOGS INITIATES, FXOGS TERMINATES Line States Interface Conditions Comments FXSGS FXOGS FXO and FXS Idle O H CO and PBX are waiting for a call FXO Seizes O H (Ring Grounded) PBX issues the request for service FXS Answers N H CO responds with grounding the tip FXO OffHook N H L PBX goes offhook after seeing ground on tip FXO and FXS Connect N L PBX and CO now have a talkpath connection FXO Disconnects First N L H PBX goes onhook first FXS Disconnects Next N O H CO removes ground from tip lead next MultiTech Systems, Inc. SocketSLIC Developer s Guide 28

29 Chapter 3 Interfaces Foreign Exchange Subscriber GroundStart Port The Foreign Exchange Subscriber GroundStart (FXSGS) port looks like a CO trunk circuit. This port is also referred to as the CO side of the groundstart interface. Its counterpart is the FXO port configured for groundstart supervision. Abbreviation: Alerting: CAS Bits: Signaling Type: Start Mode: Transmission: Wire terminals: FXSGS RINGING A and B NONE GROUNDSTART 2WIRE TIP and RING FXSGS PORT INTERFACING TIP LEAD RING LEAD ANALOG PORT DIGITAL PORT ARCV = TGROUND BRCV = no RINGING AXMT = closed LOOP BXMT = RGROUND FXSGS PORT CONDITIONS The Analog port does what and/or what in which state Receives OPEN LOOP NO RING GROUND PBX idle Receives RING GROUND PBX seized Receives CLOSED LOOP RING GROUND PBX connected Transmits NO RINGING NO TIP GROUND CO idle Transmits NO RINGING TIP GROUND CO seized Transmits AC RINGING TIP GROUND CO alerting Transmits NO RINGING TIP GROUND CO connected FXSGS PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port Open LOOP, No Ring GROUND X Open LOOP, Ring GROUND No Tip GROUND Closed LOOP or Ring GROUND Tip GROUND X No RINGING, No Tip GROUND No RINGING, Tip GROUND Open LOOP AC RINGING, Tip GROUND Closed LOOP No RINGING, Tip GROUND MultiTech Systems, Inc. SocketSLIC Developer s Guide 29

30 Chapter 3 Interfaces Foreign Exchange Office GroundStart Port The Foreign Exchange Office GroundStart (FXOGS) port looks like a PBX trunk circuit. This port is also referred to as the PBX trunk side of the groundstart interface. Its counterpart is the FXS port configured with groundstart supervision. Abbreviation: Alerting: CAS Bits: Signaling Type: Start mode: Transmission: Wire terminals: FXOGS RINGING A and B NONE GROUNDSTART 2WIRE TIP and RING FXOGS PORT INTERFACING TIP LEAD RING LEAD ANALOG PORT DIGITAL PORT ARCV = closed LOOP BRCV = RGROUND AXMT = TGROUND BXMT = no RINGING FXOGS PORT CONDITIONS The Analog Port does what in which state Receives No Tip GROUND CO idle Receives Tip GROUND CO seized Receives AC RINGING CO alerting Receives No RINGING CO connected Transmits Open LOOP PBX onhook Transmits Closed LOOP PBX offhook Transmits No Ring GROUND PBX idle Transmits Ring GROUND PBX seized FXOGS PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port No Tip GROUND Tip GROUND No RINGING AC RINGING Open LOOP Closed LOOP No Ring GROUND Ring GROUND MultiTech Systems, Inc. SocketSLIC Developer s Guide 3

31 Chapter 3 Interfaces Interface With LoopReverseBattery Supervision The interface with loopreversebattery supervision is part of the loop signaling facility interface group. This interface is also known as DirectInwardDialing Service or DID service. DID is a function provided by the Central Office for inbound call traffic only. The customer premise equipment (CPE), Private Branch Exchanges (PBX) or Voice Messaging Systems (VMS) typically receive the last 3 to 7 digits of the telephone number dialed by the caller through the Central Office which is connected at the other side of the DID trunk. The PBX/VMS uses the DID digits to route and place the call to a specific person (station) or during a ringnoanswer/busynoanswer condition to an individual mailbox. The loopreversebatterysignaling interface is polarity sensitive. It makes a difference which way the tip and ring wires are hooked up to the public switched telephone network. If the wires are reversed, the trunk busies out and the caller may hear the alltrunksbusy or fast busy signal. The two sides of the loopreversebattery interface are the dial pulse originating and the dial pulse terminating (DPT) port. Connection CO Loop PBX DPT TalkPath Battery DPO States Conditions Normal Battery Reverse Battery Loop Open Idle Busy Loop Closed Seized Answered Voltage Diagram Idle Seizure Wink Addressing Ringback Answer Talking Flash CO Disconnect Idle Reverse onhook Reverse offhook Volt level CPE Disconnect Normal offhook Normal onhook CAS Bit Mapping AXMT Loop Loop ARCV T BXMT Loop X BRCV T DPO DPT R ARCV Battery Battery AXMT R BRCV X Battery BXMT MultiTech Systems, Inc. SocketSLIC Developer s Guide 3

32 Chapter 3 Interfaces Sequence of Events H High DC resistance loop (greater than 3, Ohms) L Low DC resistance loop ( Ohms to 2,4 Ohms) N Normal battery with the tip at ground (+Vdc) and the ring at battery ( Vdc) R Reverse battery with the tip at battery ( Vdc) and the ring at ground (+Vdc) DPT INITIATES, DPT TERMINATES Line States Interface Conditions Comments DPT DPO DPT and DPO Idle H N CO and PBX are waiting for a call DPT seizes H L N CO goes offhook DPO answers L N R PBX provides reverse battery DPO and DPT Connect L R PBX and CO have a talkpath connection DPT Disconnects First L H R CO goes back onhook DPO Disconnects Next H R N PBX goes back to normal battery DPT INITIATES, DPO TERMINATES Line States Interface Conditions Comments DPT DPO DPT and DPO Idle H N CO and PBX are waiting for a call DPT seizes H L N CO goes offhook DPO answers L N R PBX provides reverse battery DPO and DPT Connect L R PBX and CO have a talkpath connection DPO Disconnects First L R N PBX goes back to normal battery DPT Disconnects Next L H N CO goes back onhook MultiTech Systems, Inc. SocketSLIC Developer s Guide 32

33 Chapter 3 Interfaces Dial Pulse Terminating Port The Dial Pulse Terminating (DPT) port looks like a CO network interface circuit configured for loopreversebattery supervision. This port is also referred to as the CO side of the DID trunk. Its counterpart is the DPO port. Abbreviation: Alerting: CAS Bits: Signaling Type: Start Mode: Transmission: Wire terminals: DPT NONE A = B NONE IMMEDIATE, WINK, and DELAYDIAL 2WIRE TIP and RING DPT PORT INTERFACING TIP LEAD RING LEAD ANALOG PORT DIGITAL PORT ARCV = closed LOOP BRCV = X AXMT = Rev BAT BXMT = Rev BAT DPT PORT CONDITIONS The Analog Port does What in which state Receives normal BATTERY Idle or Seized Receives reverse BATTERY Busy or Answered Transmits Open LOOP Idle or Busy Transmits closed LOOP Seized or Answered DPT PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port Normal BATTERY X X Reverse BATTERY X X X X X Open LOOP X X X Closed LOOP MultiTech Systems, Inc. SocketSLIC Developer s Guide 33

34 Chapter 3 Interfaces Dial Pulse Originating Port The Dial Pulse Originating (DPO) port looks like a CPE trunk circuit configured for loopreversebattery supervision. This port is also referred to as the CPE side of DID trunk. Its counterpart is the DPT port. Abbreviation: Alerting: CAS Bits: Signaling Type: Start Modes: Transmission: Wire terminals: DPO PORT INTERFACING DPO NONE A = B NONE IMMEDIATE, WINK, and DELAYDIAL 2WIRE TIP and RING TIP LEAD RING LEAD ANALOG PORT DIGITAL PORT ARCV = Rev BAT BRCV = X AXMT = closed LOOP BXMT = closed LOOP DPO PORT CONDITIONS The Analog Port Does what in which state Receives Open LOOP Idle or Busy Receives Closed LOOP Seized or Answered Transmits Normal BATTERY Idle or Seized Transmits Reverse BATTERY Busy or Answered DPO PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port Open LOOP X X Closed LOOP X X X X X Normal BATTERY X X X Reverse BATTERY MultiTech Systems, Inc. SocketSLIC Developer s Guide 34

35 Chapter 3 Interfaces Interface With E and M Lead Supervision The interface with E and M lead supervision is part of the E and M signaling facility interface group. The term E and M describes interfaces used by switches within the confines of a building. E and M signaling is not used in outside wiring. On an E and M trunk, the carrier facilities or PBX Tie Lines may dial many or no digits in DTMF or MF via inband signaling or Dial Pulse via Elead or Mlead outofband signaling. The switch uses the digits to route and place the call to a specific person (station) or during a ringnoanswer/busynoanswer condition to an individual mailbox. The term E and M originates from the old Ear and Mouthpieces associated with early telephones. The E and M leadsignaling interface is wiring sensitive. Always connect the Elead from one side to the Elead of the other side. If the E and Mlead are hooked up reversed, the interface will not operate as properly. The two sides of the E and M interface are the E&M and the pulse link repeater ports (PLR). Connection Trunk A Trunk B E&M TalkPath \ ELead MLead SGLead SBLead PLR Conditions Conditions Open ELead Ground Elead Ground Or Open MLead Idle ELead Seized Battery Or Ground MLead MLead Seized Connected Voltage Diagram Idle Wink Seize Connect Flash Connect Disconnect Idle Onhook Level Offhook Level CAS Bit Mapping M AXMT MLead MLead ARCV M T BXMT MLead X BRCV T E&M PLR R ARCV ELead ELead AXMT R E BRCV X ELead BXMT E MultiTech Systems, Inc. SocketSLIC Developer s Guide 35

36 Chapter 3 Interfaces Sequence of Events Open High DC resistance loop (greater than 2, Ohms) Looped Low DC resistance loop ( Ohms to 2,4 Ohms) Battery Battery potential ( Vdc) Ground Ground potential (+Vdc) TYPE I Line States Interface Conditions Comments M E Idle Ground Open Trunk is waiting for a call PLR Seizure Battery Open PLR lands a call on the E and M trunk E&M Seizure Ground Ground E&M lands a call on the E and M trunk Connect Battery Ground Called party and calling party are communicating TYPE II Line States Interface Conditions Comments M E Idle Open Open Trunk is waiting for a call PLR Seizure Battery Open PLR lands a call on the E and M trunk E&M Seizure Open Ground E&M lands a call on the E and M trunk Connect Battery Ground Called party and calling party are communicating TYPE III Line States Interface Conditions Comments M E Idle Ground Open Trunk is waiting for a call PLR Seizure Battery Open PLR lands a call on the E and M trunk E&M Seizure Ground Ground E&M lands a call on the E and M trunk Connect Battery Ground Called party and calling party are communicating TYPE IV Line States Interface Conditions Comments M E Idle Open Open Trunk is waiting for a call PLR Seizure Ground Open PLR lands a call on the E and M trunk E&M Seizure Open Ground E&M lands a call on the E and M trunk Connect Ground Ground Called party and calling party are communicating TYPE V Line States Interface Conditions Comments M E Idle Open Open Trunk is waiting for a call PLR Seizure Ground Open PLR lands a call on the E and M trunk E&M Seizure Open Ground E&M lands a call on the E and M trunk Connect Ground Ground Called party and calling party are communicating MultiTech Systems, Inc. SocketSLIC Developer s Guide 36

37 Chapter 3 Interfaces Interface Diagrams Here is a listing between the different E&M/PLR port interface diagrams. For simplicity reasons the diagrams do not contain any form of circuitry or contact protection. 48 Vdc Battery Normally open Contact Wire Junction Normally closed Contact Earth or Chassis Ground E Relay Wire Connection Lead Terminal Interface Demarcation E and M Type I M E PLR E&M E and M TYPE II SB M E SG PLR E&M MultiTech Systems, Inc. SocketSLIC Developer s Guide 37

38 Chapter 3 Interfaces E and M TYPE III E and M TYPE IV E and M TYPE V MultiTech Systems, Inc. SocketSLIC Developer s Guide 38

39 Chapter 3 Interfaces E and M Port The E and M (E&M) port looks like a signaling circuit configured for E and M supervision. This port is also referred to as the normal E&M side of the E and M signaling interface. Its counterpart is the PLR port. Abbreviation: Alerting: CAS Bits: Signaling Type: Start Mode: Transmission: Wire terminals: E&M NONE A = B I, II, III, IV, V IMMEDIATE, WINK, and DELAYDIAL 2WIRE and 4WIRE T, R, T, R, E, M, SG, SB, and TRC E&M PORT INTERFACING ELEAD TLEAD RLEAD MLEAD ANALOG PORT DIGITAL PORT ARCV = ELEAD BRCV = X AXMT = MLEAD BXMT = MLEAD E&M PORT CONDITIONS The Analog Port Does What In which state Receives Ground or Open MLEAD Idle or ELead Seized Receives Battery or Ground MLEAD Seized or Connected Transmits Open ELEAD Idle or MLead Seized Transmits Ground ELEAD Seized or Connected E&M PORT CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port Ground or Open MLEAD X X Battery or Ground MLEAD X X X X X Open ELEAD X X X Ground ELEAD MultiTech Systems, Inc. SocketSLIC Developer s Guide 39

40 Chapter 3 Interfaces Pulse Link Repeater Port The Pulse Link Repeater (PLR) port looks like a trunk circuit configured for E and M supervision. This port is also referred to as the reverse E and M side of the E and M signaling interface. Its counterpart is the E&M port. Abbreviation: Alerting: CAS Bits: Signaling Type: Start Mode: Transmission: Wire terminals: PLR NONE A = B I, II, III, IV, V IMMEDIATE, WINK, and DELAYDIAL 2WIRE and 4WIRE T, R, T, R, E, M, SG, SB, and TRC INTERFACING MLEAD RCV A = MLEAD RCV A = MLEAD ANALOG DIGITAL RCV B = X TLEAD PORT PORT RLEAD AXMT = ELEAD ELEAD BXMT = ELEAD CONDITIONS The Analog Port Does What In which state Receives Open ELEAD Idle or MLead Seized Receives Ground ELEAD Seized or Connected Transmits Ground or Open MLEAD Idle or ELead Seized Transmits Battery or Ground MLEAD Seized or Connected CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port Open ELEAD X X Ground ELEAD X X X X X Ground or Open MLEAD X X X Battery or Ground MLEAD MultiTech Systems, Inc. SocketSLIC Developer s Guide 4

41 Chapter 3 Interfaces Interface With No Supervision No supervision indicates that the trunk is a dry circuit. Dry means that there is no battery power or flow of any current involved. There is also no signaling associated with this kind of interface. The talkpath consists of a balanced wire pair and is suitable for long haul signal transmissions. The signaling interface without any supervision is not wiring sensitive. However, it is good practice to always connect the Tlead from one side to the Tlead of the other side and connect the Rlead from one side to the Rlead from the other side. The Interface with no supervision maintains a constant and direct talkpath connection to the other side. The following ports are part of this interface: Transmission Only (TO) Equalized Transmission Only (ETO) Connection CO PBX ETO TalkPath ETO Conditions Conditions NO Signaling NO Signaling Connected Sequence of Events X = Any condition Line States Interface Conditions Comments TO TO Idle = Connect X X Line is passing payload MultiTech Systems, Inc. SocketSLIC Developer s Guide 4

42 Chapter 3 Interfaces TransmissionOnly Port The TransmissionOnly (TO) port looks like a twowire terminal circuit configured for no supervision. This port is also referred to as the 2wire dry voice circuit. This port may carry talkpath information in either direction on the same wire pair. The advantage of the TO is that transmit and receive signals are carried on one wire pair only. Its counterpart is the TO port. Abbreviation: Alerting: CAS Bits: Signaling Type: Start Mode: Transmission: Wire terminals: TO NONE does not care NONE NONE 2WIRE T, R INTERFACING TLEAD RLEAD ANALOG PORT DIGITAL PORT ARCV = X BRCV = X AXMT = or BXMT = or CONDITIONS The Analog Port Does What In which state Receives No SIGNALING Any Transmits No SIGNALING Any CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port No SIGNALING or or X X No SIGNALING MultiTech Systems, Inc. SocketSLIC Developer s Guide 42

43 Chapter 3 Interfaces Equalized TransmissionOnly Port The Equalized Transmission Only (ETO) port looks like a fourwire terminal circuit configured for no supervision. This port is also referred to as the 4wire dry voice circuit. The port carries transmit and receive talkpath information on separate wire pairs. The advantage of the ETO is that signals can easily be amplified, attenuated, or equalized as required. Each wire pair of this fourwire circuit has to be defined as transmit only and receive only port. Its counterpart is the ETO port. Abbreviation Alerting CAS Bits Signaling Type Start Mode Transmission Wire terminals ETO NONE does not care NONE NONE 4WIRE T, R, T, and R INTERFACING TLEAD ARCV = X RLEAD BRCV = X ANALOG PORT DIGITAL PORT TLEAD AXMT = or RLEAD BXMT = or CONDITIONS The Analog Port Does What In which state Receives No SIGNALING Any Transmits No SIGNALING Any CAS BIT FUNCTIONS Input To Port AXMT BXMT ARCV BRCV Output From Port No SIGNALING or or X X No SIGNALING MultiTech Systems, Inc. SocketSLIC Developer s Guide 43

44 Chapter 4 Module Registers Chapter 4 Module Registers Address and data are written into or read back from the 32 module registers through the control interface port using either UART or SPI communication. All module register write instructions require 2 bytes. Some of the registers are read only Some of the registers should not be written to Some of the registers are not user accessible Some of the registers are reserved for future use Some of the registers are for factory use only # FUNCTION ABBR. Read Write Module Mode Register MMR x6 x2 2 Solid State Register SSR For factory use only 3 Telephony Error Status Register TER x62 Read only 4 Solid State Register 2 SSR2 For factory use only 5 CAS Bit Status Register CBR x64 Read only 6 CAS Bit Manipulation Register CMR x65 x25 7 CAS Bit Receive Declaration Register RDR x66 x26 8 CAS Bit Transmit Declaration Register TDR x67 x27 9 Interface Selection Register ISR x68 x28 Ring Pattern Register RPR x69 x29 Ring Frequency Register RFR x6a x2a 2 Ring Voltage Register RVR x6b x2b 3 Telecom Voltage Register TVR x6c x2c 4 Upper Ring Frequency Detection Limit Register URFDLR x6d x2d 5 Lower Ring Frequency Detection Limit Register LRFDLR x6e x2e 6 Special Function Register SFR x6f x2f 7 Codec Control Register CCR x7 x3 8 Interface Latch Register ILR For factory use only 9 Latch Direction Register LDR For factory use only 2 Reserved for Future Use x73 x33 2 Receive Gain Register RGR x74 x34 22 Transmit Gain Register TGR x75 x35 23 Hybrid Balance Register HBR x76 Write not recommended 24 Hybrid Balance Register 2 HBR2 x77 Write not recommended 25 Hybrid Balance Register 3 HBR3 x78 Write not recommended 26 Receive Timeslot Register RTR x79 x39 27 Transmit Timeslot Register TTR x7a x3a 28 Reserved for Future Use x7b x3b 29 SPI Control Register SPCR x7c x3c 3 Wink Delay Register WDR x7d x3d 3 Answer Delay Register ADR x7e x3e 32 Reset Count Register RCR x7f x3f MultiTech Systems, Inc. SocketSLIC Developer s Guide 44

45 Chapter 4 Module Registers Factory Defaults All user accessible read/write registers have factory preloaded register default values. The values have been selected for standard North American telephone operation. Writing x2 to the Module Mode Register (MMR) restores the factory default values. After the factory default values have been restored the user settings may have to be reloaded. Default Settings Register Read Value Function Parameter MMR x6 xxx Module Mode Register Returns firmware version SSR x6 xxx Solid State One Register No default value applicable TER x62 xxx Telephony Error Register No default value applicable SSR2 x63 xxx Solid State Two Register No default value applicable CBR x64 xxx CAS Bit Status Register No default value applicable CMR x65 x CAS Bit Manipulation Nothing manipulated RDR x66 x CAS Bit Receive Declaration Nothing declared TDR x67 x CAS Bit Transmit Declaration Nothing declared ISR x68 x Interface Selection FXOLS (looks like a telephone) RPR x69 x Ring Pattern Selection DAC (typical pattern) RFR x6a x32 Ring Frequency Selection 2. Hz (typical frequency) RVR x6b xf Ring Voltage Selection 7.3 Vac (highest voltage) TVR x6c x Telecom Voltage Selection 5. Vdc (typical voltage) URFDLR x6d xe Upper Ring Frequency Detection Limit 7.42 Hz (highest limit) LRFDLR x6e x3f Lower Ring Frequency Detection Limit 5.87 Hz (lowest limit) SFR x6f x Special Function Register No special function selected CCR x7 x8 Codec Control Selection 2.48 MHz TDM clock ulaw companding Delayed data timing ILR x7 xcc Interface Latch Fixed and not user accessible LDR x72 x3 Latch Direction Fixed and not user accessible x73 x Reserved for Future Use No default value applicable RGR x74 xc2 Receive Gain Selection +2. db TGR x75 x83 Transmit Gain Selection +6. db HBR x76 xe Hybrid Balance Register Should not be changed by user HBR2 x77 x24 Hybrid Balance Register 2 Should not be changed by user HBR3 x78 x26 Hybrid Balance Register 3 Should not be changed by user RTR x79 x8 Receive Timeslot Selection TDM Timeslot is set to TTR x7a x8 Transmit Timeslot Selection TDM Timeslot is set to x7b xxx Reserved for Future Use No default value applicable SPCR x7c xc7 SPI Control Register MSB first Low when Idle Clock on leading edge WDR x7d xff Wink Delay Register Wink delay timing is disabled ADR x7e xff Answer Delay Register Answer delay timing is disabled RCR x7f xxx Reset Count Register No default value applicable MultiTech Systems, Inc. SocketSLIC Developer s Guide 45

46 Chapter 4 Module Registers Value Ranges From the following registers the user may select a specific value from a range of values. Factory default settings are loaded for ease of use and installation. Register Range Settings # Parameter Register Minimum Default Maximum Ring Frequency RFR 6.3 Hz 2. Hz Hz 2 Ring Voltage RVR 9.3 Vrms 7.3 Vrms 7.3 Vrms 3 Telecom Voltage TVR 24.7 Vdc 5. Vdc 74.7 Vdc 4 Upper Ring Frequency Detection Limit URFDLR 5.87 Hz 7.42 Hz 7.42 Hz 5 Lower Ring Frequency Detection Limit LRFDLR 5.87 Hz 5.87 Hz 7.42 Hz 2 Receive Gain RGR 7.3 db +2. db +2. db 22 Transmit Gain TGR.4 db +6. db +9. db 3 Wink Delay WDR s Off 25.4 s 3 Answer Delay ADR s Off 25.4 s MultiTech Systems, Inc. SocketSLIC Developer s Guide 46

47 Chapter 4 Module Registers Individual Register Details Module Mode Register The module mode register allows the user to set a number or special module modes. The module can be shut down in order to reduce its current draw to about 4mA. Shutting down the module powers down all active components of the module, including the on board processor. In this mode the module will not respond to any external input or communication command. A temporary transition to the high state on the module s reset pin is required to bring the module back to normal operation. The module is preloaded with register default settings. In the default mode the module look like a regular telephone or modem input. See the register default settings for further information. Reading this register returns the firmware version number Writing x to this register has no effect Writing x to this register shuts down the module Writing x2 to this register restores the original factory default register settings MMR Settings x6 x2 Bit Number Function Reserved X Reserved X Reserved X Reserved X Reserved X Reserved X Normal Operation Restore Factory Defaults Normal Operation Shut Down MultiTech Systems, Inc. SocketSLIC Developer s Guide 47

48 Chapter 4 Module Registers Telephony Error Register The telephony error register indicates various analog port error conditions. The interface is capable of recognizing the absence of current when current should be flowing. In, short, when going offhook, current should flow. If current does not flow in an offhook condition, then the port is either not powered correctly either due to wiring error or a power fail condition on the other side of the interface. Errors are normally due to wiring mistakes or incompatible interface port operation. The following analog port errors may be encountered during operation: FXOLS Closed loop condition but loop current is not flowing FXORB Closed loop condition but loop current is not flowing FXOGS Ring ground condition but ground current is not flowing FXOGS Closed loop condition but loop current is not flowing DPT Closed loop condition but loop current is not flowing E&M Elead active but Elead current is not flowing PLR Mlead active but Mlead current is not flowing No error condition is detectable for FXS, DPO, TO and ETO port interfaces. The TER is a read only register. The new value is latched until the next register read resets the value back to. TER Settings x62 Bit Number Function M Normal Current Load Ok M Normal Current Load Error M Reverse Current Load Ok M Reverse Current Load Error E Normal Current Load Ok E Normal Current Load Error E Reverse Current Load Ok E Reverse Current Load Error Reserved Reserved Reserved Reserved MultiTech Systems, Inc. SocketSLIC Developer s Guide 48

49 Chapter 4 Module Registers CAS Bit Status Register The CAS Bit Status Register allows the user to read the CAS bit status for the current condition of the selected interface port. The CBR is a read only register. CBR Settings x64 Function Bit Number ARCV X BRCV X CRCV X DRCV X AXMT X BXMT X CXMT X DXMT X CAS Bit Manipulation Register The CAS Bit manipulation register allows the user to pass normal, invert, or swap specific CAS receive and/or transmit bits. EXAMPLE ARCV invert and swap results in B looking like an inverted ARCV level BRCV normal and swap results in A looking like a normal BRCV level ARCV A BIT MANIPULATOR: A BRCV Digital B Normal B Analog Loop or E and M I/F Invert I/F AXMT Port A Normal & Swap A Port Signaling Facility BXMT B Invert & Swap B CMR SETTINGS x65 x25 Function ARCV Normal ARCV Invert ARCV Normal & Swap ARCV Invert & Swap BRCV Normal BRCV Invert BRCV Normal & Swap BRCV Invert & Swap AXMT Normal AXMT Invert AXMT Normal & Swap AXMT Invert & Swap BXMT Normal BXMT Invert BXMT Normal & Swap BXMT Invert & Swap Bit Number MultiTech Systems, Inc. SocketSLIC Developer s Guide 49

50 Chapter 4 Module Registers MultiTech Systems, Inc. SocketSLIC Developer s Guide 5 CAS Bit Receive Declaration Register The CAS bit receive declaration register allows the user to force a specific receive CAS bit to a preset state for the selected interface port operation. RDR SETTINGS x66 x26 Function Bit Number ARCV Not Set ARCV Set To ARCV Set To ARCV Set To B BRCV Not Set BRCV Set To BRCV Set To BRCV Set To A CRCV Set To CRCV Set To CRCV Set To A CRCV Set To B DRCV Set To DRCV Set To DRCV Set To A DRCV Set To B CAS Bit Transmit Declaration Register The CAS bit transmit declaration register allows the user to force a specific transmit CAS bit to a preset state for the selected interface port operation. TDR SETTINGS x67 x27 Function Bit Number AXMT Not Set AXMT Set To AXMT Set To AXMT Set To B BXMT Not Set BXMT Set To BXMT Set To BXMT Set To A CXMT Set To CXMT Set To CXMT Set To A CXMT Set To B DXMT Set To DXMT Set To DXMT Set To A DXMT Set To B

51 Chapter 4 Module Registers Interface Selection Register The interface selection register allows the user to select specific interface ports for different interface applications. Writing to x28 a hex inactivates the analog port. ISR Settings x68 x28 Bit Number Function Hex Inactive x FXOLS x FXSLS x2 FXORB x3 FXSRB x4 FXOGS x5 FXSGS x6 DPO x7 DPT x8 2W, TO x9 2W, E&M, I xa 2W, E&M, II xb 2W, E&M, III xc 2W, E&M, IV xd 2W, E&M, V xe 2W, PLR, I xf 2W, PLR, II x 2W, PLR, III x 2W, PLR, IV x2 2W, PLR, V x3 4W, ETO x4 4W, E&M, I x5 4W, E&M, II x6 4W, E&M, III x7 4W, E&M, IV x8 4W, E&M, V x9 4W, PLR, I xa 4W, PLR, II xb 4W, PLR, III xc 4W, PLR, IV xd 4W, PLR, V xe Not Assigned xf Not Assigned / / / / / / / / To Not Assigned xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 5

52 Chapter 4 Module Registers Ring Pattern Register The ring pattern register allows the user to select specific alerting patterns for the FXS ports. Standard preloaded ringing patterns may be selected: DA type code (2. s on, 4. s off) DA type code 2 (. s on,. s off,. s on, 3. s off) DA type 2 (.8 s on,.4 s off,.8 s on, 4. s off) DA type 3 (.4 s on,.2 s off,.4 s on,.2 s off,.8 s on, 4. s off) The ring pattern repeats every 6 seconds. Custom ringing patterns may be created by selecting constant ringing and turning the BRCV CAS bit on and off to start and stop the individual ring burst. RPR SETTINGS x69 x29 Bit Number Function Hex Pattern DAC x Pattern DAC2 x Pattern DA2 x2 Pattern DA3 x3 Constant Ringing x4 Not Assigned x5 Not Assigned / / / / / / / / To Not Assigned xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 52

53 Ring Frequency Register The ring frequency register allows the selection of specific ring generation frequencies for the FXS ports. RFR SETTINGS: x6a x2a Chapter 4 Module Registers Bit Number Ring Frequency Function Hex in Hz +/ % Not Assigned x Not Assigned \ \ \ \ \ \ \ \ To Not Assigned xe 5 ms xf ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x ms xa ms xb ms xc ms xd ms xe ms xf ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x2a ms x2b ms x2c ms x2d ms x2e ms x2f ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x3a ms x3b ms x3c ms x3d ms x3e 6.3 Not Assigned x3f Not Assigned \ \ \ \ \ \ \ \ To Not Assigned xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 53

54 Chapter 4 Module Registers Ring Voltage Register The ring voltage register allows the user to select specific ring generation voltages for the FXS ports. RVR SETTINGS x6b Function x2b Bit Number Hex Ring Voltage Setting Mid+ x 5.7 Ring Voltage Setting Mid+ x 52.6 Ring Voltage Setting Mid+2 x Ring Voltage Setting Mid+3 x Ring Voltage Setting Mid+4 x Ring Voltage Setting Mid+5 x Ring Voltage Setting Mid+6 x6 57. Ring Voltage Setting Mid+7 x Ring Voltage Setting Mid+8 x Ring Voltage Setting Mid+9 x Ring Voltage Setting Mid+ xa 6.4 Ring Voltage Setting Mid+ xb 6.3 Ring Voltage Setting Mid+2 xc 62.2 Ring Voltage Setting Mid+3 xd 63. Ring Voltage Setting Mid+4 xe 64. Ring Voltage Setting Mid+5 xf 64.9 Ring Voltage Setting Mid+6 x 65.8 Ring Voltage Setting Mid+7 x 66.7 Ring Voltage Setting Mid+8 x Ring Voltage Setting Mid+9 x Ring Voltage Setting Mid+2 x Ring Voltage Setting Mid+2 x5 7.3 Ring Voltage Setting Min+22 x6 7.2 Ring Voltage Setting Min+23 x7 72. Ring Voltage Setting Min+24 x Ring Voltage Setting Min+25 x Ring Voltage Setting Min+26 xa 74.7 Ring Voltage Setting Min+27 xb 75.6 Ring Voltage Setting Min+28 xc 76.5 Ring Voltage Setting Min+29 xd 77.3 Ring Voltage Setting Min+3 xe 78.3 Ring Voltage Setting Min+3 xf 79. Ring Voltage Setting Min+32 x Ring Voltage Setting Min+33 x Ring Voltage Setting Min+34 x Ring Voltage Setting Mid+35 x Ring Voltage Setting Mid+36 x Ring Voltage Setting Mid+37 x Ring Voltage Setting Mid+38 x Ring Voltage Setting Mid+39 x Ring Voltage Setting Mid+4 x Ring Voltage Setting Mid+4 x Ring Voltage Setting Mid+42 x2a 32. Ring Voltage Setting Mid+43 x2b 33. Ring Voltage Setting Mid+44 x2c 33.9 Ring Voltage Setting Mid+45 x2d 34.7 Ring Voltage Setting Mid+46 x2e 35.6 Ring Voltage Setting Mid+47 x2f 36.5 Ring Voltage Setting Mid+48 x Ring Voltage Setting Mid+49 x Ring Voltage Setting Mid+5 x Ring Voltage Setting Mid+5 x33 4. Ring Voltage in Vrms +/ no Load MultiTech Systems, Inc. SocketSLIC Developer s Guide 54

55 Chapter 4 Module Registers Continued from previous page: Function Bit Number Hex Ring Voltage Setting Mid+52 x Ring Voltage Setting Mid+53 x Ring Voltage Setting Mid+54 x Ring Voltage Setting Mid+55 x Ring Voltage Setting Mid+56 x Ring Voltage Setting Mid+57 x Ring Voltage Setting Mid+58 x3a 46.2 Ring Voltage Setting Mid+59 x3b 47. Ring Voltage Setting Mid+6 x3c 48. Ring Voltage Setting Mid+6 x3d 48.9 Ring Voltage Setting Mid+62 x3e 49.8 Ring Voltage Setting Mid+63 x3f 5.7 Ring Voltage Set to zero Vac x4. Not Assigned x4 Not Assigned / / / / / / / / To Not Assigned xff Ring Voltage in Vrms +/ no Load MultiTech Systems, Inc. SocketSLIC Developer s Guide 55

56 Chapter 4 Module Registers Telecom Voltage Register The telecom voltage register allows the user to select specific telecom voltages for the FXS, DPO, E&M and PLR ports. TVR SETTINGS x6c Function x2c Bit Number Hex Telecom Voltage in Vdc +/ no Load Telecom Voltage Setting Mid+ x 58. Telecom Voltage Setting Mid+ x 58.8 Telecom Voltage Setting Mid+2 x Telecom Voltage Setting Mid+3 x3 6.5 Telecom Voltage Setting Mid+4 x4 6.6 Telecom Voltage Setting Mid+5 x Telecom Voltage Setting Mid+6 x Telecom Voltage Setting Mid+7 x Telecom Voltage Setting Mid+8 x Telecom Voltage Setting Mid+9 x Telecom Voltage Setting Mid+ xa 67. Telecom Voltage Setting Mid+ xb 68. Telecom Voltage Setting Mid+2 xc 68.9 Telecom Voltage Setting Mid+3 xd 69.8 Telecom Voltage Setting Mid+4 xe 7.7 Telecom Voltage Setting Mid+5 xf 7.5 Telecom Voltage Setting Mid+6 x 72.4 Telecom Voltage Setting Mid+7 x 73.3 Telecom Voltage Setting Mid+8 x Telecom Voltage Setting Mid+9 x3 75. Telecom Voltage Setting Mid+2 x Telecom Voltage Setting Mid+2 x Telecom Voltage Setting Min+22 x Telecom Voltage Setting Min+23 x Telecom Voltage Setting Min+24 x Telecom Voltage Setting Min+25 x9 8.3 Telecom Voltage Setting Min+26 xa 8.2 Telecom Voltage Setting Min+27 xb 82. Telecom Voltage Setting Min+28 xc 83. Telecom Voltage Setting Min+29 xd 83.9 Telecom Voltage Setting Min+3 xe 84.7 Telecom Voltage Setting Min+3 xf 85.5 Telecom Voltage Setting Min+32 x Telecom Voltage Setting Min+33 x Telecom Voltage Setting Min+34 x Telecom Voltage Setting Mid+35 x Telecom Voltage Setting Mid+36 x Telecom Voltage Setting Mid+37 x Telecom Voltage Setting Mid+38 x Telecom Voltage Setting Mid+39 x Telecom Voltage Setting Mid+4 x Telecom Voltage Setting Mid+4 x Telecom Voltage Setting Mid+42 x2a 37.8 Telecom Voltage Setting Mid+43 x2b 38.8 Telecom Voltage Setting Mid+44 x2c 39.7 Telecom Voltage Setting Mid+45 x2d 4.6 Telecom Voltage Setting Mid+46 x2e 4.6 Telecom Voltage Setting Mid+47 x2f 42.5 Telecom Voltage Setting Mid+48 x Telecom Voltage Setting Mid+49 x Telecom Voltage Setting Mid+5 x Telecom Voltage Setting Mid+5 x MultiTech Systems, Inc. SocketSLIC Developer s Guide 56

57 Chapter 4 Module Registers Continued from previous page: Function Bit Number Hex Telecom Voltage in Vdc +/ no Load Telecom Voltage Setting Mid+52 x Telecom Voltage Setting Mid+53 x Telecom Voltage Setting Mid+54 x Telecom Voltage Setting Mid+55 x Telecom Voltage Setting Mid+56 x Telecom Voltage Setting Mid+57 x Telecom Voltage Setting Mid+58 x3a 52.4 Telecom Voltage Setting Mid+59 x3b 53.3 Telecom Voltage Setting Mid+6 x3c 54.3 Telecom Voltage Setting Mid+6 x3d 55. Telecom Voltage Setting Mid+62 x3e 56. Telecom Voltage Setting Mid+63 x3f 56.9 Telecom Voltage Set to zero Vac x4. Not Assigned x4 Not Assigned / / / / / / / / To Not Assigned X X X X X X X xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 57

58 Chapter 4 Module Registers Upper Ring Frequency Detection Limit Register The upper ring frequency detection limit register allows the user to select the detection limit for the upper ring frequencies for the FXO port operation. When the incoming ringing frequency is greater than the selected frequency then the ring detector will not trigger a response and the received ringing is being ignored. RING FREQUENCY DETECTION RANGE LRFDLR Ringing URFDLR 5.87 Hz to 7.42 Hz 6.3 Hz to Hz 5.87 Hz to 7.42 Hz Reject Range Accept Range Reject Range URFDLR SETTINGS x6d x2d Bit Number Ring Frequency Function Hex in Hz +/ % Not Assigned x 7.42 Not Assigned / / / / / / / / To 7.42 Not Assigned xd ms xe ms xf ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x ms xa ms xb ms xc ms xd ms xe ms xf ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x2a ms x2b ms x2c ms x2d ms x2e ms x2f ms x ms x ms x ms x ms x ms x MultiTech Systems, Inc. SocketSLIC Developer s Guide 58

59 Chapter 4 Module Registers Continued from previous page: Bit Number Ring Frequency Function Hex in Hz +/ % 54 ms x ms x ms x ms x ms x3a ms x3b ms x3c ms x3d ms x3e ms x3f 5.87 Not Assigned x Not Assigned / / / / / / / / To 5.87 Not Assigned xff 5.87 MultiTech Systems, Inc. SocketSLIC Developer s Guide 59

60 Chapter 4 Module Registers Lower Ring Frequency Detection Limit Register The lower ring frequency detection limit register allows the user to select the detection limit for the lower ring frequencies for the FXS port operation. When the incoming ringing frequency is less than the selected frequency then the ring detector will not trigger a response and the received ring signal is being ignored. RING FREQUENCY DETECTION RANGE EXAMPLE LRFDLR Ringing URFDLR 5.87 Hz to 25. Hz Hz to Hz 4. Hz to 7.42 Hz Reject Accept Reject LRFDLR SETTINGS x6e x2e Bit Number Ring Frequency Function Hex in Hz +/ % Not Assigned x Not Assigned / / / / / / / / To Not Assigned xd 4 ms xe ms xf ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x ms xa ms xb ms xc ms xd ms xe ms xf ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x ms x2a ms x2b ms x2c ms x2d ms x2e ms x2f ms x ms x ms x ms x ms x MultiTech Systems, Inc. SocketSLIC Developer s Guide 6

61 Chapter 4 Module Registers Continued from previous page: Bit Number Ring Frequency Function Hex in Hz +/ % 53 ms x ms x ms x ms x ms x ms x3a ms x3b ms x3c ms x3d ms x3e ms x3f 5.87 Not Assigned x4 Not Assigned \ \ \ \ \ \ \ \ To Not Assigned xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 6

62 Chapter 4 Module Registers Special Function Register The special function register allows the selection of telephony functions that are optional to the operation of the selected telephony interface. The following special functions are currently supported: Caller ID PassThrough Pass Loop Disconnect AutoWINK TM FlashtoAnswer Originate Loop Disconnect SFR SETTINGS x6f x2f Bit Number Function Reserved Reserved Reserved Originate FXS Loop Disconnect Disabled Originate FXS Loop Disconnect Enabled FXS FlashtoAnswer Supervision Disabled FXS FlashtoAnswer Supervision Enabled FXS autowink Operation Disabled FXS autowink Operation Enabled Pass FXS/FXO Loop Disconnect Disabled Pass FXS/FXO Loop Disconnect Enabled Caller ID PassThrough Disabled Caller ID PassThrough Enabled MultiTech Systems, Inc. SocketSLIC Developer s Guide 62

63 Chapter 4 Module Registers Codec Control Register The codec control register allows the user to select the specific operation for the digital port of the module. A TDM master clock must be provided to the module for operation of the TDM, filter coding/decoding functions. The BCLK frequency must be.536 MHz,.544 MHz, 2.48 MHz, or 4.96 MHz. Bits 4 and 5 in the CCR permit the selection of ulaw coding or Alaw coding, with or without even bit inversion. The analog loopback mode is entered by setting the AL and DL bits in the CCR. In the analog loopback mode, the analog transmit input is isolated from the input and internally passed to the analog output, forming a loop from the TDM input (DR) back to TDM output (DX). The programmed settings of transmit and receive gains remain unchanged. Care must be taken to ensure that overload levels are not exceeded anywhere in the loop. It is recommended that the hybridbalance filter be disabled during analog loopback. The digital loopback mode is entered by setting the AL and DL bits in the CCR. This mode provides another level of path verification by enabling data written into receive TDM register to be read back from that register in any transmit timeslot at DX. In digital loopback mode, the decoder remains functional and outputs signals at the analog port. If this is undesirable, receive output can be disabled by programming receive gain register to all s. The module can operate in either fixed timeslot or timeslot assignment modes for selecting transmit and receive TDM timeslots. Following powerup, the module is automatically in nondelayed timing mode, in which the timeslot always begins with the leading (rising) edge of the framesync input (FS). Timeslot assignment can only be used with delayeddata timing. The internal timeslot counter can be used to access any timeslot in a frame by using the frame sync (FS) input as a marker pulse for the beginning of transmit and receive timeslots of 8 bits each. A timeslot is assigned by a 2 byte instruction. The last 6 bits of the second byte indicate the selected timeslot from to 63 using a straight binary notation. A new assignment becomes active on the second frame following the end of the following the end of the chip select (CS) for the second control byte. Timeslot assignment mode requires that the FS pulse must conform to the delayeddatatiming format. CCR SETTINGS x7 x3 Function Reserved BCLK =.536 MHz or.544 MHz BCLK = 2.48 MHz* BCLK = 4.96 MHz ulaw* ALaw, Including Even Bit Inversion ALaw, No Even Bit Inversion Delayed Data Timing Nondelayed Data Timing* Normal Operation* Digital Loopback (DL) Analog Loopback (AL) Power Amp Enabled in Shutdown Power Amp Disabled in Shutdown* Bit Number and Name X X Note: State at powerup initialization (bit 4 = ) MultiTech Systems, Inc. SocketSLIC Developer s Guide 63

64 Chapter 4 Module Registers Receive Gain Register The receive gain register allows the user to select the gain or loss between the digital interface port and the analog interface port. Receive gain can be programmed in. db steps from 7.3 db to +2. db. This corresponds to a range of dbm levels at the analog output between.987 Vrms and.6 Vrms driving into 6Ohm termination impedance. Telephony signals are usually referenced to a db TLP (transmission level point) level at the digital signal cross connect (DSX) interface. In this case, the digital port is considered the db TLP ( dezi Bell level referenced to the zero transmission level point) To set the receive gain, determine the gain required of the module in order to achieve the desired TLP at the TDM interface. (Usually dbm or 4. dbm) To convert the signal gain to the analog output voltage, use the following formula: V =.7746 Vrms * (Gr/2) To convert the analog output voltage to the signal gain, use the following formula: Gr = 2 * log (V/.7746 Vrms) For example, the factory default setting for transmit gain is +2. db. A signal with a level of dbm presented at the digital input produces an output of 2 dbm at the analog output. When attenuated by 7.3 db a dbm level at the digital input produces a.6 Vrms signal into 6 Ohms at the analog output. RECEIVE PATH db TLP Digital Analog.6 Vrms to Ohms Ohms 7.3 db to +2. db 7.3 dbm to +2.dBm MultiTech Systems, Inc. SocketSLIC Developer s Guide 64

65 RGR Settings [x to x3f] x74 x34 Chapter 4 Module Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db x. x x x x x x x x x xa xb xc xd xe xf x x x x x x x x x x xa xb xc xd xe xf x x x x x x x x x x x2a x2b.7 2. x2c x2d x2e x2f x x x x x x x x x x x3a x3b x3c x3d x3e x3f MultiTech Systems, Inc. SocketSLIC Developer s Guide 65

66 Chapter 4 Module Registers RGR Settings [x4 to x7f] x74 x34 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db x x x x x x x x x x x4a x4b x4c x4d x4e x4f x x x x x x x x x x x5a x5b x5c x5d x5e x5f x x x x x x x x x x x6a x6b x6c x6d x6e x6f x x x x x x x x x x x7a x7b x7c x7d.44.9 x7e x7f.45.7 MultiTech Systems, Inc. SocketSLIC Developer s Guide 66

67 Chapter 4 Module Registers RGR Settings [x8 to xbf] x74 x34 db receive path gain setting is xae. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db x x x x x x x x x x x8a.52.6 x8b.58.5 x8c x8d.53.3 x8e x8f.542. x x x x x x x x x x x9a x9b x9c x9d x9e x9f xa xa xa xa xa xa xa xa xa xa xaa xab xac xad xae xaf xb xb xb xb xb xb xb xb xb xb xba xbb xbc xbd xbe xbf MultiTech Systems, Inc. SocketSLIC Developer s Guide 67

68 Chapter 4 Module Registers RGR Settings [xc to xff] x74 x34 Receive path gain settings greater than xc3 are permitted; however, large signals may cause overload. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db xc xc xc xc xc xc xc xc xc xc xca xcb xcc xcd xce xcf xd xd xd xd xd xd xd xd xd xd xda xdb xdc xdd xde xdf xe xe xe2.4.8 xe xe xe xe xe xe8.5.2 xe xea.546. xeb xec xed.6.7 xee.69.6 xef xf xf xf xf3.74. xf xf xf xf xf xf xfa xfb xfc xfd xfe xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 68

69 Chapter 4 Module Registers Transmit Gain Register The transmit gain register allows the user to select the gain or loss between the analog interface port and the digital interface port. Transmit gain can be programmed in. db steps from.4 db to +9. db. This corresponds to a range of dbm levels at the analog input between.8 Vrms and.87 Vrms driving into the 6ohm termination impedance. Telephony signals are usually referenced to a db TLP (transmission level point) level at the digital signal cross connect (DSX) interface. In this case, the digital port is considered the db TLP ( dezi Bell level referenced to the zero transmission level point). To set the transmit gain, determine the gain required of the module in order to achieve the desired TLP at the digital interface (usually dbm or 2 dbm). In order for the internal hybridbalance circuitry to be effective, the portion of the module analog output to the analog input must be between 2.5 db to.25 db of the analog output. For instance, if the input signal is 6. dbm when the output signal produces dbm, good hybrid balance can be achieved. To convert the signal gain to the analog output voltage, use the following formula: V =.7746 Vrms * (Gx/2) To convert the analog output voltage to the signal gain, use the following formula: Gx = 2 * log (V/.7746 Vrms) For example: The factory default setting for transmit gain is +6. db. A signal with a level of 6. dbm presented at the analog input port produces an output of dbm at the digital port. When amplified by 9. db, a.87 Vrms signal at analog input produces dbm at digital port. TRANSMIT PATH.87 Vrms to.8 Vrms Analog Digital db 6 Ohms.7746 Vrms 9. dbm to +.4 dbm.4 db to Ohms MultiTech Systems, Inc. SocketSLIC Developer s Guide 69

70 TGR Settings [x to x3f] x75 x35 Chapter 4 Module Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db x x x x x x x x x x xa xb xc xd. +.8 xe. +.7 xf x x x x x x x x x x xa xb xc xd xe xf x x x x x x x x x x x2a x2b x2c x2d x2e x2f x x x x x x x x x x x3a x3b x3c x3d x3e x3f MultiTech Systems, Inc. SocketSLIC Developer s Guide 7

71 TGR Settings [x4 to x7f] x75 x35 Chapter 4 Module Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db x x x x x x x x x x x4a x4b x4c x4d x4e x4f x x x x x x x x x x x5a x5b x5c x5d x5e x5f x x x x x x x x x x x6a x6b x6c x6d x6e x6f x x x x x x x x x x x7a.35. x7b x7c x7d x7e x7f.37.6 MultiTech Systems, Inc. SocketSLIC Developer s Guide 7

72 TGR Settings [x8 to xbf] x75 x35 db transmit path gain setting is xbf Chapter 4 Module Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db x x x x x x x x x x x8a.42.7 x8b x8c.43.9 x8d x8e x8f x x x x x x x x x x x9a x9b x9c x9d x9e x9f xa xa xa xa xa xa xa xa xa xa xaa xab xac xad xae xaf xb xb xb xb xb xb xb xb xb xb xba xbb xbc xbd xbe xbf MultiTech Systems, Inc. SocketSLIC Developer s Guide 72

73 TGR Settings [xc to xff] Chapter 4 Module Registers x75 x35 Transmit path gain settings greater than xc3 are permitted; however, large signals may cause overload. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Hex Gain Vrms Gain db xc xc xc xc xc xc xc xc xc xc xca xcb xcc xcd xce xcf xd xd xd xd xd xd xd xd xd xd xda xdb xdc xdd.94. xde.7. xdf.2.2 xe.33.3 xe.46.4 xe xe xe xe5.2.8 xe xe xe xe xea.27.3 xeb xec.3.5 xed.36.6 xee.33.7 xef xf xf xf xf xf xf xf xf xf xf xfa xfb xfc xfd xfe xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 73

74 Chapter 4 Module Registers HybridBalance Registers The Codec HybridBalance Software Program from Lucent Technologies defines the correct settings for the Hybrid Balance Registers, 2, and 3. The settings are dependent on internal component parameters, external circuit parameters, and the termination impedance. Extensive knowledge of transmission theory and complex mathematics is required to setup the transfer functions and run the program which computes the hybrid register settings. The HybridBalance filter is selected for twowire interfaces. The HybridBalance filter is deselected for fourwire interfaces. HBR Settings x76 x36 Byte 2 of Register Function SEL INV SEL2 GAIN (ALL = MAX) HYBAL Filter Deselected HYBAL Filter Selected Cancellation Signal NonInverted Cancellation Signal Inverted HYBAL2 Filter Deselected HYBAL2 Filter Selected Attenuator Values X X X X X HBR2 Settings x77 x37 Byte 2 of Register Function SEL SET ZERO POLE HYBAL Filter Deselected HYBAL Filter Selected HYBAL Filter First Order Selected HYBAL Filter Biquad Selected HYBAL Filter Zero Frequencies X X X HYBAL Filter Pole Frequencies X X X HBR3 Settings x78 x38 Byte 2 of Register Function ZERO POLE HYBAL2 Filter Zero Frequencies X X X X HYBAL2 Filter Pole Frequencies X X X X MultiTech Systems, Inc. SocketSLIC Developer s Guide 74

75 Chapter 4 Module Registers Receive TimeSlot Register The Receive Timeslot Register byte 2 functions are identical to the Receive Timeslot Register byte 2 functions. The new timeslot assignment becomes active on the second frame following end of the CS for the second control byte. RTR Settings x79 x39 T5 is the MSB of the timeslot assignment. Bit Number and Name Function EN PS T5 T4 T3 T2 T T DR TDM Input Disabled X X X X X X DR TDM Input Enabled Assign One Binary Coded Timeslot from 63 Note: T5 is the MSB of the timeslot assignment. Transmit TimeSlot Register The Transmit Timeslot Register byte 2 functions are identical to the Receive Timeslot Register byte 2 functions. The new timeslot assignment becomes active on the second frame following end of the CS for the second control byte. TTR Settings x7a x3a Note: T5 is the MSB of the timeslot assignment. Bit Number and Name Function EN PS T5 T4 T3 T2 T T DX TDM Output Disabled X X X X X X DX TDM Output Enabled Assign One Binary Coded Timeslot from 63 Note: T5 is the MSB of the timeslot assignment. MultiTech Systems, Inc. SocketSLIC Developer s Guide 75

76 Chapter 4 Module Registers Delay Dial Register The Delay Dial Register (DDR) allows the user to select the duration of the wink signal when the FXS port is setup for AutoWINK operation. The delay between the start of the wink signal and the end of the wink signal can be set in ms increments. The answer delay timing range is adjustable from ms to 2.54s. DDR Settings x7b x3b Bit Number Function Hex INVALID x ms x 2ms x2 3ms x3 4ms x4 5ms x5 6ms x6 7ms x7 8ms x8 9ms x9 ms xa ms xb 2ms xc 3ms xd 4ms xe 5ms xf 6ms x 7ms x 8ms x2 9ms x3 2ms x4 2ms x5 22ms x6 23ms x7 24ms x8 25ms x9 26ms xa 27ms xb 28ms xc 29ms xd 3ms xe 3ms xf 32ms x2 33ms x2 34ms x22 35ms x23 36ms x24 37ms x25 38ms x26 39ms x27 4ms x28 4ms x29 42ms x2a 43ms x2b 44ms x2c 45ms x2d 46ms x2e 47ms x2f 48ms x3 49ms x3 5ms x32 5ms x33 52ms x34 53ms x35 54ms x36 55ms x37 MultiTech Systems, Inc. SocketSLIC Developer s Guide 76

77 Chapter 4 Module Registers Continued from previous page: Bit Number Function Hex 56ms x38 57ms x39 58ms x3a 59ms x3b 6ms x3c 6ms x3d \ \ \ \ \ \ \ \ To 2.54s xfe DISABLED xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 77

78 Chapter 4 Module Registers SPI Control Register The SPI control register allows the user to set specific SPI modes. Writing to bit 2 selects the SPI Clock Phase Writing to bit 3 selects the SPI Clock Polarity Writing to bit 5 selects the SPI Data Order SPCR Settings x7c x3c Bit Number Function Reserved Reserved SPI Data Order MSB First (default) SPI Data Order LSB First Reserved SPI Clock Polarity Low When Idle (default) SPI Clock Polarity High When Idle Reserved X SPI Clock Phase Trailing Edge SPI Clock Phase Leading Edge (default) Reserved Reserved MultiTech Systems, Inc. SocketSLIC Developer s Guide 78

79 Chapter 4 Module Registers Wink Delay Register The wink delay register allows the user to select the wink timing delay when the FXS port is setup for AutoWink operation. When the ringing FXS analog port is answered then an automatic wink signal of 2ms duration is being issued on the digital CAS bit side. The timing delay between the analog offhook and digital wink signal can be set in ms increments. The winkdelay timing range is adjustable from ms to 25.4 seconds. WDR Settings x7d x3d Bit Number Function Hex INVALID x ms x 2ms x2 3ms x3 4ms x4 5ms x5 6ms x6 7ms x7 8ms x8 9ms x9 s xa.s xb.2s xc.3s xd.4s xe.5s xf.6s x.7s x.8s x2.9s x3 2.s x4 2.s x5 2.2s x6 2.3s x7 2.4s x8 2.5s x9 2.6s xa 2.7s xb 2.8s xc 2.9s xd 3.s xe 3.s xf 3.2s x2 3.3s x2 3.4s x22 3.5s x23 3.6s x24 3.7s x25 3.8s x26 3.9s x27 4.s x28 4.s x29 4.2s x2a 4.3s x2b 4.4s x2c 4.5s x2d 4.6s x2e 4.7s x2f 4.8s x3 4.9s x3 5.s x32 5.s x33 5.2s x34 MultiTech Systems, Inc. SocketSLIC Developer s Guide 79

80 Chapter 4 Module Registers Continued from previous page: Bit Number Function Hex 5.3s x35 5.4s x36 5.5s x37 5.6s x38 5.7s x39 5.8s x3a 5.9s x3b 6.s x3c 6.s x3d 6.2s x3e \ \ \ \ \ \ \ \ To 25.4 xfe DISABLED xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 8

81 Answer Delay Register Chapter 4 Module Registers The answer delay register allows the user to select the answer timing delay when the FXS port is setup for AutoFlash operation. When the ringing FXS analog port is answered then an answer signal is being issued on the digital CAS bit side either through hookflash control or through the answer delay timeout. The timing delay between the analog offhook and digital answer signal can be set in ms increments. The answer delay timing range is adjustable from ms to 25.4 seconds. ADR Settings x7e x3e Bit Number Function Hex INVALID x ms x 2ms x2 3ms x3 4ms x4 5ms x5 6ms x6 7ms x7 8ms x8 9ms x9 s xa.s xb.2s xc.3s xd.4s xe.5s xf.6s x.7s x.8s x2.9s x3 2.s x4 2.s x5 2.2s x6 2.3s x7 2.4s x8 2.5s x9 2.6s xa 2.7s xb 2.8s xc 2.9s xd 3.s xe 3.s xf 3.2s x2 3.3s x2 3.4s x22 3.5s x23 3.6s x24 3.7s x25 3.8s x26 3.9s x27 4.s x28 4.s x29 4.2s x2a 4.3s x2b 4.4s x2c 4.5s x2d 4.6s x2e 4.7s x2f 4.8s x3 4.9s x3 5.s x32 5.s x33 5.2s x34 MultiTech Systems, Inc. SocketSLIC Developer s Guide 8

82 Chapter 4 Module Registers Continued from previous page: Bit Number Function Hex 5.3s x35 5.4s x36 5.5s x37 5.6s x38 5.7s x39 5.8s x3a 5.9s x3b 6.s x3c 6.s x3d \ \ \ \ \ \ \ \ To 25.4 xfe DISABLED xff MultiTech Systems, Inc. SocketSLIC Developer s Guide 82

83 Chapter 4 Module Registers Reset Count Register The RCR keeps track of how often the module has been reset since start of operation. The RCR can be reset by writing zeros into it. A module reset can occur due to the following events: Regular PowerUp Operation Module Reset Pin Asserted Internal Watchdog Timer Triggered RCR Settings x7f x3f Bit Number and Name Function Current Reset Count Value X X X X X X X X MultiTech Systems, Inc. SocketSLIC Developer s Guide 83

84 Chapter 5 System Design Considerations Chapter 5 System Design Considerations System Design Considerations: Power Grounding Safety Telecom Emissions To Protect the Product Against Outside World Threats: Power Line Crossings Transient Voltage Surges Electrostatic Discharges To Prevent System Noise from Reaching the Outside World: Conducted Emissions Radiated Emissions To Stabilize the Module s +5Vdc Power Source: Power Entry Filtering Current Spike Smoothing Temporary Energy Storage To Meet Telecom and Safety Requirements: Domestically Globally Electromagnetic Interference (EMI) Considerations The following guidelines are offered specifically to help minimize EMI generation. Some of these guidelines are the same as, or similar to, the general guidelines but are mentioned again to reinforce their importance. In order to minimize the contribution of the SocketModembased design to EMI, the designer must understand the major sources of EMI and how to reduce them to acceptable levels.. Keep traces carrying high frequency signals as short as possible. 2. Provide a good ground plane or grid. In some cases, a multilayer board may be required with full layers for ground and power distribution. 3. Decouple power from ground with decoupling capacitors as close to the SocketModem power pins as possible. 4. Eliminate ground loops, which are unexpected current return paths to the power source and ground. 5. Decouple the telephone line cables at the telephone line jacks. Typically, use a combination of series inductors, common mode chokes, and shunt capacitors. Methods to decouple telephone lines are similar to decoupling power lines; however, telephone line decoupling may be more difficult and deserves additional attention. A commonly used design aid is to place footprints for these components and populate as necessary during performance/emi testing and certification. 6. Decouple the power cord at the power cord interface with decoupling capacitors. Methods to decouple power lines are similar to decoupling telephone lines. 7. Locate high frequency circuits in a separate area to minimize capacitive coupling to other circuits. 8. Locate cables and connectors so as to avoid coupling from high frequency circuits. 9. Lay out the highest frequency signal traces next to the ground grid.. If a multilayer board design is used, make no cuts in the ground or power planes and be sure the ground plane covers all traces.. Minimize the number of throughhole connections on traces carrying high frequency signals. 2. Avoid right angle turns on high frequency traces. Fortyfive degree corners are good; however, radius turns are better. MultiTech Systems, Inc. SocketSLIC Developer s Guide 84

85 Chapter 5 System Design Considerations 3. On 2layer boards with no ground grid, provide a shadow ground trace on the opposite side of the board to traces carrying high frequency signals. This will be effective as a high frequency ground return if it is three times the width of the signal traces. 4. Distribute high frequency signals continuously on a single trace rather than several traces radiating from one point. Electrostatic Discharge Control All electronic devices should be handled with certain precautions to avoid damage due to the accumulation of static charge. See the ANSI/ESD Association Standard (ANSI/ESD S2.2999) a document for the Development of an Electrostatic Discharge Control for Protection of Electrical and Electronic Parts, Assemblies and Equipment. This document covers ESD Control Program Administrative Requirements, ESD Training, ESD Control Program Plan Technical Requirements (grounding/bonding systems, personnel grooming, protected areas, packaging, marking, equipment, and handling), and Sensitivity Testing. MultiTech Systems, Inc. strives to follow all of these recommendations. Input protection circuitry has been incorporated into the MultiTech devices to minimize the effect of this static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling. MultiTech uses and recommends that others use antistatic boxes that create a faraday cage (packaging designed to exclude electromagnetic fields). MultiTech recommends that you use our packaging when returning a product and when you ship your products to your customers. Phone Line Warning Statement for the Developer Board Use extreme caution when the phone line is installed due to live energized components. In fact, do not touch any components on the board while the phone line is installed. In addition, the phone line should be detached when making modifications to or servicing the developer board. For other telephone warnings, refer to the Telecom Warnings listed earlier in this chapter. MultiTech Systems, Inc. SocketSLIC Developer s Guide 85

86 Chapter 6 Power Considerations Chapter 6 Power Considerations In order to achieve low power dissipation the following considerations should be followed: Power Supply Power Dissipation Power Management Power Supply It is recommended that the standard CMOS practice of applying ground to the device before any other connections are made should always be followed. The module by itself is not designed for hotswap ability. A bypass capacitor of 47 uf, 6.3Vdc, low ESR should be connected between the each modules power pins. The board power supply input should also be decoupled with a low effective series resistance (ESR) capacitor of at least uf located at the printed circuit board power entry point. For electromagnetic compatibility (EMC) use of at least one set of power and ground planes within a multilayer printed circuit board (PCB) is strongly recommended. A stable, low ESR and regulated power supply is required for optimum and troublefree module operation. Power Dissipation The SocketSLIC power dissipation varies between different interface and mode settings. Refer to the table below for power budget requirements in multiport system designs under the following conditions:. Interface is at idle condition OnHook (no ringing, no AC or DC load) 2. Interface is at alerting condition Ringing (ringing into an AC load) 3. Interface is at seize condition OffHook (powering a DC load) INTERFACE Supply Current MA Supply Current ma Supply Current MA. ONHOOK No load 2. RINGING 2.2uF//3.9 kohms 3. OFFHOOK Ohms SHUTDOWN 4 RESET INACTIVE 22 FXSLS FXSRB FXSGS DPO FXOLS 4 FXORB 4 FXOGS 4 DPT 4 TO/ETO 4 E&M, I E&M, II E&M, III E&M, IV E&M, V PLR, I PLR, II PLR, III PLR, IV PLR, V MultiTech Systems, Inc. SocketSLIC Developer s Guide 86

87 Chapter 6 Power Considerations Power Management Considering the management of the following registers reduces power consumption during operation: Module Mode Register (shut down the module when the port is not assigned) Telecom Voltage Register (reduce telecom voltage for short haul applications) Ring Voltage Register (reduce ringing voltage for short haul applications) Ring Pattern Register (see below) When operating multiple modules on the same power supply consider managing the alerting pattern (ring cadence) via the CAS bits from the host controller. That way each module can be instructed to ring while the other modules are not ringing. PowerUp When power is first applied, the module should be held in the reset state. After the supply voltage and the externally applied logic levels have been stabilized the reset may be released. After reset has been released, the module reverts to the factory default settings. ShutDown Writing x to the module mode register (MMR) instructs the module to shutdown and go to sleep. The power consumption is the lowest while in this state. The processor is shutdown thus reading and writing to and from the internal registers is not possible. A hard module reset is required to powerup the module from this state and start the initialization sequence. Reset Pulling the reset pin high causes the module to enter its reset state. There is no limit on how long the reset state may remain active. The power consumption is reduced while in this state. All module functions are disabled. Pulling the reset pin low releases the module from the reset state and starts the initialization sequence. For normal operation the reset pin must be pulled low. It is recommended to use a reset generator integrated circuit (IC) to provide proper powerup reset control. The module has a user accessible reset count register that keeps track of how often the module reset has been released. This feature comes in handy to check how often the modulereset pin or power supply has been cycled. The reset counter can be preset or cleared as needed. Inactive Writing x to the interface selection register (ISR) instructs the analog port to enter the inactive state. All analog interface operation stops, the Codec is shut down and the telecom power supply is shutoff. The power consumption in this state is about half of the interface idle state. The processor is still active and reading and writing through the control interface port is possible. A different interface selection is required to change this state. All registers are initialized. PowerOff We recommend that data not be written to the module before and during removal of power. MultiTech Systems, Inc. SocketSLIC Developer s Guide 87

88 Chapter 7 Port HookUps Chapter 7 Port HookUps FXO, FXS, DPO AND DPT 2W, E&M I 2W, E&M II 2W, E&M III SB (not used) SG (not used) T (not used) E/TIP Tip Lead (transmit/receive talkpath and signaling) M/RING Ring Lead (transmit/receive talkpath and signaling) R (not used) TRC (not used) R (not used) T (not used) SB (not used) SG (not used) T TLead (transmit/receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (transmit/receive talkpath) TRC Ground (common ground) R (not used) T (not used) SB SBLead (receive signaling/battery) SG SGLead (transmit signaling/looped) T TLead (transmit/receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (transmit/receive talkpath) TRC (not used) R (not used) T (not used) SB SBLead (receive signaling/battery) SG SGLead (receive signaling/ground) T TLead (transmit/receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (transmit/receive talkpath) TRC Ground (common ground) R (not used) T (not used) 2W, E&M IV Notes: The following module pins must be relabeled for E&M type IV interface operation: The Elead pin becomes the Mlead. The Mlead pin becomes the Elead. The SGlead pin becomes the SBlead. The SBlead pin becomes the SGlead. SB SGLead (receive signaling/ground) SG SBLead (transmit signaling/looped) T TLead (transmit/receive talkpath) E MLead (transmit signaling) M ELead (receive signaling) R RLead (transmit/receive talkpath) TRC (not used) R (not used) T (not used) MultiTech Systems, Inc. SocketSLIC Developer s Guide 88

89 Chapter 7 Port HookUps 2W, E&M V SB (not used) SG (not used) T TLead (transmit/receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (transmit/receive talkpath) TRC Ground (common ground) R (not used) T (not used) 2W, TO 2W, PLR I 2W, PLR II 2W, PLR III 2W, PLR IV SB (not used) SG (not used) T TLead (transmit/receive talkpath) E (not used) M (not used) R RLead (transmit/receive talkpath) TRC (not used) R (not used) T (not used) SB (not used) SG (not used) T TLead (transmit/receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (transmit/receive talkpath) TRC Ground (common ground) R (not used) T (not used) SB SBLead (transmit signaling/looped) SG SGLead (receive signaling/ground) T TLead (transmit/receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (transmit/receive talkpath) TRC (not used) R (not used) T (not used) SB SBLead (transmit signaling/looped/active) SG SGLead (transmit signaling/looped/idle) T TLead (transmit/receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (transmit/receive talkpath) TRC Ground (common ground) R (not used) T (not used) SB SBLead (transmit signaling/looped) SG SGLead (receive signaling/ground) T TLead (transmit/receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (transmit/receive talkpath) TRC (not used) R (not used) T (not used) MultiTech Systems, Inc. SocketSLIC Developer s Guide 89

90 Chapter 7 Port HookUps 2W, PLR V SB (not used) SG (not used) T TLead (transmit/receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (transmit/receive talkpath) TRC Ground (common ground) R (not used) T (not used) 4W, ETO 4W, E&M I 4W, E&M II 4W, E&M III SB (not used) SG (not used) T TLead (receive talkpath) E (not used) M (not used) R RLead (receive talkpath) TRC (not used) R RLead (transmit talkpath) T TLead (transmit talkpath) SB (not used) SG (not used) T TLead (receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (receive talkpath) TRC Ground (common ground) R RLead (transmit talkpath) T TLead (transmit talkpath) SB SBLead (receive signaling/battery) SG SGLead (transmit signaling/looped) T TLead (receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (receive talkpath) TRC (not used) R RLead (transmit talkpath) T TLead (transmit talkpath) SB SBLead (receive signaling/battery) SG SGLead (receive signaling/ground) T TLead (receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (receive talkpath) TRC Ground (common ground) R RLead (transmit talkpath) T TLead (transmit talkpath) MultiTech Systems, Inc. SocketSLIC Developer s Guide 9

91 Chapter 7 Port HookUps 4W, E&M IV Note: The following module pins must be relabeled for E&M type IV interface operation: The Elead pin becomes the Mlead. The Mlead pin becomes the Elead. The SGlead pin becomes the SBlead. The SBlead pin becomes the SGlead. SB SGLead (receive signaling/ground) SG SBLead (transmit signaling/looped) T TLead (receive talkpath) E MLead (transmit signaling) M ELead (receive signaling) R RLead (receive talkpath) TRC (not used) R RLead (transmit talkpath) T TLead (transmit talkpath) 4W, E&M V 4W, PLR I 4W, PLR II 4W, PLR III SB (not used) SG (not used) T TLead (receive talkpath) E ELead (transmit signaling) M MLead (receive signaling) R RLead (receive talkpath) TRC Ground (common ground) R RLead (transmit talkpath) T TLead (transmit talkpath) SB (not used) SG (not used) T TLead (receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (receive talkpath) TRC Ground (common ground) R RLead (transmit talkpath) T TLead (transmit talkpath) SB SBLead (transmit signaling/looped) SG SBLead (receive signaling/ground) T TLead (receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (receive talkpath) TRC (not used) R RLead (transmit talkpath) T TLead (transmit talkpath) SB SBLead ((transmit signaling/looped/active) SG SGLead (transmit signaling/looped/idle) T TLead (receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (receive talkpath) TRC Ground (common ground) R RLead (transmit talkpath) T TLead (transmit talkpath) MultiTech Systems, Inc. SocketSLIC Developer s Guide 9

92 Chapter 7 Port HookUps 4W, PLR IV 4W, PLR V SB SBLead (transmit signaling/looped) SG SGLead (receive signaling/ground) T TLead (receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (receive talkpath) TRC (not used) R RLead (transmit talkpath) T TLead (transmit talkpath) SB (not used) SG (not used) T TLead (receive talkpath) E ELead (receive signaling) M MLead (transmit signaling) R RLead (receive talkpath) TRC Ground (common ground) R RLead (transmit talkpath) T TLead (transmit talkpath) MultiTech Systems, Inc. SocketSLIC Developer s Guide 92

93 Chapter 8 Specifications Chapter 8 Specifications Ports Per Module Analog Port Digital Port Control Port Analog Interfaces Foreign Exchange Subscriber Foreign Exchange Office Dial Pulse Originating Dial Pulse Terminating E&M Lead Signaling Pulse Link Repeater Equalized Transmission Only Transmission Only FXS FXO DPO DPT E&M PLR ETO TO (LoopStart, GroundStart or Reverse Battery) (LoopStart, GroundStart or Reverse Battery) (LoopReverseBatterySignaling, DID ) (LoopReverseBatterySignaling, DOD ) (2Wire or 4Wire) (2Wire or 4Wire) (4Wire) (2Wire) Digital Interfaces AT&T MultiVendor Integration Protocol Mitel CHI MVIP STBus (Concentration Highway Interface) (subset) (2.48 Mbps) Command Interfaces SPI Interface UART Interface Synchronous Serial Asynchronous Serial Termination Analog Port Digital Port Command Port 9Pin 9Pin 9Pin (Header with 2mm pitch) (Header with 2mm pitch) (Header with 2mm pitch) Power Requirements Voltage Tolerance Current Power +5 Vdc +/5 %.425 A 2.25 W (Nominal) (Maximum) (Maximum) (Maximum) Dimensions Length Depth Height (seated) (9.525 cm) (2.75 cm) (.372 cm) Environmental Operating Temperature Storage Temperature Humidity +32 F to +4 F 4 F to +85 F 5 % to 95 % ( C to 4 C) (4 C to +85 C) (noncondensing) Weight Net Weight oz (28 g) MultiTech Systems, Inc. SocketSLIC Developer s Guide 93

94 Chapter 8 Specifications Technical Data PARAMETERS MIN TYP MAX UNIT CONDITION AUDIO FREQUENCY RESPONSE 3. 3,4. Hz.5 db AUDIO IMPEDANCE Ohms 3 Hz3 Hz TRANSMIT GAIN RANGE Ohms TRANSMIT GAIN STEP. db RECEIVE GAIN RANGE Ohms RECEIVE GAIN STEP. db RETURN LOSS 34. db 3 Hz3 Hz TRANSHYBRID LOSS 24. Ohms CROSS TALK 8. Ohms LONGITUDINAL BALANCE 6. db 2 Hz Hz LONGITUDINAL BALANCE 4. db Hz4 Hz DISTORTION, SINGLE FREQUENCY 46. db 4 dbm DISTORTION, INTER MODULATION 4. Ohms IDLE CHANNEL NOISE 2. Ohms BATTERY RESISTANCE Ohms BATTERY VOLTAGE (typical) Vdc BATTERY CURRENT ma LOOP RESISTANCE 2,4. Ohms LOOP VOLTAGE Vdc LOOP CURRENT ma OFFHOOK RESISTANCE 2. Ohms OFFHOOK VOLTAGE Vdc OFFHOOK CURRENT ma ONHOOK RESISTANCE 3,. Ohms ONHOOK VOLTAGE Vdc ONHOOK CURRENT..76 ma RING FREQUENCY Hz RING LOAD. 5. REN RING VOLTAGE Vrms RING TRIP TIME Ohms LOOP DETECT CURRENT FOR Tip/E 6. ma LOOP DETECT CURRENT FOR 3. ma Ring/M MultiTech Systems, Inc. SocketSLIC Developer s Guide 94

95 Chapter 8 Specifications Characteristics ELECTRICAL TDM (as per Lucent Codec T757) SPI (as per Atmel Microcontroller AT89S8252) UART (as per Atmel Microcontroller AT89S8252) TRANSMISSION TDM (as per Lucent Codec T757) SPI (as per Atmel Microcontroller AT89S8252) UART (as per Atmel Microcontroller AT89S8252) TIMING TDM (as per Lucent Codec T757) SPI (as per Atmel Microcontroller AT89S8252) UART (as per Atmel Microcontroller AT89S8252) Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings can cause permanent damage to the module. These are absolute stress ratings only. Functional operation of the module is not implied at these or any other conditions in excess of those given in the technical data sections of this manual. Exposure to absolute maximum rating conditions for extended periods can affect the module reliability. PARAMETERS MIN MAX UNIT Storage Temperature C Operating Temperature. +7. C Logic Power Supply Voltage +6.5 V Logic Pins in Reference to Ground V Logic DC Output Current 5. ma MultiTech Systems, Inc. SocketSLIC Developer s Guide 95

96 Chapter 8 Specifications Facility Interface Codes The Federal Communications Commission (FCC) has established different Facility Interface Codes (FIC) defining registered interfaces. Those codes are tariff references used by customers to order the type of service from the local servicing Phone Company. Please note that the FCC does not issue FIC codes for certain interfaces. Those interfaces are typically associated either with CO switches or PBX station interfaces. FACILITY INTERFACE CODE LOOP FXSLS LOOP FXSRB LOOP FXSGS LOOP DPO 2RV2T LOOP FXOLS 2LS2 LOOP FXORB LOOP FXOGS 2GS2 LOOP DPT E&M 2W, E&M, I TLE E&M 2W, E&M, II TL2E E&M 2W, E&M, III E&M 2W, E&M, IV E&M 2W, E&M, V E&M 2W, PLR, I TLM E&M 2W, PLR, II TL2M E&M 2W, PLR, III E&M 2W, PLR, IV E&M 2W, PLR, V E&M 4W, E&M, I TL3E E&M 4W, E&M, II TL32E E&M 4W, E&M, III E&M 4W, E&M, IV E&M 4W, E&M, V E&M 4W, PLR, I TL3M E&M 4W, PLR, II TL32M E&M 4W, PLR, III E&M 4W, PLR, IV E&M 4W, PLR, V MultiTech Systems, Inc. SocketSLIC Developer s Guide 96

97 Appendix A SocketSLIC Developer Board Appendix A SocketSLIC Developer Board Customers planning to use the SocketSLIC in an application of any significant complexity will need to conduct tests using it in a prototype of the system in which it will ultimately operate. MultiTech developed the IFM Developer s Board for this purpose. Customers who have identified their SocketSLIC application or are considering an application can use the Developer Board for evaluation and development. SocketSLIC Developer Board SocketSLIC Developer Kit Contents The SocketSLIC Developer Kit contains the following: Two SocketSLIC units are included so that a full bidirectional coding/decoding path can be constructed. One Developer Test Card/Developer Board One Universal Power Supply One DB9 to RJ45 cable One SocketSLIC CD MultiTech Systems, Inc. SocketSLIC Developer s Guide 97

98 Appendix A SocketSLIC Developer Board LED Descriptions LEDs FOR CHANNELS & RSG XSG ARCV BRCV AXMT BXMT CS RESET POWER DESCRIPTION RECEIVE SIGNALING This active high output indicates the outgoing analog signaling state. TRANMIT SIGNALING This active high output indicates the incoming analog signaling state. RECEIVE A CAS BIT This input receives the A signaling bit that controls the outgoing analog signaling state. RECEIVE B CAS BIT This input receives the B signaling bit that controls the outgoing analog signaling state. TRANSMIT A CAS BIT This output transmits the A signaling bit that indicates the incoming analog signaling state. TRANSMIT B CAS BIT This output transmits the B signaling bit that indicates the incoming analog signaling state. CHIP SELECT This input receives the chip select signal for the SPI and UART ports. RESET This active high input must be pulled low for normal operation. When pulled momentarily high for at least us, (LED lights during RESET) all programmable registers in the device are reset to the states specified under powerup utilization. Power The Power LED lights when the power is applied. Dip Switches Dip Switches through 4 correspond to the MTIFM in location (Channel ) Switch Closed RESET MTIFM is held in reset. Switch 2 Closed CS Active chipselect signal to MTIFM. CS and CS should not be activated at the same time. Switch 3 Closed AXMT A signaling bit to MTIFM. Switch 4 Closed BXMT B signaling bit to MTIFM. Dip Switches 5 through 8 correspond to the MTIFM in location (Channel ) Switch 5 Closed RESET MTIFM is held in reset. Switch 6 Closed CS Active chipselect signal to MTIFM. CS and CS should not be activated at the same time. Switch 7 Closed AXMT A signaling bit to MTIFM. Switch 8 Closed BXMT B signaling bit to MTIFM. Dip Switches 9 through 2 allow flexibility in connecting the PCM source and MTIFMs Switch 9 Closed PCMSRC PCM clock and frame sync sources connected to MTIFM. Switch 9 Open PCMSRC Disconnects the PCM source from MTIFM allowing an external source to be connected on the header pins. Switch Closed PCMSS PCM signals of MTIFM are connected to MTIFM. If PCMSRC is also closed, MTIFM and MTIFM receive the PCM clock and frame sync from the onboard source. Switch Open PCMSS Isolates the PCM interface of MTIFM from the PCM source and MTIFM. Switch Closed ABSS XMT and RCV A&B signaling bits are connected between MTIFM and MTIFM. The ARCV signaling bit connects to AXMT and BRCV to BXMT in both directions. Switch Open ABSS Allows A&B bit control via the header pins for MTIFM or Dip Switches for both MTIFMs. MultiTech Systems, Inc. SocketSLIC Developer s Guide 98

99 Appendix A SocketSLIC Developer Board Example Using the Developer Board to Test an Application The following block diagram shows a simple configuration that can be used to check voice quality through the MTIFMs. To Setup the Test Card: Connect an analog telephone to the FXO/FXS jack on the test card Connect a telephone cable to the FXO/FXS jack on the test card. This connects the PSTN POTS line to the analog telephone through the MTIFMs. To Configure the Module on Channel : Set Dip Switch 2 down Set Dip Switch 6 up Set Dip Switches 9 through down Set the remaining switches up Then connect a COM port from your PC to the Command port jack on the test card Set the PC COM port for 9.2K bps in order to communicate with the test card. Using Hyperterminal to configure Channel, enter the following values: Important: Be sure to use upper case letters. Command Description 22 Defaults the MTIFM 282 Set FXS interface Telephone 398 PCM Receive time slot 3A8 PCM Transmit time slot MultiTech Systems, Inc. SocketSLIC Developer s Guide 99

100 Appendix A SocketSLIC Developer Board To Configure the Module on Channel : Set Dip Switch 6 down Set Dip Switch 2 up Set Dip Switches 9 through down Set the remaining switches up Then enter the following values: Command Description 22 Defaults the MTIFM 28 Set FXO interface Phone Line 398 PCM Receive time slot 3A8 PCM Transmit time slot MultiTech Systems, Inc. SocketSLIC Developer s Guide

101 Appendix B SocketSLIC Developer Board Schematics and Recommended Parts Appendix B SocketSLIC Developer Board Schematics and Recommended Parts General Block Diagram MultiTech Systems, Inc. SocketSLIC Developer s Guide

102 Appendix B SocketSLIC Developer Board Schematics and Recommended Parts Developer Board Schematics MultiTech Systems, Inc. SocketSLIC Developer s Guide 2

103 Appendix B SocketSLIC Developer Board Schematics and Recommended Parts Developer Board Schematics MultiTech Systems, Inc. SocketSLIC Developer s Guide 3

104 Appendix B SocketSLIC Developer Board Schematics and Recommended Parts Developer Board Schematics MultiTech Systems, Inc. SocketSLIC Developer s Guide 4

105 Recommended Parts Appendix B SocketSLIC Developer Board Schematics and Recommended Parts Disclaimer: MultiTech Systems makes no warranty claims for vendor product recommendations listed below. Other vendor products may or may not operate satisfactorily. MultiTech System s recommended vendor products only indicate that the product has been tested in controlled conditions and were found to perform satisfactorily. Surface mount ferrites are used on T&R (Tip and Ring) to mitigate emission levels out the RJ cable. 22pF capacitors are also used on T&R to reduce the common mode emissions that may be present in certain systems. The ferrite and capacitors also aid in reducing the effects of transients that may be present on the line. Note: These parts are RoHS compliant. Recommended Ferrite (SMT) Manufacturer Associated Component Technology (ACT) Manufacturer Murata Erie Recommended Ferrite (ThruHole) Manufacturer Associated Component Technology (ACT) Part # CBZ26223LF Part # BLM3AJ6SNL Part # WB22.OT Recommended Capacitor (SMT) Manufacturer NOVACAP Part # ES22N22K52NXT Manufacturer Murata Erie Part # GA355DR7GC22KY2L Recommended Capacitor (ThruHole) Manufacturer Ever Grace Electronic Industrials Part # YP22K2EA7PS8. Manufacturer Murata Erie Part # DE2B3KH22KA3B Note: Capacitors used on T&R must have the Y2 safety rating. Recommended RJ Connector Manufacturer Full Rise Electronic Co. Part # E5964P45 Recommended Sidactor Tip to Ground, Ring to Ground Manufacturer RayChem / Tyco Electronics Part # TVB4MSCL Manufacturer ST Microelectronics Part# SMPMC4 Recommended Sidactor Across Tip and Ring Manufacturer ST Microelectronics Part# SMTPA27 Recommended Poly Switch Thermal Fuse (ThruHole) Manufacturer RayChem (Tyco Electronics) Part# TRF65 or TRF652 Note: The Fuse & Sidactor are required in order to comply with UL695 for protection against overvoltages from power line cross. Fuse can be reset type. Common Mode Choke Manufacturer TDK Part # ZJYS5R52PT Recommended Transceiver Manufacturer Analog Devices Part # ADM27EARZ SIP Connector Manufacturer Neltron Industrial Co. ( Part #229SxxSG 4Pin 2.mm SIP Socket (2 Each) Pin 2.mm SIP Socket (2 Each) Telecom The RJ connector must meet FCC Part 68 requirements. Refer to FCC Part 68 section 68.5 subpart F for connector specifications. A selfhealing fuse is used in series with line to help prevent damage to the DAA circuit. This fuse is required in order to comply with compliance regulations. MultiTech Systems, Inc. SocketSLIC Developer s Guide 5

106 Appendix C Tip and Ring Interface Appendix C Tip and Ring Interface Tip and Ring for the SocketSLIC MultiTech Systems, Inc. SocketSLIC Developer s Guide 6

107 Appendix D Regulatory and Compliance Statements Appendix D Regulatory and Compliance Statements EMC Compliance and Requirements EMC, Safety, and R&TTE Directive Compliance The CE mark is affixed to this product to confirm compliance with the following European Community Directives: Council Directive 24/8/EC of 5 December 24 on the approximation of the laws of Member States relating to electromagnetic compatibility; and Council Directive 26/95/EC of 2 December 26 on the harmonization of the laws of Member States relating to electrical equipment designed for use within certain voltage limits; and Council Directive 999/5/EC of 9 March 999 on radio equipment and telecommunications terminal equipment and the mutual recognition of their conformity. International Modem Restrictions Some dialing and answering defaults and restrictions may vary for international modems. Changing settings may cause a modem to become noncompliant with national telecom requirements in specific countries. Also note that some software packages may have features or lack restrictions that may cause the modem to become noncompliant. EMC Requirements for the United States FCC 47 CFR Part 5 Regulations This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to 47 CFR Part 5 regulations. The stated limits in this regulation are designed to provide reasonable protection against harmful interference in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy, and if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Plug the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/tv technician for help. This device complies with Part 5 of the 47 CFR rules. Operation of this device is subject to the following conditions:. This device may not cause harmful interference, and 2. This device must accept any interference that may cause undesired operation. Warning: Changes or modifications to this unit not expressly approved by the party responsible for compliance could void the user s authority to operate the equipment. EMC Requirements for Industry Canada This Class A digital apparatus meets all requirements of the Canadian InterferenceCausing Equipment Regulations. Cet appareil numérique de la classe A respecte toutes les exigences du Reglement Canadien sur le matériel brouilleur. MultiTech Systems, Inc. SocketSLIC Developer s Guide 7

108 Appendix D Regulatory and Compliance Statements FCC Part 68 The Federal Communications Commission (FCC) has established rules that permit this equipment to be directly connected to the public switched telephone network (PSTN). Standardized jacks are used for these connections. This equipment should not be used on party lines or coin lines. If this equipment is malfunctioning, it may be causing harm to the telephone network. This equipment should be disconnected until the source of the problem can be determined and until repair has been made. If repair is not done, the Telephone Company may temporarily disconnect service. The Telephone Company may make changes in its technical operations and procedures; if such changes affect the compatibility of this equipment, the Telephone Company is required to give adequate notice of the changes. You will be advised of your right to file a complaint with the FCC. If the Telephone Company requests information on what equipment is connected to their lines, please inform them of the following: The Telephone Number This Unit Is Connected To (NBR #) The Ringer Equivalence Number (REN #) The Universal Service Order Code Jack Required (USOC #) The Service Order Code (SOC #) The Facility Interface Code (FIC #) The FCC Registration Number (FCC #) DID Information Notice: Allowing this equipment to be operated in such a manner as not to provide PROPER ANSWER SUPERVISION is in violation of Part 68 of the FCC 47 CFR rules. and PROPER ANSWER SUPERVISION is when this equipment returns answer supervision to the PSTN when DID calls are: Answered by the called station Answered by an attendant Routed to a recorded announcement that can be administered by the CPE user Routed to a dial prompt This equipment returns answer supervision for all directinwarddialing calls forwarded to the PSTN. Permissible exceptions are: A call is unanswered A busy tone is received A reorder tone is received MultiTech Systems, Inc. SocketSLIC Developer s Guide 8

109 Appendix D Regulatory and Compliance Statements Waste Electrical and Electronic Equipment Statement Note to OEMs: The statement is included for your information and may be used in the documentation of your final product applications. WEEE Directive The WEEE directive places an obligation on EUbased manufacturers, distributors, retailers, and importers to takeback electronics products at the end of their useful life. A sister Directive, ROHS (Restriction of Hazardous Substances) complements the WEEE Directive by banning the presence of specific hazardous substances in the products at the design phase. The WEEE Directive covers all MultiTech products imported into the EU as of August 3, 25. EUbased manufacturers, distributors, retailers and importers are obliged to finance the costs of recovery from municipal collection points, reuse, and recycling of specified percentages per the WEEE requirements. Instructions for Disposal of WEEE by Users in the European Union The symbol shown below is on the product or on its packaging, which indicates that this product must not be disposed of with other waste. Instead, it is the user s responsibility to dispose of their waste equipment by handing it over to a designated collection point for the recycling of waste electrical and electronic equipment. The separate collection and recycling of your waste equipment at the time of disposal will help to conserve natural resources and ensure that it is recycled in a manner that protects human health and the environment. For more information about where you can drop off your waste equipment for recycling, please contact your local city office, your household waste disposal service or where you purchased the product. July, 25 MultiTech Systems, Inc. SocketSLIC Developer s Guide 9