SG6931 FEATURES OVERVIEW APPLICATIONS DESCRIPTION TYPICAL APPLICATION. Product Specification. Green mode PFC/Forward PWM Controller

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1 FEATURES OVERVIEW Interleaved PFC/PWM switching Green mode PFC and PWM operation Low operating current Innovative Switching-Charge multiplier-divider Multi-vector control for improved PFC output transient response Average-current-mode for input-current shaping PFC over-voltage and under-voltage protections PFC and PWM feedback open-loop protection Cycle-by-cycle current limiting for PFC/PWM Slope compensation for PWM Programmable PWM maximum duty cycle Power on sequence control and soft-start Brownout protection APPLICATIONS Switch mode Power Suppliers with Active PFC Servo System Power Supplies PC-ATX Power Supplies DESCRIPTION The highly integrated SG69 is specially designed for power supplies consist of boost PFC and Forward PWM. SG69 It requires very few external components to achieve green-mode operation and versatile protections/compensation. It is available in 0-pin DIP and SOP packages. The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is continuously decreased to reduce power consumption. For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, SG69 will shut off to prevent extra-high voltage on output. For the Forward PWM stage, the synchronized slope compensation ensures the stability of the current loop under continuous-conduction-mode operation. Hiccup operation during output overloading is guaranteed. The soft start and programmable maximum duty cycle ensure safe operation. In addition, SG69 provides complete protection functions such as brownout protection and RI open/short protection. TYPICAL APPLICATION System General Corp Version.(IAO.004.B) Nov., 006

2 SG69 MARKING DIAGRAMS PIN CONFIGURATION SG69TP XXXXXXXXYWWV T: D = DIP, S = SOP P : Z =Lead Free ROHS Compatible XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location VRMS RI OTP IEA IPFC IMP ISENSE FBPWM IPWM AGND IAC VEA FBPFC OVP SS VDD OPFC GND OPWM M_DUTY ORDERING INFORMATION Part Number Package SG69DZ SG69SZ 0-pin PDIP (Lead Free) 0-pin SOP (Lead Free) PIN DESCRIPTIONS Name Pin No. Type Function VRMS Line-Voltage Detection Line voltage detection. The pin is used for PFC multiplier and brownout protection. RI Oscillator Setting Reference setting. One resistor connected between RI and ground determines the switching frequency. A resistor having a resistance between k ~ 47kΩ is recommended. The switching frequency is equal to [560 / RI] khz, where RI is in kω. For example, if RI is equal to 4kΩ, then the switching frequency will be 65 khz. This pin provides an over temperature protection. A constant current is output from this pin. OTP If RI is equal to 4kΩ, then the magnitude of the constant current will be 00uA. An external Over Temperature NTC thermistor must be connected from this pin to ground. The impedance of the NTC Protection thermistor decreases whenever the temperature increases. Once the voltage of the OTP pin drops below the OTP threshold, the SG69 will be shutdown. IEA 4 IPFC 5 IMP 6 Output of PFC Current This is the output of the PFC current amplifier. The signal from this pin will be compared with Amplifier an internal saw-tooth and hence determine the pulse width for PFC gate drive. Inverting Input of PFC The inverting input of the PFC current amplifier. Proper external compensation circuits will Current Amplifier result in excellent input power factor via average-current-mode control. Non-inverting Input of The non-inverting input of the PFC current amplifier and also the output of multiplier. Proper PFC Current Amplifier external compensation circuits will result in excellent input power factor via average current and Output of mode control. Multiplier System General Corp Version.(IAO.004.B) Nov., 006

3 SG69 ISENSE 7 Peak Current Limit Setting for PFC The peak current limit setting for PFC. The control input for voltage-loop feedback of PWM stage. It is internally pulled high through FBPWM 8 PWM Feedback Input a 6.5 kω resistance. Usually an external opto-coupler from secondary feedback circuit is connected to this pin. IPWM 9 PWM Current Sense The current sense input for the PWM stage. Via a current sense resistor, this pin provides the control input for peak-current-mode control and cycle-by-cycle current limiting. AGND 0 Ground The signal ground. This input is used to determine the maximum duty cycle of the PWM stage. A constant M_DUTY M_DUTY (%) =[(V MD - 0.V).9V] x 00. The maximum duty cycle is clamped to 65%. Maximum duty cycle current source 0uA (RI = 4kΩ) is output from this pin. Connecting a resistor from this pin of PWM stage to ground will generate a voltage V MD. The maximum duty cycle will be: OPWM PWM Gate Drive The totem pole output drive for PWM MOSFET. This pin is internally clamped under 8V to protect the MOSFET. GND Ground The power ground OPFC 4 PFC Gate Drive The totem pole output drive for PFC MOSFET. This pin is internally clamped under 8V to protect the MOSFET. VDD 5 Supply The power supply pin. The threshold voltages for start-up and turn-off are 4V and 0V, respectively. The operating current is lower than 0mA. SS 6 PWM Soft Start During startup, the SS pin will charge an external capacitor with a 50uA constant current source. The voltage on FBPWM will be clamped by SS during startup. In the event of a protection condition occurring and/or PWM being disabled, the SS pin will be quickly discharged. The over-voltage input of the PFC stage. The comparator will disable the PFC output driver OVPPFC 7 input for PFC over-voltage protection. PFC over-voltage if this input exceeds.5v. This pin can be connected to the FBPFC pin or it can be input connected to the PFC boost output through a divider network. This pin provides an extra FBPFC 8 Voltage Feedback The feedback input for PFC voltage loop. The inverting input of PFC error amp. This pin is Input for PFC connected to the PFC output through a divider network. Error-Amp Output for The error-amp output for PFC voltage feedback loop. A compensation network (usually a VEA 9 PFC voltage feedback capacitor) is connected between this pin and ground. A large capacitor value will result in a loop narrow bandwidth and hence improve the power factor. IAC 0 Input AC Current For normal operation, this input is used to provide current reference for the multiplier. The suggested maximum IAC is 60 ua. System General Corp Version.(IAO.004.B) Nov., 006

4 SG69 BLOCK DIAGRAM System General Corp Version.(IAO.004.B) Nov., 006

5 SG69 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DD DC Supply Voltage* 5 V I AC Input AC Current ma V High OPWM, OPFC, IAC -0. to 5 V V Low Others -0. to 7 V P D Power Dissipation At T A < 50 C 0.8 W T J Operating Junction Temperature -40 to 5 T stg Storage Temperature Range -55 to 50 Rθj-C Thermal resistance (Junction to Case) DIP 4.64 SOP 5. T L Lead Temperature (Wave soldering or IR, 0 seconds) 60 ESD ESD capability, HBM model 4.5 KV ESD capability, Machine model 50 V *All voltage values, except differential voltages, are given with respect to GND pin. *Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. /W RECOMMENDED OPERATING JUNCTOIN TEMPERATURE: -0 C~ 85 C* * For proper operation ELECTRICAL CHARACTERISTICS (V DD =5V, T A =5 C UNLESS NOTED) VDD section V DD-OP Continuously Operating Voltage 0 V I DD ST Start-Up Current V TH(ON) 0.6V 0 0 ua I DD OP Operating Current V DD = 5V; OPFC, OPWM open 6 0 ma V TH-ON Start Threshold Voltage 4 5 V V DD-min Min. Operating Voltage 9 0 V V DD-OVP VDD OVP (turn off PWM with delay) V TV DD-OVP Delay time of VDD OVP RI= 4kΩ 8 5 us Oscillator & Green-Mode Operation V RI RI Voltage V F OSC PWM frequency RI= 4kΩ KHz F OSC-MINFREQ Minimum frequency in green mode RI= 4kΩ 8 0 KHz RI RI range 47 kω RI OPEN RI SHORT RI Pin Open Protection If RI> RI open, PWM will be turned off RI Pin Short Protection If RI< RI short, PWM will be turned off 00 kω kω System General Corp Version.(IAO.004.B) Nov., 006

6 SG69 VRMS for UVP V RMS-UVP- RMS AC Voltage Under-Voltage Threshold to turn off PFC (with T UVP delay) for UVP Mode V V RMS-UVP- Recovery level on VRMS for UVP mode T UVP Under Voltage Protection Propagation Delay Time (No delay for startup) V RMS-UVP -0.7 V V RMS-UVP -0.9 V V RMS-UVP -0. V RI= 4kΩ ms V PFC stage Voltage Error Amplifier V REF Reference Voltage V Av -PFC Open-loop Gain 60 db Z o Output Impedance 0 kω OVP FBPFC PFC Over-voltage-protection on OVP..5. V OVP FBPFC PFC Feedback Voltage Protection Hysteresis mv V FBPFC-H Clamp-High Feedback Voltage..5. V G FBPFC-H Clamp-High Gain 0.5 ma/ V V FBPFC-L Clamp-Low Feedback Voltage V G FBPFC-L Clamp-Low Gain 6.5 ua/mv I FBPFC-L. Maximum Source Current.5 ma I FBPFC-H. Maximum Sink Current 70 0 ua UVP VFB PFC Feedback Under Voltage Protection V V FBHIGH Output High Voltage on V EA V V RD-FBPFC Voltage level on FBPFC to enable OPWM during startup V T UVP-PFC Debouce time of PFC UVP us Current Error Amplifier V OFFSET Input Offset Voltage ((-) > ()) 8 mv A I Open-loop Gain 60 db BW Unit Gain Bandwidth.5 MHz CMRR Common-mode Rejection Ratio V CM = 0 ~.5V 70 db V OUT-HIGH Output High Voltage. V V OUT-LOW Output Low Voltage 0. V I MR, I MR Reference Current source RI=4 kω (I MR =0I RI *0.8) ua I L Maximum Source Current ma I H Maximum Sink Current 0.5 ma Peak Current Limit I P Constant Current Output RI = 4kΩ ua V pk Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (V sense < V pk ) VRMS=.05V V VRMS=V V System General Corp Version.(IAO.004.B) Nov., 006

7 SG69 T PD-PFC Propagation Delay 00 ns T BNK-PFC Leading-Edge Blanking Time ns Multiplier I AC Input AC Current Multiplier linear range 0 60 ua I MO max Maximum Multiplier Current Output; RI=4 kω 0 ua I MO- I MO Multiplier Current Output (low-line, high-power) Multiplier Current Output (high-line, high-power) V RMS =.05V; I AC =90uA; VEA=7.5V;RI=4 kω V RMS =V; I AC =64uA; V EA =7.5V;RI=4 kω ua UA V IMP Voltage of IMP Open V PFC Output Driver V Z-PFC Output Voltage Maximum (clamp) V DD =0V 6 8 V V OL-PFC Output Voltage Low V DD =5V; I O = 00mA.5 V V OH-PFC Output Voltage High V DD =V; I O = 00mA 8 V T R-PFC Rising Time V DD =5V; C L =5nF O/P= V to 9V ns T f-pfc Falling Time V DD =5V; C L =5nF O/P= 9V to V ns DC (MAX) Maximum Duty Cycle 9 97 % System General Corp Version.(IAO.004.B) Nov., 006

8 SG69 PWM Stage FBPWM A v-pwm FB to Current Comparator Attenuation..7. V/V Z FB Input Impedance kω FB OPEN-LOOP PWM Open Loop Protection voltage V T OPEN-PWM-Hiccup The interval of PWM Open Loop Protection RI = 4kΩ ms Reset T OPEN-PWM PWM Open Loop Protection Delay Time RI = 4kΩ ms V N Frequency Reduction Threshold on FBPWM.9.. V S G Green-Mode Modulation Slope Hz/mV V G Voltage on FBPWM for minimum Green-mode frequency V PWM-Current Sense T PD-PWM Propagation Delay to Output V LIMIT Loop VDD=5V, OPWM drops to 9V 60 0 ns V LIMIT Peak Current Limit Threshold Voltage V T BNK-PWM Leading-Edge Blanking Time ns V SLOPE Slope Compensation V s = V SLOPE x (T on /T) V s : Compensation Voltage Added to Current Sense V PWM Output Driver V Z-PWM Output Voltage Maximum (clamp) V DD =0V 6 8 V T PWM The interval of OPWM Lags behind OPFC at Startup RI=4 kω 4 6 ms V OL-PWM Output Voltage Low V DD =5V; I O = 00mA.5 V V OH-PWM Output Voltage High V DD =V; I O = 00mA 8 V T R-PWM Rising Time V DD =5V; C L =5nF; O/P= V to 9V ns T F-PWM Falling Time V DD =5V; C L =5nF; O/P= 9V to V ns Maximum Duty-Cycle DC MAX Maximum Duty Cycle for M_Duty open 6 66 % I MD Constant Current Output RI= 4kΩ ua DC RD=.8kΩ Maximum Duty Cycle for M_Duty =.8kΩ M_Duty =.8kΩ, RI= 4kΩ % OTP section I OTP OTP Pin Output Current RI = 4kΩ ua V OTP-OFF OTP Threshold Voltage.5..5 V V OTP-ON Recovery level on OTP V T OTP OTP Debounce Time RI = 4kΩ 8 5 us System General Corp Version.(IAO.004.B) Nov., 006

9 SG69 Soft Start I SS Constant Current Output for Soft Start RT= 4kΩ ua R D Discharge Resistance 470 Ω System General Corp Version.(IAO.004.B) Nov., 006

10 SG69 TYPICAL CHARACTERISTICS Start-Up Current (IDD ST) vs Temperature Min. Operation Voltge (VDD-MIN) vs Temperature IDD ST (ua) VTH-MIN(V) Start Threshold Voltage (VTH-ON) vs Temperature Frequency vs. FB Voltage VTH-ON(V) Frequency (KHz) FB Voltage (V) Start-up Current vs. VDD Voltage Duty Cycle vs. FB Voltage Start-up Current (ua) VDD Voltage (V) Duty Cycle (%) FB Voltage (V) System General Corp Version.(IAO.004.B) Nov., 006

11 SG69 VDD OVP Threshold (VDD-OVP) vs Temperature PFC over Voltage Protection (OVPPFC) vs Temperature VDD-OVP (V) OVPPFC (V) PWM Frequency (FOSC) vs Temperature Rising Time (TR) vs Temperature FOSC (KHz) TR(nS) PWM Frequency (FOSC-GREEN) vs Temperature Falling Time (TF) vs Temperature FOSC-MINFREQ (KHz) TF (ns) Reference Voltage (VREF) vs Temperature Maximum Duty Cycle (DCMAX) vs Temperature VREF (V) DCMAX (%) System General Corp Version.(IAO.004.B) Nov., 006

12 SG69 PWM Open Loop Protection voltage (FBOPEN-LOOP) vs Temperature Fall Time (TF-PWM) vs Temperature FBOPEN-LOOP (V) TF-PWM (ns) PWM Open Loop Protection Delay Time (TOPEN-PWM) vs Temperature Maximum Duty Cycle for M_DUTY open (DCMAX) vs Temperature TOPEN-PWM (ms) DCMAX (%) Peak Current Limit Threshold Voltge (VLIMIT) vs Temperature OTP Threshold Voltage (VOTP-OFF) vs Temperature VLIMIT (V) VOTP-OFF (V) Rising Time (TR-PWM) vs Temperature Constant Current Output for Soft Start (ISS) vs Temperature TR-PWM (ns) ISS (ua) System General Corp Version.(IAO.004.B) Nov., 006

13 SG69 Constant Current Output (IMD) vs Temperature IMD (ua) System General Corp Version.(IAO.004.B) Nov., 006

14 SG69 OPERATION DESCRIPTION The highly integrated SG69 is specially designed for power supply with boost PFC and forward PWM. It requires very few external components to achieve green-mode operation and versatile protections/ compensation. The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is linearly decreased to reduce power consumption. The PFC function is implemented by average-current-mode control. The patented Switching-Charge multiplier-divider provides high-degree noise immunity for the PFC circuit. This also enables the PFC circuit to operate over a much wider region. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG69 will shut off PFC to prevent extra-high voltage on output. For the forward PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-mode operation. Hiccup operation during output overloading is also guaranteed. To prevent the power supply from drawing large current during start-up, the start-up for PWM stage will be delayed 4ms after the PFC output voltage reaches its setting value. In addition, SG69 provides complete protection functions such as brownout protection and over voltage and RI open/short protection. Figure Input Voltage Detection Switching Frequency and Current Sources The switching frequency of SG69 can be programmed by the resistor R I connected between RI pin and GND. The relationship is: f PWM 560 = (khz) () RI (kω) For example, a 4kΩ resistor R I results in a 65 khz switching frequency. Accordingly, constant Current I T will flow through R I. I T.V = (ma) () RI (kω) I T is used to generate internal current reference. I AC signal Figure shows that the IAC pin is connected to input voltage by a resistance. And the current I AC will be the input for PFC multiplier. For the linear range of I AC is 0~60uA, the wide range input voltage should be connected a resistance over.m. Line Voltage Detection (V RMS ) Figure shows a resistive divider with low-pass filtering for line-voltage detection on VRMS pin. The V RMS voltage is used for the PFC multiplier and brownout protection. For brownout protection, when the VRMS voltage drops below 0.8V, OPFC will be turn off. System General Corp Version.(IAO.004.B) Nov., 006

15 SG69 achieved with good noise immunity and transient response. Figure 4 shows the total control loop for the average-current-mode control circuit of SG69. Figure Line-voltage Detection on VRMS pin Interleaved Switching and Green mode Operation The SG69 uses interleaved switching to synchronize the PFC and PWM stages. This reduces switching noise and spreads the EMI emissions. Figure shows that an off-time T OFF is inserted in between the turn-off of the PFC gate drives and the turn-on of the PWM. The off-time T OFF is increased in response to the decreasing of the voltage level of FBPWM. Therefore, the PWM switching frequency is linearly decreased to reduce switching losses. OPFC OPWM TOFF Figure Interleaved Switching Figure 4 Control Loop of PFC Stage The current source output from the Switching Charge multiplier/divider can be expressed as: I MO I AC VEA = K (ua) (4) VRMS I MP, the current output from IMP pin, is the summation of I MO and I MR. I MR and I MR are identical fixed current sources. R and R are also identical. They are used to pull high the operating point of the IMP and IPFC pins since the voltage across R S goes negative with respect to ground. Through the differential amplification of the signal across Rs, better noise immunity is achieved. The output of IEA will be compared with an internal sawtooth and hence the pulse width for PFC is determined. Through the average current-mode control loop, the input current Is will be proportional to I MO. I MO R = IS RS (5) PFC Operation The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase will follow that of the input voltage. Using SG69, average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and Switching Charge multiplier/divider for current reference, excellent input power factor is According to equation (5), the minimum value of R and maximum of Rs can be determined since I MO should not exceed the specified maximum value. There are different concerns in determining the value of the sense resistor Rs. The value of Rs should be small to reduce power consumption, but it should be large enough to maintain the resolution. A current transformer (CT) may be used to improve the efficiency of high power converters. System General Corp Version.(IAO.004.B) Nov., 006

16 To achieve good power factor, the voltage for V RMS and V EA should be kept as DC as possible according to equation (4). In other words, good RC filtering for V RMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. The trans-conductance error amplifier has output impedance R O ( >90kΩ) and a capacitor C EA (uf ~ 0uF) connected to ground (Figure. 5). This establishes a dominant pole f for the voltage loop: SG69 SG69 will shut off immediately to prevent extra-high voltage on the output capacitor..5v.85v - SG69XX f = (6) 0 EA π R C RA RB FBPFC V - K IACxVEA VRMS The average total input power can be expressed as: VEA Pin = Vin( rms) Iin( rms) V V V RMS RMS RMS I I MO V AC EA VRMS Vin V R EA AC VRMS V EA (7) From equation (7), V EA, the output of the voltage error amplifier, actually controls the total input power and hence the power delivered to the load. Multi-vector Error Amplifier The voltage-loop error amplifier of SG69 is trans-conductance, which has high output impedance (> 90kΩ). A capacitor C EA (uf ~ 0uF) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative Multi-Vector Error Amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. Figure 5 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds ± 5% of the reference voltage, the trans-conductance error amplifier will adjust its output impedance to increase the loop response. If R A is opened, Figure 5 Multi-vector Error Amp. Cycle-by-cycle Current Limiting SG69 provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 6 shows the peak current limit for the PFC stage. The PFC gate drive will be terminated once the voltage on ISENSE pin goes below V PK. The voltage of V RMS determines the voltage of V PK. The relationship between V PK and VRMS is also shown in Figure 7. The amplitude of the constant current I P is determined by the internal current reference I T, according to the following equation:.v Ip = I = (8) T R I Therefore the peak current of the I S is given by (V RMS <.05V) (Ip R ) - 0.V P S_peak = (9) S I CEA R System General Corp Version.(IAO.004.B) Nov., 006

17 SG69 positively sloped ramp is represented by the voltage signal V s-comp. In this example, the voltage of the ramp signal is 0.55V. FBPWM 0.55V Figure 6 Current Limit IPWM Power On Sequence & Soft Start SG69XX 0.7V The SG69 is enabled whenever the line voltage is higher than the brownout threshold. Once the SG69 is active, the PFC stage is enabled first. The PWM stage is enabled following a 4mS delay time after FBPFC voltage exceeds.7v. During startup of PWM stage, the SS pin will charge an external capacitor with a constant current source. The voltage on FBPWM will be clamped by SS during startup. In the event of a protection condition occurring and/or PWM being disabled, the SS pin will be quickly discharged. FBPFC V.7V Figure 8 Slope Compensation Maximum Duty Cycle of PWM stage An internal constant current, I MD, is sourced from this pin. Connecting a resistor from this pin to ground will generate a voltage V MD and determine the maximum duty cycle. It is given by, VMD 0.V M _ DUTY (%) = 00.9V In this example, a.8kω resistor is connected to the M_DUTY pin. I MD =50uA when RI=4 kω. This will result in a 48% maximum duty cycle for the PWM stage. The maximum duty cycle of the SG69 is 66%. A nf capacitor paralleled with the.8kω resistor to improve the stability is needed. OPFC Limited Power Control OPWM 4mS Figure 7 Power on Sequence Every time when the output of power supply is shorted or over loaded, the FBPWM voltage will increase. If the FB voltage is higher than a designed threshold, 4.V, for longer than 95msec, the PWM output will then be turned off. Forward PWM and Slope Compensation The PWM stage is designed for forward power converters. Peak current mode control is used to optimize system performance. Slope compensation is added to stabilize the current loop. The SG69 inserts a synchronized positively sloped ramp at each switching cycle. The Gate Drivers SG69 output stages are fast totem-pole gate drivers. The output driver is clamped by an internal 8V Zener diode in order to protect the power MOSFET. System General Corp Version.(IAO.004.B) Nov., 006

18 Protections The SG69 provides full protection functions to prevent the power supply and the load from being damaged. The protection features include: PFC Feedback Over-voltage Protection. When the PFC feedback voltage exceeds the over-voltage threshold, the SG69 will inhibit the PFC switching signal. This protection also prevents the PFC power converter from operating abnormally while the FBPFC pin is open. Second PFC Over Voltage Protection (OVP_PFC). The PFC stage over-voltage input. The comparator will disable the PFC output driver if this input exceeds.5v. This pin can be connected to the FBPFC pin, or it can be connected to the PFC boost output through a divider network. This pin provides an extra input for PFC over voltage protection. SG69 PCB layout. The ground trace is connected from the ground pin of SG69 to the decoupling capacitor, which should be low impedance and as short as possible. The ground trace provides a signal ground. It should be connected directly to the decoupling capacitor C DD and/or to the ground pin of the SG69. The ground trace is independently tied from the decoupling capacitor to the PFC output capacitor C O. The ground in the output capacitor C O is the major ground reference for power switching. In order to provide a good ground reference and reduce the switching noise of both the PFC and PWM stages, the ground traces 6 and 7 should be located very near and be low impedance. The IPFC pin is connected directly to R S through R to improve noise immunity (Beware that it may incorrectly be connected to the ground trace ). The IMP and ISENSE pins should also be connected directly via the resistors R and R P to another terminal of R S. PFC Feedback Under Voltage Protection. The SG69 will stop the PFC switching signal whenever the PFC feedback voltage drops below the under-voltage threshold. This protection feature is designed to prevent the PFC power converter from experiencing abnormal conditions while the FBPFC pin is shorted to ground. VDD Over-voltage Protection. The PFC and PWM stages will be disabled whenever the V DD voltage exceeds the over-voltage threshold. RI pin Open / Short Protection. The RI pin is used to set the switching frequency and internal current reference. The PFC and PWM stages of SG69 will be disabled whenever the RI pin is short or open. Figure 9 PCB Layout PCB Layout Note that SG69 has two ground pins. Good high-frequency or RF layout practices should be followed. Avoid long PCB traces and component leads. Locate decoupling capacitors near the SG69. A resistor (5 ~ 0 Ω ) is recommended connecting in series from the OPFC and OPWM to the gate of the MOSFET. Isolating the interference between the PFC and PWM stages is also important. Figure 9 shows an example of the System General Corp Version.(IAO.004.B) Nov., 006

19 SG69 System General Corp Version.(IAO.004.B) Nov., 006 Reference Circuit A B C D D C B A F FUSE C C/uF/X R R/0K/W 4 L TRANS C C/47/Y C C/47/Y TR NTC/47/A 4 BD BD/8A/600V C4 C/uF/400V L L R R/0K R R/.K R R/.K R4 R/0.OHM/W R6 R/499K Q IRFP460A R R/0K D D/R860P R9 R/0K R50 R/6.K C C/055Z/50V C4 C/47P/50V C5 C/0uF/50V R5 R/499K R7 R/750K R56 R/K C5 C/0uF/450V C7 C/0uF/50V D9 D/FR0 C6 C/0uF/50V TX EEL TX ER5 Q MOS D4 D/UF07 R4 R/0K HHV R57 R/0.OHM/W OPWM Q SK8 R68 R/0 R69 R/47K//4W R7 R/ R55 R/470 C C/P/KV D8 D/UF07 R8 R/0 HHV 4 U6 PO-87 4 U7 PO-87 R6 R/K R7 R/0K R0 R/0K R R/0K R70 R/ D0 D/SB540 C4 C/000uF/0V C5 C/000uF/0V L9 A K R U0 TL4 C40 C/04P/50V 5VSB ZD ZD/5.6V PGI GND /FPO /PSON 4 IS 5 RI 6 VSB 7 IS5 8 IS 9 VS 0 VS VS5 VDD PGO 4 U4 SG655 PG 5V.V VA VS VS5 R7 R/ R4 R/ UVAC R46 R/0K R45 R/0 PSONVS D6 STPP00 R R/NC R R/NC D5 D/MBR045 R R/NC R0 R/NC D D/MBR040 R7 R/NC R5 R/NC R4 R/NC D D/BYV750 D D/BYV750 R6 R/NC L L- R8 R/00 C5 C/000uF/6V L4 L- R48 R/00/W C6 C/00uF/0V C7 C/00uF/0V L5 L- R58 R/0 C9 C/470uF/5V D9 D/FR55 C0 C/47uF/5V C8 C/00uF/6.V R60 R/K L6 L- L7 L- D0 D/FR55 Q6 Q/BD40 R75 R/ R6 R/K R6 R/0K R76 R/ R78 R/4.K R79 R/5K C9 C/00uF/6.V L8 L- A K R U9 TL4 4 U5 PO-87 R7 R/K R5 R/0K R74 R/.K R84 R/.9K R85 R/9.09K A K R U8 TL4 5V VS.V -5V -V 5V VS R5 R/470 R49 R/00K C C/NC C C/NC C8 C/NC C7 C/NC C0 C/NC C9 C/NC C C/NC C4 C/NC.VSENSE R77 R/0/W C7 C/04P/50V C6 C/04P/50V L N MOV R8 R/750K VS VS5 C8 C/00uF/6V R9 R/68K C6 C/0P/KV R5 R/0 GATE VDD NC SENSE 4 RI 5 NC 6 FB 7 GND 8 U SG6848 D7 D/N448 C4 C/47uF/50V C4 C/0uF/50V R66 R/M R67 R/M 5VSB C0 C/47P/50V R4 R/ D D/N4007 D D/N4007 R64 R/K C9 C/47P/50V C C/47P/50V VDD R R/M R R/M R9 R/ R0 R/ VA VB R8 R/0 R40 R/0 R9 R/0 VB R47 R/ R44 R/K Q4 NPN Q5 N R4 R/ R5 R/ PSON R7 R/4.7K R R/0 C8 C/47/Y R54 R/470 R5 R/0K R80 R/00 C C/47P/50V R6 R/0 C C/0P/50V C C/04P/50V Gnd Vin Vout U 7905 D7 D/FR55 D8 D/FR55 R65 R//W VR VR C4 C/47P/50V R86 R/47 R87 R/5.5K//8W R88 R/.K//8W C44 C/47/50V UVAC N N N N4 N5 N6 N7 N8 N9 N0 N N N N4 N5 N6 N7 N8 N9 N0 N N N N4 N5 N6 N7 N8 N0 N N N N4 N5 N6 N7 N8 N9 N40 N4 N4 N44 N45 N46 N47 N48 N49 N50 N5 N5 N5 N54 N55 N56 N57 N58 N59 N60 N6 N6 N6 N64 N65 N66 N69 N70 N7 N7 N7 N74 N75 N76 N77 N78 N79 N80 N8 N8 N8 N84 N85 N86 N87 N88 N89 N90 N9 N9 N94 N97 N98 N99 N9 CN CON_ D D/N448 D D/N448 N00 R89 R/ VRMS IEA 4 FBPFC 8 RT VEA 9 IPFC 5 IMP 6 GND OPWM FBPWM 8 IPWM 9 SS 6 VDD 5 OPFC 4 ISENSE 7 IAC 0 A_GND 0 OTP M_DUTY OVPPFC 7 U SG69 R90 R\ RA R\ N9 N67 N68 VDD Q7 Q/907 R6 R/K VDD R8 R/0K R8 R/0 N67 N68 NTC NTC

20 SG69 PACKAGE INFORMATION 0 PINS PLASTIC DIP (D) D 0 θ E E eb 0 L e A A b b A Dimension: Symbol Millimeter Inch Min. Typ. Max. Min. Typ. Max. A A A b b D E E e L e B θ System General Corp Version.(IAO.004.B) Nov., 006

21 SG69 0 PINS PLASTIC SOP (S) E H Detail A 0 b e F c D A θ y A A L Detail A Dimension: Symbol Millimeter Inch Min. Typ. Max. Min. Typ. Max. A A A b c D E e H L F 0.508X X45 y θ System General Corp Version.(IAO.004.B) Nov., 006

22 SG69 DISCLAIMERS LIFE SUPPORT System General s products are not designed to be used as components in devices intended to support or sustain human life. Use of System General s products in components intended for surgical implant into the body, or other applications in which failure of the System General s products could create a situation where personal death or injury may occur, is not authorized without the express written approval of System General s Chief Executive Officer. System General will not be held liable for any damages or claims resulting from the use of its products in medical applications. MILITARY System General's products are not designed for use in military applications. Use of System General s products in military applications is not authorized without the express written approval of System General s Chief Executive Officer. System General will not be held liable for any damages or claims resulting from the use of its products in military applications. RIGHT TO MAKE CHANGES System General reserves the right to change this document and/or this product without notice. Customers are advised to consult their System General sales representative before ordering. System General Corp Version.(IAO.004.B) Nov., 006