PAC1932/3/4. Multi-Channel DC Power/Energy Monitor with Accumulator. Features. Applications. Computing Platform Support.

Transcription

1 Multi-Channel DC Power/Energy Monitor with Accumulator Features High-Side Current Monitor with 2, 3 or 4 Channels mv full scale range for current sense voltage,16 bit resolution - Selectable bidirectional current sense capability, -100 mv to +100 mv range, 16 bit two s complement (signed) data format - External sense resistor sets full scale current range - Very low input current simplifies routing Wide Bus Voltage Range for Voltage Monitor - 0V to 32V input common-mode voltage - 16 bit resolution for voltage measurements, 14 bits are used for power calculations Real Time Auto-Calibration of Offset and Gain Errors for Voltage and Current, No User Adjustment Required 1% Power Measurement Accuracy over a Wide Dynamic Range On-Chip Accumulation of 28-bit Power Results for Energy Measurement - 48-bit power accumulator register for recording accumulated power data - 24 bit Accumulator Count - User programmable sampling rates of 8, 64, 256 and 1024 samples per second - 17 minutes of power data accumulation minimum at 1024 S/s - Over 36 hours of power data accumulation minimum at 8 S/s 2.7V to 5.5V Supply Operation - Separate V DD I/O pin for digital I/O V capable SMBus and digital I/O - SMBus 3.0 and I 2 C Fast Mode Plus (1Mb/S) SMBus Address 16 Options, set with Resistor No Input Filters Required ALERT Features that can be Enabled: - ALERT on accumulator overflow - ALERT on Conversion Complete 4x4x0.5 mm UQFN Package 2.225x2.17 mm WLCSP Package - WLCSP available for PAC1934 only - Contact Marketing for other options Applications Embedded Computing Networking FPGA Systems Automotive Low voltage/high Power AI, GPU Industrial Linux Applications Notebook and Tablet Computing Cloud, Linux and Server Computing Computing Platform Support Windows 10 Driver Linux Driver Python Script Description The PAC1932/3/4 are two, three and four-channel power and energy monitoring devices. A high-voltage multiplexer sequentially connects the inputs to a bus voltage monitor and current sense amplifier that feed high-resolution ADCs. Digital circuitry performs power calculations and energy accumulation. This enables energy monitoring with integration periods from 1 ms up to 36 hours or longer. Bus voltage, sense resistor voltage and accumulated proportional power are stored in registers for retrieval by the system master or Embedded Controller. The sampling rate and energy integration period can be controlled over SMBus or I 2 C. Active channel selection, one-shot measurements and other controls are also configurable by SMBus or I 2 C. The PAC1932/3/4 device family uses real time calibration to minimize offset and gain errors. No input filters are required for this device Microchip Technology Inc. DS C-page 1

2 Package Types PAC1932/3/4 Top View 4x4x 0.5 mm UQFN* PAC1934 Top View 2.225x2.17 mm WLCSP PWRDN VDD I/O SENSE2- SENSE2+ A SENSE2+ SENSE1- SENSE1+ V DD SLOW/ALERT V DD GND Exposed pad SENSE1- SENSE1+ SENSE4+ B SENSE2- V DD I/O PWRDN GND SM_CLK 4 9 SENSE4- C SENSE3- ADDRSEL SLOW/ALERT SM_CLK SM_DATA ADDRSEL SENSE3- SENSE3+ D SENSE3+ SENSE4- SENSE4+ SM_DATA *Includes Exposed Thermal Pad; see Table 3-1. Device Block Diagram VDD GND SENSE 1+ VBUS1 SENSE 1- SENSE 2+ SENSE 2- SENSE 3+ SENSE 3- SENSE 4+ SENSE 4- VBUS2 Sense1+ Sense1- Sense2+ Sense2- VBUS3 Sense3+ Sense3- VBUS4 Sense4+ Sense4- Differential VSENS E Amplifier VBUS Buffer/ Divider 16-bit ADC 16-bit ADC ADC/MUX Clocking & Control Calculation and Calibration Accumlator VBUS Registers VSENS E Registers VPOWE R Registers Accumulator Registers Control Registers I 2 C/SMBus VDD I/O SM_CLK SM_DATA SLOW/ALERT PWRDN High Voltage MUX Resistor Decoder ADDRSEL Note: For PAC1932, channels 3 and 4 are inactive. For PAC1933, channel 4 is inactive. DS C-page Microchip Technology Inc.

3 1.0 ELECTRICAL CHARACTERISTICS 1.1 Electrical Specifications Absolute Maximum Ratings ( ) V DD pin to 6.0V Voltage on SENSE- and SENSE+ pins to 40V Voltage on any other pin to GND...GND -0.3 to +6.0V Voltage between Sense pins ( (SENSE+ SENSE-) ) mv Input current to any pin except V DD...±100 ma Output short-circuit current... Continuous Junction to Ambient ( J-A ) C/W Operating Ambient Temperature Range to +150 C Storage Temperature Range to +150 C ESD Rating all pins HBM V ESD Rating all pins CDM V Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. ESD Protection Diagram (Floating ESD rail) SLOW/ SM_DATA SM_CLK PWRDN ALERT ADDRSEL VDD I/O VDD GND CLAMP CIRCUIT SENSE1+ SENSE2+ SENSE3+ SENSE4+ SENSE1- SENSE2- SENSE3- SENSE4- (~40v breakdown) This diagram represents the ESD protection circuitry on the PAC1934. The SENSE pins are allowed to be at 32V if V DD is at zero. The back-to-back diodes between the Sense+ and Sense- pins have 1 kω resistors in series with them. For PAC1932 and PAC1933, some of the SENSE pins are not electrically connected inside. These unconnected pins should be grounded Microchip Technology Inc. DS C-page 3

4 TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: Unless otherwise specified, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V DD I/O = 1.62V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C V DD = V DD I/O = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE-) = 0V Characteristic Symbol Min. Typ. Max. Unit Conditions Power Supply V DD Range V DD V V DD I/O Range V DD I/O V V DD Pin Active Current I DD µa 1024 Samples/s All IDD specifications are the same for PAC1932/3/4 V DD Pin Active I DD SLOW 16 µa 4 channels enabled, 8 Samples/s Current Minimum V DD Rise V DD_RISE_MIN 0.05 V/ms 0 to 5V in 100 ms Rate Maximum V DD Rise V DD_RISE 1000 V/ms 0 to 5V in 5 µs Rate V DD Sleep Current I DD_SLEEP 5 µa Sleep State V DD Power-Down I DD_PWRDN 0.1 µa Power-Down State Current V DD I/O Current I DD I/O 2 µa All States Analog Input Characteristics V BUS Voltage Range V BUS 0.2V 32 V Common mode range for SENSE+ and SENSE- pins, referenced to ground (negative range not tested in production) V SENSE Differential Input Voltage Range V SENSE_DIF mv SENSE+, SENSE- Pin Input Current SENSE+, SENSE- Pin Input current V SENSE Measurement Accuracy V SENSE Gain V SENSE_ Accuracy GAIN_ERR V SENSE Offset V BUS_ Accuracy, referenced OFFSET_ERR to input V SENSE Unidirectional Currents V SENSE ADC Resolution V SENSE Full Scale Range V SENSE LSB Step Size I SENSE +, I SENSE µa V SENSE + = V SENSE - = 32V (Input current is the combined current for the two pins) I SENSE +, I SENSE µa V SENSE + = 6V, V SENSE - = 5.9V ±0.2 ±1 ±0.02 ±0.2 ±0.9 % % ±0.1 mv mv At +25 C typical, -40 to +85 C At +25C typical, -40 to +85 C V SENSE_RES 16 Bits Straight Binary for unidirectional currents V SENSE_FSR mv Unidirectional currents V SENSE_LSB 1.5 µv Unidirectional currents V SENSE Bidirectional Currents V SENSE V SENSE_RES 16 bits 16-bit two s complement (signed) ADC Resolution V SENSE Full Scale Range V SENSE_FSR mv Bidirectional currents DS C-page Microchip Technology Inc.

5 TABLE 1-1: DC CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V DD I/O = 1.62V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C V DD = V DD I/O = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE-) = 0V Characteristic Symbol Min. Typ. Max. Unit Conditions V SENSE LSB Step Size V SENSE_LSB 3 µv Bidirectional currents V BUS Measurement Accuracy V BUS Gain Accuracy V BUS_GAIN_ERR ±0.02 ±0.2 V BUS Offset Accuracy, referenced to input V BUS Unipolar Voltages V BUS ADC Resolution V BUS Unipolar Full-Scale Range V BUS_ OFFSET_ERR ±1 ±2 ±0.5 % % LSB LSB At +25 C typical, -40 to +85 C At +25 C typical, -40 to +85 C V BUS_RES 16 bits Straight Binary for unidirectional currents V BUS_ FSR 0 32 V Unipolar voltage V BUS LSB Step Size V BUS_ LSB 488 µv FSR = 32V, 16-bit resolution V BUS Bipolar Voltages V BUS ADC Resolution V BUS_RES 16 bits 16-bit two's complement (signed) numbers are reported for V BUS measurement result V BUS Bipolar Full-Scale Range V BUS_ FSR V Mathematical scaling. Physics limits the negative input voltage to -0.2V V BUS LSB Step Size V BUS_ LSB 976 µv Bipolar voltages Microchip Technology Inc. DS C-page 5

6 TABLE 1-1: DC CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V DD I/O = 1.62V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C V DD = V DD I/O = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE-) = 0V Characteristic Symbol Min. Typ. Max. Unit Conditions Power Accumulator Accuracy Accumulator Error ACC_Err 0.2 % V SENSE = 97 mv Accumulator Error ACC_Err 0.2 % V SENSE = 10 mv Accumulator Error ACC_Err 1 % V SENSE = 1 mv Accumulator Error ACC_Err 3 % V SENSE = 100 µv Accumulator Error ACC_Err 5 % V SENSE = 50 µv Active Mode Timing Pull-Up Voltage Range Time to First Communications Transition From Sleep State to Start of Conversion Cycle V PULLUP V Pull-up voltage for I 2 C/SMBus pins and digital I/O pins. Set by V DD I/O. t INT_T ms t SLEEP_TO_ACTIVE 3 ms Digital I/O Pins (SM_CLK, SM_DATA, SLOW/ALERT, PWRDN) Input High Voltage V IH V DD I/O V x 0.7 Input Low Voltage V IL V DD I/O V x 0.3 Output Low Voltage V OL 0.4 V Sinking 8 ma for the ALERT pin and 20 ma for the SMCLK pin Leakage Current I LEAK 1 +1 µa DS C-page Microchip Technology Inc.

7 TABLE 1-2: SMBUS MODULE SPECIFICATIONS Electrical Characteristics: Unless otherwise specified, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; Typical values are at T A = +25 C, V DD = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE-) = 0V, V DD I/O = 1.62V to 5.5V Characteristic Sym. Min. Typ. Max. Units Conditions SMBus Interface Input Capacitance C IN 4 10 pf Not tested in production SMBus Timing Clock Frequency f SMB MHz No minimum if Time-Out is not enabled. Spike Suppression t SP 0 50 ns Bus Free Time Stop to t BUF 0.5 µs Per SMBus 3.0 Start Hold Time after Repeated Start Condition t HD:STA 0.26 µs Per SMBus 3.0 Repeated Start t SU:STA 0.26 µs Per SMBus 3.0 Condition Setup Time Setup Time: Stop t SU:STO 0.26 µs Per SMBus 3.0 Setup Time: Start t SU:STA 0.26 µs Data Hold Time t HD:DAT 0 µs Data Setup Time t SU:DAT 50 ns Per SMBus 3.0 (Note) Clock Low Period t LOW 0.5 µs Per SMBus 3.0 Clock High Period t HIGH µs Clock/Data Fall Time t FALL 120 ns Not tested in production Clock/Data Rise Time t RISE 120 ns Not tested in production Capacitive Load C LOAD 550 pf Per bus line, C LOAD not tested in production SLOW Pin Pulse Width SLOWpw 100 µs Pulses narrower than 100 µs may not be detected Note: A device must internally provide a hold time of at least 300 ns for the SM_DATA signal (with respect to the V IH(min) of the SM_CLK signal) to bridge the undefined region of the falling edge of SM_CLK. T LOW T HIGH T HD:STA T SU:STO SMCLK T RISE T FALL T T HD:DAT HD:STA T SU:DA T T SU:STA SMDATA T BUF P S S - Start Condition S P - Stop Condition P FIGURE 1-1: SMBus Timing Microchip Technology Inc. DS C-page 7

8 NOTES: DS C-page Microchip Technology Inc.

9 2.0 TYPICAL OPERATING CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C, V DD = 3.3V, V BUS = 3.3V, V SENSE = (SENSE+ SENSE-) = 0V, V DD I/O = 1.62 to 5.5V. Error (percent) vDC 25 o C 10uV 100uV 1mV 10mV 100mV Sense Input Voltage Error (percent) vDC -40 o C vDC 0 o C vDC 25 o C vDC 85 o C 5 3.3vDC 125 o C uV 10uV 0.1mV 1mV 10mV 100mV Sense Input Voltage FIGURE 2-1: Input Voltage. V SENSE Error vs. V SENSE FIGURE 2-4: V SENSE Error vs. V SENSE Input Voltage and Temperature % CM3.3v 3.3vDC 25 o C 0.025% CM3.3v 3.3vDC 25 o C Error (%FullScale) % % Error (%FullScale) % % % Sense Input Voltage (mv) % -1mV -0.5mV 0 0.5mV 1mV Sense Input Voltage FIGURE 2-2: V SENSE Error vs. V SENSE Input Voltage Bidirectional Mode. FIGURE 2-5: V SENSE Error vs. V SENSE Input Voltage Bidirectional Mode (Zoom View). 0.05% 0.05% Error (%FullScale) % -0.1% Ch1 3.3vDC -40 o C Ch1 3.3vDC 0 o C Ch1 3.3vDC 25 o C Ch1 3.3vDC 85 o C -0.15% Ch1 3.3vDC 125 o C 0 20mV 40mV 60mV 80mV 100mV Sense Input Voltage Error (%FullScale) 0.025% % CM1v 3.3vDC 25 o C CM3v 3.3vDC 25 o C CM5v 3.3vDC 25 o C CM16v 3.3vDC 25 o C CM32v 3.3vDC 25 o C -0.05% 0 20mV 40mV 60mV 80mV 100mV Sense Input Voltage FIGURE 2-3: V SENSE Error vs. V SENSE Input Voltage vs. Temperature. FIGURE 2-6: V SENSE Error vs. V SENSE and Common Mode Microchip Technology Inc. DS C-page 9

10 Note: Unless otherwise indicated, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C, V DD = 3.3V, V BUS = 3.3V, V SENSE = (SENSE+ SENSE-) = 0V, V DD I/O = 1.62 to 5.5V. Error (percent) vDC 25 o C Error (percent) vDC -40 o C 3.3vDC 0 o C 3.3vDC 25 o C 3.3vDC 85 o C 3.3vDC 125 o C 1mV 10mV 0.1V 1V 10V Input Voltage 0 1mV 10mV 0.1V 1V 10V Input Voltage FIGURE 2-7: Voltage. V BUS Error vs. V BUS Input FIGURE 2-10: V BUS Error vs. V BUS Input Voltage vs. Temperature. 2% 3.3vDC 25 o C 2% Error (percent) 1% 0-1% -2% 10mV 100mV 1V 10V Input Voltage FIGURE 2-8: V BUS Error vs. V BUS Input Voltage (Zoom View). Error (percent) 1% 0 3.3vDC -40 o C 3.3vDC 0 o C -1% 3.3vDC 25 o C 3.3vDC 85 o C 3.3vDC 125 o C -2% 10mV 100mV 1V 10V 32V Input Voltage FIGURE 2-11: V BUS Error vs. V BUS Input Voltage vs. Temperature (Zoom View). 0.05% 3.3vDC 25 o C 0.1% 0 Error (%FullScale) % -0.1% Input Voltage Error (%FullScale) -0.2% -0.4% -0.6% -0.8% 3.3vDC -40 o C 3.3vDC 0 o C 3.3vDC 25 o C 3.3vDC 85 o C 3.3vDC 125 o C -0.5v 0v 0.5v 1v Input Voltage FIGURE 2-9: Voltage. V BUS Error vs. V BUS Input FIGURE 2-12: V BUS Error vs. V BUS Input Voltage vs. Temperature (Bipolar Voltage Mode). DS C-page Microchip Technology Inc.

11 Note: Unless otherwise indicated, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C, V DD = 3.3V, V BUS = 3.3V, V SENSE = (SENSE+ SENSE-) = 0V, V DD I/O = 1.62 to 5.5V. Error (%FullScale) 3.3vDC -40 o C 0.2% 3.3vDC 0 o C 3.3vDC 25 o C 0.1% 3.3vDC 85 o C 3.3vDC 125 o C 0-0.1% -0.2% 0v 5v 10v 15v 20v 25v 30v Input Voltage FIGURE 2-13: V BUS Error vs. V BUS Input Voltage vs. Temperature. DC Offset (LSB's 15b+sign) Temperature ( o C) FIGURE 2-16: Input Offset for V BUS Measurements vs. Temperature. 0 DC Offset (LSB's 15b+sign) Temperature ( o C) FIGURE 2-14: Zero Input Histogram for V BUS (LSBs, 8X Average Results, Total Population 5,000 devices). FIGURE 2-17: Input Offset for V SENSE Measurements vs. Temperature. SMBUS Drive Current (IOL) ma VIO=1.6v VDD=2.6v VIO=5.5v VDD=5.5v SMBUS Output Voltage (VOL) FIGURE 2-15: Zero Input Histogram for V SENSE (LSBs, 8X Average Results, Total Population 5,000 Devices). FIGURE 2-18: vs. V OL. I 2 C/SMBus Drive Current Microchip Technology Inc. DS C-page 11

12 Note: Unless otherwise indicated, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C, V DD = 3.3V, V BUS = 3.3V, V SENSE = (SENSE+ SENSE-) = 0V, V DD I/O = 1.62 to 5.5V. 1kSps mode Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Active Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v 16 Sps 256 Sps 1kSps Temperature ( o C) FIGURE 2-19: I DD vs. Temperature and Supply at 1024 Samples/Second. 8 Sps Temperature ( o C) FIGURE 2-22: I DD vs.temperature, V DD, and Sample Rate. 8Sps mode Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Sleep mode Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Temperature ( o C) FIGURE 2-20: I DD in SLOW Mode vs. Temperature and V DD Temperature ( o C) FIGURE 2-23: I DD in SLEEP Mode vs. Temperature and V DD. VIO Current (ua) VDD 2.6v/VIO 1.7v VDD 5.6v/VIO 1.7v VDD 2.6v/VIO 5.6v VDD 5.6v/VIO 5.6v Temperature ( o C) FIGURE 2-21: I DD for V DD I/O Pin vs. Temperature and V DD. PowerDown Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Temperature ( o C) FIGURE 2-24: I DD in Power Down Mode vs. Temperature and V DD. DS C-page Microchip Technology Inc.

13 Note: Unless otherwise indicated, maximum values are at T A = -40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C, V DD = 3.3V, V BUS = 3.3V, V SENSE = (SENSE+ SENSE-) = 0V, V DD I/O = 1.62 to 5.5V. Average Current 1kSps (ua) v CM 1v CM 5v CM 16v CM 32v CM Leakage Current (ua) v CM 1v CM 5v CM 16v CM 32v CM Temperature ( o C) FIGURE 2-25: V SENSE Input Current Active Mode, 1024 Samples/Second Temperature ( o C) FIGURE 2-28: V SENSE Input Leakage Current vs. V DD and Temperature. Leakage Current (ua) v v 5v v 32v Temperature ( o C) FIGURE 2-26: V BUS Input Leakage Current vs. V DD and Temperature. FIGURE 2-29: Clock Frequency Error -40 C to +85 C. Total Population 200 Devices. Average Current 1kSps (ua) v 1v 5v 16v 32v Temperature ( o C) FIGURE 2-27: V BUS Input Current Active Mode, 1024 Samples/Second. FIGURE 2-30: Clock Frequency Error at 30 C. Total Population 11,189 Devices Microchip Technology Inc. DS C-page 13

14 Figure 2-31 shows the equivalent circuitry for the input channels of the PAC193X devices. ESD protection diodes include two 40V breakdown diodes. Input leakage current is very low (no DC bias current). The switched capacitor sampling circuits shown as a switch with equivalent series resistance and sampling capacitor. The switches work at 1024 samples per second (SPS) maximum, independent of sampling rate (at 8 SPS, the device is sleeping in between samples). Input impedance for each input is about 32 MΩ. 6 kω V SENSE- 1 1 kω 6 kω 30 pf 1 kω 1 29 kω 30 pf V SENSE+ 1.2 pf 40V V V SS /GND FIGURE 2-31: Equivalent Input Circuits for PAC193X Devices. DS C-page Microchip Technology Inc.

15 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN DESCRIPTIONS QFN WLCSP16 Symbol Pin Type Description 1 C3 SLOW/ALERT Digital I/O pin Voltage range is set by V DD I/O pin. Default function is SLOW, may be programmed to function as ALERT pin (Open Collector when functioning as ALERT, requires pull-up resistor to V DD I/O). 2 A4 V DD Power for IC Positive power supply voltage. 3 B4 GND Ground pin Ground for the IC. 4 C4 SM_CLK SMBus clock input Clock Input pin. 5 D4 SM_DATA SMBus data I/O Open drain requires pull-up resistor to V DD I/O. 6 C2 ADDRSEL Analog I/O pin Address selection for the SMBus Slave address. 7 C1 SENSE3- (1) 32V analog pin 0-32V range, connect to load side of sense resistor. 8 D1 SENSE3+ (1) 32V analog pin 0-32V range, connect to supply side of sense resistor. 9 D2 SENSE4- (1) 32V analog pin 0-32V range, connect to load side of sense resistor. 10 D3 SENSE4+ (1) 32V analog pin 0-32V range, connect to supply side of sense resistor. 11 A3 SENSE1+ 32V analog pin 0-32V range, connect to supply side of sense resistor. 12 A2 SENSE1-32V analog pin 0-32V range, connect to load side of sense resistor. 13 A1 SENSE2+ 32V analog pin 0-32V range, connect to supply side of sense resistor. 14 B1 SENSE2-32V analog pin 0-32V range, connect to load side of sense resistor. 15 B2 V DD I/O Sets V IH reference for digital I/O Digital power reference level for digital I/O. 16 B3 PWRDN Digital input pin Voltage range is set by V DD I/O pin. Active low puts the device in power-down state (all circuitry is powered down including SMBus). 17 EP N/C The Exposed pad is not electrically connected. Note 1: For PAC1932, pins 7,8,9,10 are not connected inside and should be grounded. For PAC1933, pins 9 and 10 are not connected inside and should be grounded. 3.1 SenseN+/SenseN (N=1,2,3,4) These two pins form the differential input for measuring voltage across a sense resistor in the application. The positive input (SenseN+) also acts as the input pin for bus voltage. 3.2 Ground (GND) System ground. 3.3 SMBus Data (SM_DATA) This is the bi-directional SMBus data pin. This pin is open drain, and requires a pull-up resistor to V DD I/O. 3.4 SMBus Clock (SM_CLK) This is the SMBus clock input pin. 3.5 Positive Power Supply Voltage (V DD ) Power supply input pin for the device V range, bypass with 100 nf ceramic capacitor to ground near the IC. 3.6 Digital Power Reference Voltage (V DD I/O ) Connect this pin to the power supply voltage for the digital controller driving the SMBus pins and digital input pins for the device, 1.62V-5.5V. Bypass with 100 nf ceramic capacitor to ground near the IC. This pin does not supply power, instead it acts as the V IH reference. 3.7 Address Selection (ADDR_SEL) Connect a resistor from this pin to ground to select SMBus address Microchip Technology Inc. DS C-page 15

16 3.8 Enable Pin (PWRDN) Power down input pin for the device, active low. 3.9 SLOW/ALERT In default mode, if this pin is forced high, sampling rate is forced to eight samples/second. When it is forced low, the sampling rate is 1024 samples/second unless a different sample rate has been programmed.this pin may be programmed to act as the ALERT pin, in ALERT mode the pin needs a pull-up resistor to V DD I/O Exposed Thermal Pad Pin (EP) The Exposed pad is not electrically connected. It is recommended that you connect it to ground. DS C-page Microchip Technology Inc.

17 4.0 GENERAL DESCRIPTION The PAC1934 is a four-channel, bidirectional, high-side current-sensing device with precision voltage measurement capabilities, DSP for power calculation and a power accumulator. PAC1932 and PAC1933 are two and three channel versions of the PAC1934. These devices measure the voltage developed across an external sense resistor (V SENSE ) to represent the high-side current of a battery or voltage regulator. The PAC1932/3/4 also measures the SENSE+ pin voltages (V BUS ). Both V BUS and V SENSE are converted to digital results by a 16-bit ADC, and the digital results are multiplied to give V POWER. The V POWER results are accumulated on-chip, which enables energy measurement over the accumulation period. The PAC1932/3/4 has an I 2 C/SMBus interface for digital control and reading results. It also has digital supply reference V DD I/O that is to be connected to the same supply as the digital master for the I 2 C/SMBUS, enabling digital I/O voltages as low as 1.62V. A system diagram is shown in Figure 4-1. Sense Resistors V SOURCE 0V 32V Load V SOURCE 0V 32V Load V SOURCE 0V 32V Load V SOURCE 0V 32V Load 2.7V to 5.5V SENSE1+ SENSE2+ SENSE3+ SENSE4+ SENSE1- SENSE2- SENSE3- SENSE4- V DD I/O 1.62V to 5.5V Digital Supply V DD ADDRSEL PAC193X PAC1934 SM_CLK SM_DATA System Master GND SLOW PWRDN Note: V DD and V DD I/O may be connected together. FIGURE 4-1: PAC1932/3/4 System Diagram Microchip Technology Inc. DS C-page 17

18 VDD GND SENSE 1+ VBUS1 SENSE 1- SENSE 2+ SENSE 2- SENSE 3+ SENSE 3- SENSE 4+ SENSE 4- VBUS2 Sense1+ Sense1- Sense2+ Sense2- VBUS3 Sense3+ Sense3- VBUS4 Sense4+ Sense4- Differential VSENS E Amplifier VBUS Buffer/ Divider 16-bit ADC 16-bit ADC ADC/MUX Clocking & Control Calculation and Calibration Accumlator VBUS Registers VSENS E Registers VPOWE R Registers Accumulator Registers Control Registers I 2 C/SMBus VDD I/O SM_CLK SM_DATA SLOW/ALERT PWRDN High Voltage MUX Resistor Decoder ADDRSEL FIGURE 4-2: PAC1932/3/4 Functional Block Diagram. FIGURE 4-3: Resistor. PCB Pattern for Sense Figure 4-3 shows the recommended PCB pattern for sense resistor with wide metal for the high-current path. The drawing shows metal, solder paste openings and resistor outline. V SOURCE connects to the +terminal of the high-current path, and the load connects to the -terminal of the high-current path. Sense+ and Sense- have a Kelvin connection to the current sense resistor to ensure that no metal with high current is included in the V SENSE measurement path. Sense+ and Sense- are shown as a differential pair, route them as a differential pair to the Sense inputs at the chip. DS C-page Microchip Technology Inc.

19 4.1 Detailed Description A high-voltage multiplexer connects the input pins to the V BUS and V SENSE amplifiers. The amplifier outputs are sampled simultaneously for each channel, converted by 16 bit ADCs and processed for gain and offset error correction. After each conversion, V BUS and V SENSE are multiplied together to give V POWER. An internal oscillator and digital control signals control the two ADCs and the mux. The mux sequentially connects each channel s amplifiers to the ADC inputs. The PAC1932/3/4 measures the source-side voltage, V BUS, and the voltage V SENSE across an external current sense resistor, R SENSE INITIAL OPERATION AND ACTIVE STATE After POR and a start-up sequence, the device is in the Active state and begins sampling the inputs sequentially. Voltage and current are sampled for all active channels and power is calculated and accumulated. All active channels are sampled at 1024 samples/second by default. Sample rates of 256, 64 or eight samples/second may be programmed over I 2 C or SMBus. If the SLOW pin is asserted the sample rate is eight samples per second. For sampling rates lower than 1024 samples/second, the device is in Sleep mode for a portion of the conversion cycle, which results in lower power dissipation. If fewer than four channels are active, power is also reduced. To read accumulator data and reset the accumulators, the REFRESH command is used. To read the voltage, current, power and accumulator data without resetting the accumulators, the REFRESH_V command is used. Changes to the Control register (01h) are activated by sending either REFRESH or REFRESH_V. When a new value is written to the Control register (01h), the new values take effect at the end of the next round-robin sampling cycle following the next REFRESH or REFRESH_V command REFRESH COMMAND The master sends the REFRESH command after changing the Control register and/or before reading accumulator data from the device. The master controls the accumulation period in this manner. The readable registers for the V BUS, V SENSE, Power, accumulator outputs and accumulator count are updated by the REFRESH command and the values will be static until the next REFRESH command. These readable registers will be stable within 1 ms from sending the REFRESH command, and may be read by the master at any time up until the next REFRESH command is sent. The internal accumulator values and accumulator count will be reset by the REFRESH command, but the sampling of the inputs, data conversion and power integration is not interrupted and will continue as determined by the settings in the Control register. Changes written to the control and configuration registers take effect 1 ms after a REFRESH command is sent. Any new commands written within this 1 ms window will be ignored and NACKed to indicate that they are ignored. The values for V BUS and V SENSE measurement results and Power calculation results respond to the REFRESH command in the same fashion as the accumulators and accumulator count. The readable registers will be stable within 1 ms from sending the REFRESH command and may be read by the master at any time. The internal values continue to be updated according to the sampling plan determined by the settings in the Control register. The results that are sent to the readable registers for V BUS, V SENSE and Power are the values from the most recent complete conversion cycle. See Register 6-1 REFRESH Command (Address 00h) REFRESH_G COMMAND The REFRESH_G is identical in every respect to the REFRESH command, but it is used with the I 2 C General Call address ( ). This allows the system to issue a REFRESH command to all of the PAC1932/3/4 devices in the system with a single command. Then the data from this REFRESH_G command may be read device-by-device to capture a snapshot of the system power and energy for all devices. See Register 6-12 REFRESH_G Command (Address 1Eh). Note that the REFRESH_G command can also be used with a valid Slave address but in this case only the device with this Slave address will receive the command. In other words it has the same properties as the REFRESH command with the possibility of being compatible with the I 2 C General Call address REFRESH_V COMMAND If the user wants to read V SENSE and V BUS results, the most recent Power calculation, and/or the accumulator values and count without resetting the accumulators, the REFRESH_V command may be sent. Sending the REFRESH_V command and waiting 1 ms ensures that the V SENSE, V BUS, Power, accumulator and accumulator count values will be stable when read by the master. The sampling of the inputs, data conversion and power integration are not interrupted and will continue as determined by the settings in the Control register. The data in these readable registers will remain stable until the next REFRESH or REFRESH_V command. The internal accumulator values and accumulator count are unaffected by the REFRESH_V command Microchip Technology Inc. DS C-page 19

20 Note that the REFRESH_V command may also be used to activate changes to the Control register, just like the REFRESH command, except with the REFRESH_V command changes to the Control register will be enacted without resetting the accumulators or accumulator count. See Register 6-13 REFRESH_V Command (Address 1Fh) SLEEP STATE The SLEEP state is a lower power state than the Active state. While in this state, the device will draw a supply current of I SLEEP from the V DD pin. The device automatically goes to this state between conversion cycles when sampling rates lower than 1,024 samples/second are selected, or if fewer than four channels are active. All digital states and data are retained in the SLEEP state. The device can also be put in the Sleep state by setting the SLEEP bit followed by a REFRESH or REFRESH_V command, and sampling will resume when the SLEEP bit is cleared followed by a REFRESH of REFRESH_V command. The device does not go into SLEEP state based on any other condition such as static conditions on the SMBus pins. If SMBus Timeout is enabled, it is supported in SLEEP mode or ACTIVE mode POWER-DOWN STATE The Power-Down state is entered by pulling the PWRDN pin low. In this state, all circuits on the chip including the SMBus pins are inactive, and the device is in a state of minimum power dissipation. In the Power-Down state, no data is retained in the chip (neither register configuration nor measurement data). When the PWRDN pin is pulled high, integration, measurement and accumulation will begin using the default register settings, as described in Section Initial Operation and Active State. The first measurement data may be requested by a REFRESH or REFRESH_V command 20 ms after the PWRDN pin is pulled high PROGRAMMING THE SAMPLE RATE AND THE SLOW PIN The default sampling rate after power-up is 1024 samples/second. Sampling rates of 256, 64 or 8 samples/second may be programmed in the Register 6-2 CTRL Register (Address 01h). Any time a new sample rate is programmed, it does not take effect until a REFRESH, REFRESH_G, or REFRESH_V command is received. When any of these REFRESH commands are received, any round-robin sampling cycle in progress will complete before the new sampling rate takes effect. For example, if the user is sampling at 8 SPS and program a new sample rate, it may take up to 125 ms for the new sample rate to take effect and for all the sample rate related registers (like CTRL_ACT) to show their updated values. If one of these lower sample rates is used, power dissipation is reduced. The round-robin sampling and conversion cycle is exactly the same, but the device goes into the sleep state between conversion cycles. See Section 2.0 Typical Operating Curves. If the SLOW pin is pulled high, the device will sample at eight samples/second. No matter what the programmed sample rate, this new SLOW sample rate will take effect on the next conversion cycle (if a round-robin conversion cycle is in process when the SLOW pin goes high, that conversion cycle will complete before the SLOW sample rate takes effect.) If the device is programmed for Single Shot mode, and the SLOW pin is asserted, the first sampling will begin within 125 ms after the SLOW pin is asserted. If the device is in the Sleep state, asserting the SLOW pin will not cause sampling to start. Whenever the SLOW pin changes state, a limited REFRESH or REFRESH_V command may be executed by the chip hardware (default is REFRESH). Like any other REFRESH command, this resets the accumulators and accumulator count for a REFRESH command, and updates the readable registers for either REFRESH or REFRESH_V. These are limited REFRESH commands because no programmed changes to the Control or Status registers take effect (Control and Status registers means registers 01h, 1Ch, 1Dh, and 20h-26h). The readable registers are stable with the new values within 1 ms of the SLOW pin transition. The Slow register enables selection of REFRESH or REFRESH_V on the SLOW pin transitions, which allows this function to be disabled for either edge, and also tracks both the state of the SLOW pin and transitions on the SLOW pin. See Register 6-14, SLOW (Address 20h). This is the default functionality of the SLOW pin, but it may be reconfigured to function as an ALERT pin (see paragraph Section 4.4 Alert Functionality ). If the SLOW pin is configured to serve as an ALERT pin, the slower sampling rate of eight samples/second is only available by programming the Control register 01h. 4.2 Conversion Cycles A conversion cycle for the device consists of analog-to-digital conversion being complete for all channels (including the real-time calibration that is part of each conversion cycle). Immediately following the data conversion, the power results are calculated for that channel and the power value is added to the accumulator. Averaged values for V SENSE and V BUS are also updated internally as part of each conversion cycle. DS C-page Microchip Technology Inc.

21 Data conversion and processing is performed for each active channel in sequential fashion until all active channels have been converted, completing the conversion cycle for the device. The sequential sampling of each channel, along with the calculation time and any sleep time needed to set the overall sampling rate, is referred to as a round-robin sampling period. 4.3 Conversion Cycle Controls REDUCING THE NUMBER OF CHANNELS TO BE SAMPLED Program Register 6-10 CHANNEL_DIS and SMBus (Address 1Ch) to reduce the number of channels that are active. The sample rate is unaffected, but power dissipation is reduced very slightly if some channels are disabled. Any or all channels may be disabled; if all channels are disabled, the device goes into Sleep mode. When a channel is disabled due to register programming in the PAC1934 or due to factory programming on the PAC1932 and PAC1933, the auto incrementing pointer will skip these channels by default (see Section 5.5 Auto-Incrementing Pointer ) SINGLE SHOT MODE The Control register also allows the device to operate in Single Shot mode. In Single Shot mode, all active channels will sample and convert once, followed by results being calculated. The accumulator and accumulator count operate the same as for continuous conversion mode, accumulating each single shot power calculation and incrementing the accumulator count. The conversion cycle will start when the REFRESH command (or REFRESH_V or REFRESH_G) is sent. After the single shot measurements and calculations are complete, the device will go into Sleep mode. A REFRESH, REFRESH_G or REFRESH_V command may be sent to read the data. The user needs to wait 3 ms after the REFRESH command before commanding another Single Shot conversion by means of sending one of the REFRESH commands. This is because a 1 ms delay is required between REFRESH commands, and coming out of Sleep requires 2 ms USING THE ALERT FUNCTION To use the ALERT function, configure the SLOW pin to function as ALERT using Register 6-2 CTRL Register (Address 01h). For this configuration, the ALERT pin must have a pull-up to V DD I/O (it will function as an open drain output). If a pull-up resistor is attached to the pin for Alert functionality, the device will power up in Slow mode. Any of the four sample rates can be programmed using Register 6-2 CTRL Register (Address 01h). The Alert function for Accumulator Overflow can also be used without reconfiguring the SLOW pin, by monitoring the OVF bit in Register 6-2 CTRL Register (Address 01h) ALERT AFTER COMPLETE CONVERSION Register 6-2 has an ALERT_CC bit that can be used to enable the ALERT_CC function. If this bit is set, the ALERT pin will go low for 5 μs after each complete conversion cycle is complete ALERT ON ACCUMULATOR OVERFLOW If the ALERT function is enabled, and any of the accumulators or the accumulator count overflows, the ALERT pin may be used to notify the system. To enable this trigger for the ALERT pin, bit 1 in the Register 6-2 CTRL Register (Address 01h) must be set. Note that the OVF bit in the Register 6-2 CTRL Register (Address 01h) will be set when these overflows occur CLEARING ALERT AND OVF When the Alert function has been tripped by accumulator or accumulator count overflow, it will remain asserted until a REFRESH command is received. REFRESH_G will also clear the OVF bit and the Alert function, but REFRESH_V will not. 4.4 Alert Functionality The Alert functionality can serve two purposes: to notify the system that a conversion cycle for all active channels is complete, or to notify the system that the accumulator or accumulator count has overflowed Microchip Technology Inc. DS C-page 21

22 4.5 Voltage Measurement The V BUS voltage for each channel is measured by the SENSE+ pin for each channel. A high-voltage multiplexer is connected to each SENSE+ pin, and the multiplexer sequentially connects each SENSE+ input to and ADC for conversion. The result is stored in a 16-bit V BUS results register and the 14 MSBs are multiplied by the V SENSE number for the V POWER results value. The V POWER results are accumulated in the accumulator. Full-Scale Voltage (FSV) is 32V by default. The device may be programmed for bipolar V BUS measurements. in this bipolar mode, the mathematical range for negative V BUS numbers is -32V, the actual range is limited to about -200mV due to physical factors. This bipolar capability for V BUS enables accurate offset measurement and correction. For bipolar operation, the 16-bit V BUS result is a two s complement (signed) number. The measured voltage at SENSE+ can be calculated using Equation 4-1. EQUATION 4-1: Where: V Source BUS VOLTAGE V BUS = 32V Denominator V SOURCE = The measured voltage on the SENSE+ pin V BUS = The value read from the V BUS results registers Denominator = 2 16 for unipolar measurements = 2 15 for bipolar measurements 4.6 Current Measurement The PAC1932/3/4 device family includes high-side current sensing circuits. These circuits measure the voltage (V SENSE ) induced across a fixed external current sense resistor (R SENSE ) and store the voltage as a 16-bit number in the V SENSE Results registers. The PAC1932/3/4 current sensing operates with a Full-Scale Range (FSR) of 100 mv in unidirectional mode (default). When sensing unidirectional currents (the default mode), the ADC results are presented in straight binary format. For bidirectional current sensing, the ADC results are in two s complement (signed) format. For bipolar current measurements, the range is ±100 mv, but use FSR = 100 mv in the equations that follow. For best accuracy on current values near zero, it is recommended to use the bidirectional current mode and 8x average current results. 4.7 Selecting R SENSE Values R SENSE can easily be calculated if you know the maximum current you want to sense, as shown in Equation 4-2. Consider that you may need to select a value for IMax that includes current peaks well beyond your nominal current. EQUATION 4-2: CALCULATING R SENSE FSR Rsense = IMax Where: FSR = Full Scale V SENSE voltage input R SENSE = External R SENSE resistor value IMax = Maximum current to measure Full-Scale Current (FSC) can be calculated from Equation 4-3. EQUATION 4-3: FULL-SCALE CURRENT 100 mv FSC = R SENSE Where: FSC = Full-scale current R SENSE = External sense resistor value The actual current through R SENSE can then be calculated using Equation 4-4. EQUATION 4-4: Where: I SENSE SENSE CURRENT V SENSE = FSC Denominator I SENSE = Actual bus current FSC = Full-scale current value (from Equation 4-3) V SENSE = The value read from the V SENSE results registers Denominator = 2 16 for unipolar measurements = 2 15 for bipolar measurements DS C-page Microchip Technology Inc.

23 4.8 ADC Measurements, Offset, and 8x Averaging The PAC1932/3/4 is primarily desired for energy measurements where many power readings are accumulated. This is inherently an averaging process. Individual voltage and current measurements can also benefit from averaging to reduce noise and offset. Averaged values are internally calculated for V BUS and V SENSE, with a rolling average of the most recent eight values present in the VBUSn_AVG (Register 6-7) and VSENSEn_AVG (Register 6-6) registers. The average is updated internally after every conversion cycle. The readable registers are updated with REFRESH, REFRESH_V, or REFRESH_G commands like all the other readable results registers. These averaged results may be used for the most accurate, lowest noise and lowest offset measurements. The ADC channels use a special offset canceling technique. If the user observes the unaveraged results for near-zero values of V BUS and V SENSE, they may observe a cyclical pattern of offset variation. The user may think this is noise, but in fact it is due to internal circuitry switching through different permutations of offset cancellation circuitry. This small variation in unaveraged offset is canceled in the 8x averaged result. It is also canceled in the Power Accumulator results. The overall effect is offset that is consistently very close to zero LSB over supply and temperature variations. The offset canceling technique is illustrated in Figure 4-4. It is very difficult to accurately observe, as it is a challenge to read the data from every conversion cycle. The effect of capturing data points at a rate that does not correspond exactly to the internal sampling rate of the PAC1932/3/4 can make these permutations appear less periodic and deterministic than they are inside the chip. The data conversion uses one of the permute positions 1-4 for each input on each conversion, cycling through all four permutations in four conversions. When averaged the Permute Enabled result shown below is realized, evenly distributed around zero. FIGURE 4-4: Illustration of the Four Permute Combinations that the ADC Cycles through and the Resulting Low Average Offset. Each Bin Represents One Code. Results from both the V BUS and V SENSE ADCs are 17b two's complement (signed) internally. There is an additional bit of resolution that is not accessible from the results register. The NEG_PWR (Address 1Dh) register determines whether the conversion results are reported in the readable registers as unipolar or bipolar numbers. Using bipolar numbers can give more accurate results for very small numbers that may actually be negative for some readings, in addition to measuring bidirectional currents (charging/discharging) and voltages that can dip below ground. Averaged values are also calculated for V BUS and V SENSE. A rolling average of the most recent eight values is present in the VBUSn_AVG (Register 6-7) and VSENSEn_AVG (Register 6-6) registers. These registers require eight conversion cycles after POR before they represent an accurate value, they are updated after every conversion cycle. The readable registers are updated with REFRESH, REFRESH_V or REFRESH_G commands like all the other readable results registers Microchip Technology Inc. DS C-page 23

24 4.9 Power and Energy The Full-Scale Range for Power depends on the external sense resistor used, as shown in Equation 4-5. EQUATION 4-5: Where: PowerFSR POWER FSR CALCULATION = 100 mv R SENSE 32V = 3.2V 2 R SENSE R SENSE = External R SENSE resistor value 100 mv = Full-Scale V SENSE voltage input 32V = Full-Scale V BUS voltage input The device implements Power measurements by multiplying V BUS and the V SENSE to give a result V POWER. V POWER values are used to calculate Proportional Power as shown in Equation 4-6. The Proportional Power is the fractional portion of Power FSR measured in one sample. Bipolar mode is where V BUS is bipolar mode, V BUS is bidirectional mode, or both V BUS and V SENSE are bipolar/bidirectional. accumulation period, T. In this equation, T must be known from a system clock time stamp or other accurate indicator of the total accumulation period. EQUATION 4-8: Energy Where: ENERGY CALCULATION Vaccum T = P w r F S R Denominator AccCount Denominator = 2 28 (unipolar mode) = 2 27 (bipolar mode) EQUATION 4-9: ENERGY CALCULATION Where: Energy V accum PwrFSR = Denominator fs Denominator = 2 28 (unipolar mode) = 2 27 (bipolar mode) Equation 4-9 shows how to calculate energy using the accumulated power and the sampling rate, f s. EQUATION 4-6: PROPORTIONAL POWER CALCULATION P PROP = Vpower Denominator Where: Denominator = = 2 28 (unipolar mode) 2 27 (bipolar mode) To calculate the actual power from the Proportional Power, multiply by the Power FSR as shown in Equation 4-7. This Actual Power number is the power measured in one sample. EQUATION 4-7: POWER CALCULATION P actual = PowerFSR P PROP These V POWER results are digitally accumulated on chip, and stored in the VACCUM registers. The energy calculation Equations 4-8 and 4-9 use a different denominator term depending on unipolar or bipolar mode. Bipolar mode for energy applies when bipolar/bidirectional mode is used for V BUS and/or V SENSE. Equation 4-8 shows how to realize this using the Accumulator results, Accumulator count and the DS C-page Microchip Technology Inc.

25 4.9.1 ADDITIONAL ACCUMULATOR INFORMATION The math for the Power calculation and accumulation inside the chip is always done in two's complement math, no matter what the user sets the output registers to show. V BUS and V SENSE are 17-bit two's complement (signed) numbers internally. V POWER is the product of V SENSE multiplied by the 14 MSBs of V BUS, and this is a 31 bit two's complement result (signed) internally. In some cases this results in a Power result that is not identical to the product of the V BUS results register multiplied by the V SENSE register. However, the Power result from the Power results register is more accurate than the product of the V BUS register multiplied by the V SENSE register in these cases, as explained below. If V SENSE and V BUS are both programmed to be unsigned (unipolar) in register NEG_PWR (Address 1Dh), 16b without sign are exported to V BUS and V SENSE results registers. If V BUS is programmed to be signed (bipolar) in Register 6-11 NEG_PWR (Address 1Dh), the corresponding data is truncated to 16-bit two's complement (signed) for the readable results register. If V SENSE is programmed to be signed (bipolar) in register NEG_PWR (Address 1Dh), the corresponding results register value is truncated to 16-bit two's complement (signed), but the power calculation uses 17-bit two's complement (signed). Therefore, a mismatch is possible between an externally calculated power value (V BUS times V SENSE ) and the actual power value calculated internally to the chip. The internally calculated (and accumulated) value is more accurate than the externally calculated value in every case. The continuous power integration periods (also called the energy accumulation period) can range from ~1ms to many hours, depending on the number of samples per second selected via SMBus. The number of samples is limited by the size of the Accumulator Count register to 16,777,216 (2 24 ). This count corresponds to about 273 minutes at 1024 samples/second, or 582 hours at eight samples/second. This Accumulator Count can overflow, and it will not reset when it overflows. When the accumulation registers reach their maximum value, this is called accumulator overflow. The accumulator outputs remain at their maximum value; they do not roll over. The user can calculate the worst-case time to roll over and read them at or before that time or use the built in Alert functions to detect rollover and read them at that time. Worst-case accumulator overflow time can be calculated assuming that every measurement that is accumulated is a full-scale number. Since the power numbers are 28 bits, and the accumulator is 48 bits, 2 20 samples can be accumulated before overflow if they are all full-scale values. For most applications, they will not all be full-scale numbers; this is especially true if V BUS is not 32V. If V BUS is a lower number, the maximum number of full-scale samples that can be accumulated is scaled by 32V/V BUS. This limitation can limit the accumulation period before overflow to 17 minutes at 1024 samples/second, or 36 hours at eight samples/second, if most values are near full-scale. The Accumulator Count limit described above will still limit the total number of samples to Microchip Technology Inc. DS C-page 25

26 5.0 SMBUS AND I 2 C COMMUNICATIONS PROTOCOL The PAC1932/3/4 communicates over a two-wire bus with a controller using SMBus or I 2 C serial communication protocol. A detailed timing diagram is shown in Figure 1-1. Stretching of the SMCLK signal is supported; however, the PAC1932/3/4 will not stretch the clock signal. 5.1 I 2 C/SMBus Addressing and Control Bits SMBUS ADDRESS AND RD/WR BIT The SMBus Address Byte consists of the 7-bit slave address followed by a 1-bit RD / WR indicator. If this RD / WR bit is a logic 0, the SMBus master is writing data to the slave device. If this RD / WR bit is a logic 1, the SMBus master is reading data from the slave device. The PAC1932/3/4 I 2 C/SMBus address is determined by a single pull-down resistor connected between ground and the ADDRSEL pin as shown in Table 5-1. The chip translates the resistor value into an address on power-up, and the value is latched until another power-up event takes place. The address cannot be changed on the fly SMBUS DATA BYTES All SMBus data bytes are sent most significant bit first and composed of eight bits of information. TABLE 5-1: ADDRESS SELECT RESISTOR Resistor (1%) SMBus Address 0 (Tie to GND) 0010_000(r/w) _001(r/w) _010(r/w) 1, _011(r/w) 2, _100(r/w) 3, _101(r/w) 5, _110(r/w) 8, _111(r/w) 13, _000(r/w) 21, _001(r/w) 34, _010(r/w) 54, _011(r/w) 88, _100(r/w) 140, _101(r/w) 226, _110(r/w) Tie to V DD 0011_111(r/w) SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus data line from a logic 1 state to a logic 0 state while the SMBus Clock line is in a logic 1 state SMBUS ACK AND NACK BITS The SMBus slave will ACK (acknowledge) all data bytes that it receives. This is done by the slave device pulling the SMBus data line low after the eighth bit of each byte that is transmitted SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus data line from a logic 0 state to a logic 1 state while the SMBus clock line is in a logic 1 state. When the PAC1932/3/4 detects an SMBus Stop bit, and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications. DS C-page Microchip Technology Inc.

27 5.2 SMBus Time-Out The PAC1932/3/4 can support the SMBus Time-Out functionality. This functionality is disabled by default, and can be enabled by writing to the Timeout bit (see Register 6-10 CHANNEL_DIS and SMBus (Address 1Ch). If Time-Out is enabled and the clock is held at logic 0 for t TIMEOUT = ms, the device will time-out and reset the SMBus interface. Communication is restored with a start condition. 5.3 SMBus and I 2 C Compatibility The PAC1932/3/4 is compatible with SMBus MHz class and I 2 C Fast-mode Plus. The major differences between SMBus and I 2 C devices are highlighted here. For more information, refer to the SMBus 3.0 and I 2 C specifications. 1. If Time-Out function is enabled, the minimum frequency for SMBus communications is 10 khz. If Time-Out function is disabled (default condition), then there is no minimum frequency for SMBus communications. 2. If SMBus Time-Out is enabled in Register 6-10: CHANNEL_DIS and SMBus (Address 1Ch),the SMBus slave protocol will reset if the clock is held at a logic 0 for t TIMEOUT. I 2 C does not have a time-out, this is the default condition. 3. I 2 C devices do not support the Alert Response Address functionality (which is optional for SMBus).The PAC1932/3/4 does not support the Alert Response Address functionality; instead, the ALERT is a GPIO pin that may be monitored by the master or Embedded Controller. 4. I 2 C devices support Block Read and Block Write differently. I 2 C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol for Block Read and Block Write requires that an additional data byte indicating number of bytes to read/write is transmitted. PAC1932/3/4 devices support the I 2 C protocol for Block Read by default (no byte count information is sent). If the Byte Count bit is set (see Register 6-10: CHANNEL_DIS and SMBus (Address 1Ch), it will be sent as the first data byte in response to the Block Read command, per SMBus protocol. 5.4 I 2 C/SMBus Protocols The PAC1932/3/4 supports Write Byte, Read Byte, Block Read, Send Byte and Receive Byte as valid protocols. It will not respond to the Alert Response Address protocol. It will respond to the I 2 C General Call Address. All of the protocol charts listed below use the convention in Table 5-2. TABLE 5-2: PROTOCOL FORMAT Data Sent to Device Data Sent to the Master # of bits sent # of bits sent 5.5 Auto-Incrementing Pointer The PAC1932/3/4 has an auto-incrementing address pointer. The pointer has two loops for auto-incrementing, a read loop and a write loop. The read loop includes all of the readable registers all of the configuration and Control registers, the results registers, and the Product ID, Manufacturer ID and Revision ID registers. The write loop includes only the writable control and configuration registers. Neither loop includes the REFRESH commands. The read loop will skip inactive channels, if some channels have been disabled. This automatic channel skipping feature can be disabled by setting the No Skip bit in Register 6-10: CHANNEL_DIS and SMBus (Address 1Ch). If the user elects to read disabled channels, they will return FFh and the register address will by NACKed. See Figure 5-1 for a graphic representation Microchip Technology Inc. DS C-page 27

28 App Read Loop App Write Loop Channels ON or (Channels OFF and Skip OFF) Channels 1 & 4 OFF and Skip ON Channels OFF and Skip ON Don t care if Channels ON or OFF 0x00 W 1 byte REFRESH REFRESH REFRESH REFRESH 0x01 R/W 1 byte CTRL CTRL CTRL CTRL 0x02 R 3 bytes ACC_COUNT ACC_COUNT ACC_COUNT ACC_COUNT 0x03 R 6 bytes VPOWER1_ACC VPOWER1_ACC VPOWER1_ACC VPOWER1_ACC 0x04 R 6 bytes VPOWER2_ACC VPOWER2_ACC VPOWER2_ACC VPOWER2_ACC 0x05 R 6 bytes VPOWER3_ACC VPOWER3_ACC VPOWER3_ACC VPOWER3_ACC 0x06 R 6 bytes VPOWER4_ACC VPOWER4_ACC VPOWER4_ACC VPOWER4_ACC 0x07 R 2 bytes VBUS1 VBUS1 VBUS1 VBUS1 0x08 R 2 bytes VBUS2 VBUS2 VBUS2 VBUS2 0x09 R 2 bytes VBUS3 VBUS3 VBUS3 VBUS3 0x0A R 2 bytes VBUS4 VBUS4 VBUS4 VBUS4 0x0B R 2 bytes VSENSE1 VSENSE1 VSENSE1 VSENSE1 0x0C R 2 bytes VSENSE2 VSENSE2 VSENSE2 VSENSE2 0x0D R 2 bytes VSENSE3 VSENSE3 VSENSE3 VSENSE3 0x0E R 2 bytes VSENSE4 VSENSE4 VSENSE4 VSENSE4 0x0F R 2 bytes VBUS1_AVG VBUS1_AVG VBUS1_AVG VBUS1_AVG 0x10 R 2 bytes VBUS2_AVG VBUS2_AVG VBUS2_AVG VBUS2_AVG 0x11 R 2 bytes VBUS3_AVG VBUS3_AVG VBUS3_AVG VBUS3_AVG 0x12 R 2 bytes VBUS4_AVG VBUS4_AVG VBUS4_AVG VBUS4_AVG 0x13 R 2 bytes VSENSE1_AVG VSENSE1_AVG VSENSE1_AVG VSENSE1_AVG 0x14 R 2 bytes VSENSE2_AVG VSENSE2_AVG VSENSE2_AVG VSENSE2_AVG 0x15 R 2 bytes VSENSE3_AVG VSENSE3_AVG VSENSE3_AVG VSENSE3_AVG 0x16 R 2 bytes VSENSE4_AVG VSENSE4_AVG VSENSE4_AVG VSENSE4_AVG 0x17 R 4 bytes VPOWER1 VPOWER1 VPOWER1 VPOWER1 0x18 R 4 bytes VPOWER2 VPOWER2 VPOWER2 VPOWER2 0x19 R 4 bytes VPOWER3 VPOWER3 VPOWER3 VPOWER3 0x1A R 4 bytes VPOWER4 VPOWER4 VPOWER4 VPOWER4 0x1C R/W 1 byte CHANNEL_DIS CHANNEL_DIS CHANNEL_DIS CHANNEL_DIS 0x1D R/W 1 byte NEG_PWR NEG_PWR NEG_PWR NEG_PWR 0x1E W 1 byte REFRESH_G REFRESH_G REFRESH_G REFRESH_G 0x1F W 1 byte REFRESH_V REFRESH_V REFRESH_V REFRESH_V 0x20 R/W 1 byte SLOW SLOW SLOW SLOW 0x21 R 1 byte CTRL_ACT CTRL_ACT CTRL_ACT CTRL_ACT 0x22 R 1 byte CHANNEL_DIS_ACT CHANNEL_DIS_ACT CHANNEL_DIS_ACT CHANNEL_DIS_ACT 0x23 R 1 byte NEG_PWR_ACT NEG_PWR_ACT NEG_PWR_ACT NEG_PWR_ACT 0x24 R 1 byte CTRL_LAT CTRL_LAT CTRL_LAT CTRL_LAT 0x25 R 1 byte CHANNEL_DIS_LAT CHANNEL_DIS_LAT CHANNEL_DIS_LAT CHANNEL_DIS_LAT 0x26 R 1 byte NEG_PWR_LAT NEG_PWR_LAT NEG_PWR_LAT NEG_PWR_LAT 0xFD R 1 byte PID PID PID PID 0xFE R 1 byte MID MID MID MID 0xFF R 1 byte REV REV REV REV FIGURE 5-1: READ and WRITE Auto Incrementing Loops. Figure 5-1 shows how the auto-incrementing READ loop works with SKIP option on and off, for reading. It also shows how the WRITE loop works with the REFRESH, REFRESH_V, and REFRESH_G commands. DS C-page Microchip Technology Inc.

29 5.6 I 2 C/SMBus Commands REFRESH AND REFRESH_V REFRESH and REFRESH_V commands are sent using the Send byte command, the Slave Address and the desired command (00h for REFRESH or 1Fh for REFRESH_V. See Table 5-3. TABLE 5-3: REFRESH AND REFRESH_V COMMANDS START Slave Address WR ACK REFRESH or REFRESH_V Command ACK STOP 1 0 YYYY_YYY h or 1Fh GENERAL CALL ADDRESS RESPONSE When the master sends the General Call address, the PAC1932/3/4 will be able to execute the REFRESH command by means of a second version of the REFRESH command called REFRESH_G (see Register 6-12 REFRESH_G Command (Address 1Eh)). Just as the REFRESH command is sent using a Send Byte command with the slave address, and the REFRESH command (00h), the REFRESH_G command is sent using Send Byte with the General Call address ( ) and the REFRESH_G command (1Eh). Table 5-4 shows the response to the General Call command for REFRESH_G. TABLE 5-4: GENERAL CALL RESPONSE START General Call Address WR ACK REFRESH_G Command ACK STOP _ Eh WRITE BYTE The Write Byte is used to write one byte of data to the registers, as shown in Table 5-5. TABLE 5-5: WRITE BYTE PROTOCOL START Slave Address WR ACK Register Address ACK Register Data ACK STOP 1 0 YYYY_YYY 0 0 XXh 0 XXh Microchip Technology Inc. DS C-page 29

30 5.6.4 READ BYTE The Read Byte protocol is used to read one byte of data from the registers, as shown in Table 5-6. If an invalid register address is specified, the slave will ACK its address but NACK (not acknowledge) the register address. The master will NACK the data received from the slave by holding the SMBus data line high after the eighth data bit has been sent. TABLE 5-6: READ BYTE PROTOCOL START Slave Address WR ACK Register Address ACK START Slave Address RD ACK Register Data NACK STOP 1 0 YYYY_YYY 0 0 XXh YYYY_YYY 1 0 XXh SEND BYTE The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol, as shown in Table 5-7. TABLE 5-7: SEND BYTE PROTOCOL START Slave Address WR ACK Register Address ACK STOP 1 0 YYYY_YYY 0 0 XXh RECEIVE BYTE The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via Send Byte). This is shown in Table 5-8. When an ACK is received after the REGISTER DATA, then the address pointer automatically increments. When a NACK is received after the REGISTER DATA, then the address pointer stays at the same position. If the master wishes to continue clocking and read the next register, the master will ACK after the register data, instead of sending NACK followed by STOP. If some channels are deactivated, their data registers will be skipped by the auto-incrementing pointer. Alternatively, you may set bit 0 in Register 6-10 CHANNEL_DIS and SMBus (Address 1Ch) and the pointer will not skip the addresses associated with the inactive channels. The measurement data for these inactive channels will read FFh. TABLE 5-8: RECEIVE BYTE PROTOCOL START Slave Address RD ACK Register Data NACK STOP 1 0 YYYY_YYY 1 0 XXh DS C-page Microchip Technology Inc.

31 5.6.7 BLOCK READ I 2 C VERSION Block Read is used to read multiple data bytes from a register that contains more than one byte of data, or from a group of contiguous registers, as shown in Table 5-9. The PAC1932/3/4 supports I 2 C Block Read by default, but the SMBus format can also be supported (see Table 5-10). If an invalid register address is specified, the slave will ACK its address but NACK the register address. The master will NACK the data received from the slave by holding the SMBus data line high after the 8 th data bit has been sent. TABLE 5-9: BLOCK READ PROTOCOL I 2 C VERSION (DEFAULT) START Slave Address WR ACK Register Address ACK START Slave Address RD ACK Register Data 1 0 YYYY_YYY 0 0 XXh YYYY_YYY 1 0 XXh ACK Register Data ACK Register Data ACK Register Data ACK Register Data NACK STOP 0 XXh 0 XXh 0 XXh 0 XXh BLOCK READ SMBUS VERSION PAC1932/3/4 can also support the SMBus version of Block Read. If the Byte Count bit is set, Block Read will result in the device sending the Byte Count data before the first data byte. This protocol is shown in Table Also see Section 4.3 Conversion Cycle Controls above and Register 6-10 CHANNEL_DIS and SMBus (Address 1Ch). TABLE 5-10: BLOCK READ PROTOCOL SMBUS VERSION (MUST SET BYTE COUNT BIT) START Slave Address WR ACK Register Address ACK START Slave Address RD ACK Byte Count 1 0 YYYY_YYY 0 0 XXh YYYY_YYY 1 0 XXh = N ACK Register Data ACK Register Data ACK Register Data ACK Register Data NACK STOP 0 XXh 0 XXh 0 XXh 0 XXh Microchip Technology Inc. DS C-page 31

32 6.0 REGISTERS IN HEXADECIMAL ORDER The registers shown in Table 6-1 are accessible through the SMBus. In the individual register tables that follow, an entry of indicates that the bit is not used and will always read 0. Data represented by the data registers are ensured to be synchronized and stable 1 ms after any of the REFRESH commands are sent. Immediately after the REFRESH commands are sent, the data bytes will be changing dynamically until 1 ms has elapsed. When new data is written to a Control register, and the master reads it back, this new data will be read back even if no REFRESH command has been sent to cause the new data to take effect. Note: The letter N or n is used to represent 1,2,3,4 in the register and bit names below, in sections that describe registers that are grouped for all four channels. Note: For PAC1932, channels 3 and 4 do not contain validate data and will read FF. The auto-incrementing pointer will skip these channels by default (see Section 5.5 Auto-Incrementing Pointer ). The same applies to channel 4 for the PAC1933. TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER Register Number Register 6-1 REFRESH Command (Address 00h) Register 6-2 CTRL Register (Address 01h) Register 6-3 ACC_COUNT Register (Address 02h) Register 6-4 VPOWERN Accumulator Registers: VPOWER1_ACC(03h), VPOWER2_ACC (04h), VPOWER3_ACC (05h), VPOWER4_ACC (06h) Description Type Bytes POR Value Send Byte for REFRESH command SEND 0 00h Configuration controls and status R/W 1 00h Accumulator count for all channels Accumulator output for channel 1 Accumulator output for channel 2 Accumulator output for channel 3 Accumulator output for channel 4 Block Read Block Read Block Read Block Read Block Read h 6 Note 1 6 Note 1 6 Note 1 6 Note 1 Note 1: The VPOWERN Accumulator Registers, 03h-06h, have a POR value that is all zeros: 6 bytes h. DS C-page Microchip Technology Inc.

33 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Number Register 6-5 VBUSN Result Registers VBUS1 (07h), VBUS2 (08h), VBUS3 (09h),VBUS4 (0Ah ) Register 6-6 VSENSEn Result Registers: VSENSE1 (0Bh), VSENSE2 (0Ch), VSENSE3 (0Dh), VSENSE4 (0Eh) Register 6-7 VBUSN_AVG Result Registers VBUS1_AVG (0Fh), VBUS2_AVG (10h), VBUS3_AVG (11h), VBUS4_AVG (12h) Register 6-8 VSENSEn AVG Result Register VSENSE1_AVG (13h), VSENSE2_AVG (14h), VSENSE3_AVG(15h), VSENSE4_AVG (16h) Register 6-9 VPOWERN Result Register: VPOWER1 (17h), VPOWER2 (18h), VPOWER3 (19h), VPOWER4 (1Ah) Register 6-10 CHANNEL_DIS and SMBus (Address 1Ch) Register 6-11 NEG_PWR (Address 1Dh) Register 6-12 REFRESH_G Command (Address 1Eh) Description Type Bytes V BUS measurement for channel 1 V BUS measurement for channel 2 V BUS measurement for channel 3 V BUS measurement for channel 4 V SENSE measurement for channel 1 V SENSE measurement for channel 2 V SENSE measurement for channel 3 V SENSE measurement for channel 4 Rolling average of eight most recent V BUS1 measurements Rolling average of eight most recent V BUS2 measurements Rolling average of eight most recent V BUS3 measurements Rolling average of eight most recent V BUS4 measurements Rolling average of eight most recent V SENSE1 measurements Rolling average of eight most recent V SENSE2 measurements Rolling average of eight most recent V SENSE3 measurements Rolling average of eight most recent V SENSE4 measurements V SENSE x V BUS for Channel 1 V SENSE x V BUS for Channel 2 V SENSE x V BUS for Channel 3 V SENSE x V BUS for Channel 4 Disable selected channels, activate SMBus functionality, pointer increment Configuration control for enabling bidirectional current and bipolar voltage measurements REFRESH response to General Call Address Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read Block Read h h h h h h h h h h h h h h h h h h h h R/W 1 00h R/W 1 00h SEND 0 N/A Note 1: The VPOWERN Accumulator Registers, 03h-06h, have a POR value that is all zeros: 6 bytes h. POR Value Microchip Technology Inc. DS C-page 33

34 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Number Register 6-13 REFRESH_V Command (Address 1Fh) Register 6-14 SLOW (Address 20h) Register 6-15 CTRL_ACT Register (Address 21h) Register 6-16 Channel DIS_ACT (Address 22h) Register 6-17 NEG_PWR_ACT (Address 23h) Register 6-18 CTRL_LAT Register (Address 24h) Register 6-19 Channel DIS_LAT (Address 25h) Register 6-20 NEG_PWR _LAT (Address 26h) Register 6-21 Product ID Register (Address FDh) Register 6-22 Manufacturer ID Register (Address FEh) Register 6-23 Revision ID Register (Address FFh) Description Type Bytes Refreshes V BUS and V SENSE data only, no accumulator reset Status and control for SLOW pin functions Currently active value of 01h (Control) Currently active value of 1Ch (CHANNEL_DIS and SMBus) Currently active value of 1Dh(NEG_PWR) SEND 0 N/A R/W 1 15h R 1 00h R 1 00h R 1 00h Latched image of 21h (CTRL_ACT) R 1 00h Latched image of 22h (Channel DIS_ACT) Latched image of 23h (NEG_PWR_ACT) R 1 00h R 1 00h Stores the Product ID R 1 5Bh Stores the Manufacturer ID R 1 5Dh Stores the revision R 1 03h Note 1: The VPOWERN Accumulator Registers, 03h-06h, have a POR value that is all zeros: 6 bytes h. POR Value DS C-page Microchip Technology Inc.

35 6.1 Detailed Register Information REGISTER 6-1: REFRESH COMMAND (ADDRESS 00H) SEND SEND SEND SEND SEND SEND SEND SEND No Data in this command, Send Byte only bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-0 This command is a SEND Byte, does not contain any data. When it is sent to the device, the REFRESH command is executed. The accumulator data, accumulator count, V BUS, and V SENSE measurements are all refreshed and the accumulators are reset. The master can read the accumulator data and accumulator count anytime 1 ms after the REFRESH command is sent, and anytime after than up until the next REFRESH command is sent. (The master can read V BUS and V SENSE data in the same time period. The accumulator results, accumulator count, V BUS and V SENSE data can be refreshed with the REFRESH_V command without resetting the accumulators, see Register 6-7). REGISTER 6-2: CTRL REGISTER (ADDRESS 01H) RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0 Sample_Rate<1:0> SLEEP SING ALERT_PIN ALERT_CC OVF ALERT OVF bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-1 bit 7-6 bit 5 Write to these bits to change settings from default value. Sample_Rate<1:0>: determines sample rate in Normal mode (if SLOW pin is not asserted). 00b = 1024 samples/s 01b = 256 samples/s 10b = 64 samples/s 11b = 8 samples/s SLEEP: setting this bit to 1, followed by the REFRESH or REFRESH_V command, puts the device in SLEEP mode. All programmed, readable, and measured digital data is stable in this mode. Clearing the SLEEP bit and sending a REFRESH or REFRESH_V command causes the device become active and start converting in the mode specified by the Control registers (unless the SLOW pin is asserted, in which case it will start converting at an 8 Hz rate). The SLEEP bit has higher priority than the SING bit or the SLOW pin, if the SLEEP bit is set the device goes into SLEEP mode not matter how the SING bit or the SLOW pin are set. 0 = Active mode 1 = SLEEP mode, no data conversion Microchip Technology Inc. DS C-page 35

36 REGISTER 6-2: CTRL REGISTER (ADDRESS 01H) (CONTINUED) bit 4 bit 3 bit 2 bit 1 bit 0 SING: setting this bit to 1 puts the device in Single-shot mode. After writing this bit and sending a REFRESH command, the device resets the accumulators and performs one conversion cycle for any and all active channels, then returns to sleep mode. Another REFRESH command, without changing this bit, will perform another single-shot command. When the bit is cleared, sending a REFRESH command resets the accumulators and causes the device to start converting in the sequential scan mode for active channels. A REFRESH_V command may be used instead of REFRESH to move in and out of Single Shot mode without resetting the accumulators and accumulator count. 0 = Sequential scan mode 1 = Single-shot mode ALERT_PIN: setting this bit to 1 causes the SLOW pin to function as an ALERT pin (active low output pin). If this bit is set to 1, the ALERT pin can be triggered by conversion complete if bit 2 is set. If this bit is set to 1, and the Overflow ALERT enable bit is set to 1, the ALERT pin will be triggered by accumulator or accumulator count overflow (see bit 1 and bit 0 descriptions directly below). Note that bit 3 only determines the functionality of this pin, SLOW or ALERT, it does not influence the ALERT functionality. If there is a pull-up resistor connected to the pin for ALERT functionality, the device will initially power-up in SLOW mode. Once bit 3 is set to enable ALERT functionality, the conversion rate will change to either the default or programmed value. 0 = Disable the ALERT pin function 1 = Enable the ALERT pin function ALERT_CC: setting this bit to 1 causes the ALERT pin to be asserted for 5 μs at the end of each conversion cycle. 0 = No ALERT on Conversion Cycle Complete 1 = ALERT function asserted for 5 μs on each completion of the conversion cycle Note: If this bit and the OVF ALERT bit are set, OVF ALERT dominates. EOC alerts will not be seen on the ALERT pin if OVF ALERT = 1. OVF ALERT: Overflow ALERT enable. If this bit is set and any of the accumulators or the accumulator counter overflow, the ALERT function will be triggered. This will be reflected in bit 0 of this register, and if bit 3 is set to 1, the ALERT pin will be triggered (sent low). The ALERT function is cleared by REFRESH or REFRESH_G. 0 = no ALERT if accumulator or accumulator counter overflow has occurred. 1 = ALERT pin triggered if accumulator or accumulator counter has overflowed If this bit and the ALERT_CC bit are set, OVF ALERT dominates. EOC alerts will not be seen on the ALERT pin if OVF ALERT =1. OVF: Overflow indication status bit, this bit will be set to 1 if any of the accumulators or the accumulator counter overflows.this bit is by cleared REFRESH or REFRESH_G. These commands also clear the ALERT function. 0 = no accumulator or accumulator counter overflow has occurred. 1 = accumulator or accumulator counter has overflowed DS C-page Microchip Technology Inc.

37 REGISTER 6-3: ACC_COUNT REGISTER (ADDRESS 02h) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC_COUNT<23:16> bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC_COUNT<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC_COUNT<7:0> bit 7 bit0 bit0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 23-0 ACC_COUNT<23:0>: contain the count for each time a power result has been summed in the accumulator Microchip Technology Inc. DS C-page 37

38 REGISTER 6-4: VPOWERN ACCUMULATOR REGISTERS: VPOWER1_ACC(03h), VPOWER2_ACC (04h), VPOWER3_ACC (05h), VPOWER4_ACC (06h) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<47:40> bit 47 bit 40 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<39:32> bit 39 bit 32 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<31:24> bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<23:16> bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 47-0 VPOWERn_ACC<47:0>: contain the accumulated sum of V POWER samples, where n = 1 to 4, depending on device. These are 48 bit unsigned numbers unless either V BUS or V SENSE are configured to have a bipolar range. In that case they will be 48-bit two's complement (signed) numbers. Note that power is always calculated and accumulated using signed numbers for V BUS and V SENSE, but if both V BUS and V SENSE are in the default unipolar mode, power is reported as an unsigned number. This can lead to very small discrepancies between a manual comparison of the product of V BUS and V SENSE and the results that the chip calculates and accumulates for V POWER. The digital math in the chip uses more bits than the reported results for V BUS and V SENSE, so the results registers for V POWER and Accumulated Power will in some cases have a more accurate number than calculations using the results registers for V SENSE and V BUS will provide. DS C-page Microchip Technology Inc.

39 REGISTER 6-5: VBUSN RESULT REGISTERS VBUS1 (07h), VBUS2 (08h), VBUS3 (09h),VBUS4 (0Ah) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VBUSn<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VBUSn<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 15-0 VBUSn<15:0>: contain the most recent digitized value of a V BUS sample, where n = 1 to 4, depending on device. These are 16 bit unsigned numbers unless V BUS is configured to have a bipolar range. In that case they will be 16-bit two's complement (signed) numbers. REGISTER 6-6: VSENSEn RESULT REGISTERS: VSENSE1 (0Bh), VSENSE2 (0Ch), VSENSE3 (0Dh), VSENSE4 (0Eh) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VSENSEn<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VSENSEn<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 15-0 VSENSEn<15:0>: contain the most recent digitized value of V SENSE samples, where n = 1 to 4, depending on device. These are 16 bit unsigned numbers unless V SENSE is configured to have a bipolar range. In that case they will be 16-bit two's complement (signed) numbers Microchip Technology Inc. DS C-page 39

40 REGISTER 6-7: VBUSN_AVG RESULT REGISTERS VBUS1_AVG (0FH), VBUS2_AVG (10H), VBUS3_AVG (11H), VBUS4_AVG (12H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VBUSn_AVG<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VBUSn_AVG<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 15-0 VBUSn_AVG<15:0>: contain a rolling average of the eight most recent V BUS measurements. They have the same format as the values in the V BUS registers. REGISTER 6-8: VSENSEn AVG RESULT REGISTER VSENSE1_AVG (13H), VSENSE2_AVG (14H), VSENSE3_AVG(15H), VSENSE4_AVG (16H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VSENSEn_AVG<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VSENSEn_AVG<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 15-0 VSENSEn_AVG<15:0>: contain a rolling average of the eight most recent V SENSE results. They have the same format as the values in the V SENSE registers. DS C-page Microchip Technology Inc.

41 REGISTER 6-9: VPOWERN RESULT REGISTER: VPOWER1 (17H), VPOWER2 (18H), VPOWER3 (19H), VPOWER4 (1AH) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<27:20> bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<19:12> bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPOWERn<11:4> bit 15 bit 8 R-0 R-0 R-0 R-0 U U U U VPOWERn<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 31-4 VPOWERn<27:0>: these registers contain the product of V BUS (14 MSBs) and V SENSE which represents Proportional Power for each channel.these are 28 bit unsigned numbers unless either V BUS or V SENSE are configured to have a bipolar range. In that case they will be 28-bit two's complement (signed) numbers.these are the numbers that are accumulated in the accumulators. Note that power is always calculated using signed numbers for V BUS and V SENSE, but if both V BUS and V SENSE are in the default unipolar mode, power is reported as an unsigned number. This can lead to very small discrepancies between a manual comparison of the product of V BUS and V SENSE and the results that the chip calculates for V POWER.The digital math in the chip uses more bits than the reported results for V BUS and V SENSE, so the results registers for V POWER and Accumulated Power will in some cases have a more accurate number than calculations using the results registers for V SENSE and V BUS will provide. bit 3-0 Not used at this time, always reads Microchip Technology Inc. DS C-page 41

42 REGISTER 6-10: CHANNEL_DIS AND SMBUS (ADDRESS 1CH) RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 U CH1_OFF CH2_OFF CH3_OFF CH4_OFF TIMEOUT BYTE NO SKIP COUNT bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-4 CHn_OFF<7:4>: allows one or more channels to be inactive during the conversion cycle. These settings apply for normal continuous round-robin conversion cycles or Single-Shot mode, if Single-Shot mode is selected. Note that if a channel is set to inactive, the auto incrementing address pointer will skip addresses associated with that channel unless the Pointer Skipping bit 1 in this register is set. Changes to bits 7-4 do not take effect until a REFRESH, REFRESH_V, or REFRESH_G command are sent. Changes to bits 3-1 take place as soon as a new value is written, they are not gated by a REFRESH command like most other control bits. bit 7 0 = CH1 ON. Channel 1 active during conversion cycle 1 = CH1 OFF. Channel 1 inactive during conversion cycle bit 6 0 = CH1 ON. Channel 2 active during conversion cycle 1 = CH1 OFF. Channel 2 inactive during conversion cycle bit 5 0 = CH1 ON. Channel 3 active during conversion cycle 1 = CH1 OFF. Channel 3 inactive during conversion cycle (for PAC1932 and PAC1933, this bit is set to 1 with factory trim and cannot be written) bit 4 0 = CH1 ON. Channel 4 active during conversion cycle 1 = CH1 OFF. Channel 4 inactive during conversion cycle (for PAC1933, this bit is set to 1 with factory trim and cannot be written) bit 3 TIMEOUT: Timeout enable bit. The SMBus timeout is disabled by default, and is enabled by setting this bit. 0 = No SMBus timeout feature 1 = SMBus timeout feature is available. bit 2 BYTE COUNT: causes Byte Count data to be included in the response to the SMBus Block Read command for each register read. This functionality is disabled by default, and Block Read corresponds to I 2 C protocol. 0 = No Byte Count in response to a Block Read command 1 = Data in response to a Block Read command includes the Byte Count data bit 1 NO SKIP: controls the auto-incrementing of the address pointer for channels that are inactive. 0 = The auto-incrementing pointer will skip over addresses used by/for channels that are inactive. 1 = The auto-incrementing pointer will not skip over addresses used by/for channels that are inactive. With this setting, these channels that are disabled will read 0xFF if read. bit 0 Unimplemented bits always read 0. DS C-page Microchip Technology Inc.

43 REGISTER 6-11: NEG_PWR (ADDRESS 1DH) RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 CH1_BIDI CH2_BIDI CH3_BIDI CH4 BIDI CH1_BIDV CH2_BIDV CH3_BIDV CH4_BIDV bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-4 bit 3-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CHn_BIDI<7:4>: these control bits allow the user to enable bidirectional current measurements for any channel, which will result in the V SENSE voltage measurement data being in 16-bit two's complement (signed) format. If the channel is enabled for negative current measurements, the full scale range for V SENSE is -100 mv to +100 mv. If these bits are enabled for any channel, that channel s power numbers are also capable of reporting bidirectional numbers in two s complement format. CHn_BIDI<3:0>: these control bits allow the user to enable bidirectional/bipolar voltage measurements for any channel, which will result in the V BUS voltage measurement data being in 16 bit two s complement format. If the channel is enabled for negative voltage measurements, the full scale range for V BUS is +32V to -32V. Note that this range is the digital FSR, the V BUS input will not give accurate measurements if taken more than 200 mv below ground. If these bits are enabled for any channel, that channel s power numbers are also capable of reporting bidirectional numbers in two s complement format. 0 = Channel 1 V SENSE ADC converts 0 to +100 mv range with 16-bit straight binary output 1 = Channel 1 V SENSE ADC converts -100 mv to +100 mv range with 16-bit two s complement output 0 = Channel 2 V SENSE ADC converts 0 to +100 mv range with 16 bit straight binary output 1 = Channel 2 V SENSE ADC converts -100 mv to +100 mv range with 16 bit two s complement output 0 = Channel 3 V SENSE ADC converts 0 to +100 mv range with 16-bit straight binary output 1 = Channel 3 V SENSE ADC converts -100 mv to +100 mv range with 16-bit two s complement output 0 = Channel 4 V SENSE ADC converts 0 to +100 mv range with 16-bit straight binary output 1 = Channel 4 V SENSE ADC converts -100 mv to +100 mv range with 16 bit two s complement output 0 = Channel 1 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 1 V BUS ADC converts -32V to +32 range with 16-bit two s complement output 0 = Channel 2 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 2 V BUS ADC converts -32V to +32V range with 16-bit two s complement output 0 = Channel 3 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 3 V BUS ADC converts -32V to +32V range with 16-bit two s complement output 0 = Channel 4 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 4 V BUS ADC converts -32V to +32V range with 16-bit two s complement output Microchip Technology Inc. DS C-page 43

44 REGISTER 6-12: REFRESH_G COMMAND (ADDRESS 1EH) SEND SEND SEND SEND SEND SEND SEND SEND No Data in this command, Send Byte only bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-0 This command is a SEND Byte, does not contain any data. It is exactly like the REFRESH command but is intended for use with the General Call command. When it is sent to the device, the REFRESH command is executed and the readable accumulator data, readable accumulator count, V BUS, and V SENSE measurements are all refreshed and the internal accumulators values or accumulator count are reset, exactly like the REFRESH command. The master can read the updated data 1 ms after the REFRESH_G command is sent, and anytime after than up until the next REFRESH, REFRESH_G, or REFRESH_V command is sent. REGISTER 6-13: REFRESH_V COMMAND (ADDRESS 1FH) SEND SEND SEND SEND SEND SEND SEND SEND No Data in this command, Send Byte only bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-0 This command is a SEND Byte, does not contain any data. When it is sent to the device, the REFRESH_V command is executed. It is similar to the REFRESH command except the accumulators and accumulator count are not reset. The readable accumulator data, readable accumulator count, V BUS, and V SENSE measurements are all refreshed without affecting the internal accumulators values or accumulator count. The master can read the updated data 1 ms after the REFRESH_V command is sent, and anytime after than up until the next REFRESH, REFRESH_G, or REFRESH_V command is sent. DS C-page Microchip Technology Inc.

45 REGISTER 6-14: SLOW (ADDRESS 20H) R-0 R-0 R-0 RW-1 RW-0 RW-1 RW-0 RW-1 SLOW SLOW-LH SLOW_HL R_RISE R_V_RISE R_FALL R_V_FALL POR bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown This register tracks the state of the SLOW pin, tracks transitions on the SLOW pin, and controls the type of limited REFRESH command (if any) that occurs on a SLOW pin transitions. This allows software to monitor the state of the SLOW pin and its transitions over I 2 C even though the SLOW pin is asynchronous to the I 2 C pins and may have a different controller. Note that if a REFRESH and REFRESH_V are both enabled for a certain SLOW pin transition, REFRESH will be executed (REFRESH wins over REFRESH_V). On a transition of the SLOW pin, a limited REFRESH function is executed. These limited REFRESH and REFRESH_V functions update all of the readable results registers. For the limited REFRESH function only, it also reset the accumulators and accumulator count. These are called limited REFRESH and limited REFRESH_V functions because there is no activation of any pending changes to the Control registers. If the SLOW pin is configured to act as an ALERT pin, all of these bits are always 0. The bits are not cleared when read, see the details on each bit for clearing information. SLOW Control and Status Bits bit 7 = 0 bit 7 = 1 bit 6 = 0 bit 6 = 1 bit 5 = 0 bit 5 = 1 bit 4 = 0 bit 4 = 1 bit 3 = 0 bit 3 = 1 bit 2 = 0 bit 2 = 1 bit 1 = 0 bit 1 = 1 The SLOW pin is pulled low externally The SLOW pin is pulled high externally The SLOW pin has not transitioned low to high since the last REFRESH command The SLOW pin has transitioned low to high since the last REFRESH command The bit is reset to 0 by a REFRESH or REFRESH_G command The SLOW pin has not transitioned high to low since the last REFRESH command The SLOW pin has transitioned high to low since the last REFRESH command The bit is reset to 0 by a REFRESH or REFRESH_G command Disables a limited REFRESH function to take place on the rising edge of the SLOW pin Enables a limited REFRESH function to take place on the rising edge of the SLOW pin The bit is not reset automatically, it must be written to be changed. Disables a limited REFRESH_V function to take place on the rising edge of the SLOW pin Enables a limited REFRESH_V function to take place on the rising edge of the SLOW pin The bit is not reset automatically, it must be written to be changed Disables a limited REFRESH function to take place on the falling edge of the SLOW pin Enables a limited REFRESH function to take place on the falling edge of the SLOW pin The bit is not reset automatically, it must be written to be changed Disables a limited REFRESH_V function to take place on the falling edge of the SLOW pin Enables a limited REFRESH_V function to take place on the falling edge of the SLOW pin The bit is not reset automatically, it must be written to be changed POR Status Bit The POR bit is a POR flag, for the purpose of enabling the system designer can clear it after POR, and then monitor it to detect if the device was powered cycled or somehow reset since the POR. If the reset is detected in this manner, any non-default programming can be reprogrammed. bit 0 = 0 bit 0 = 1 This bit has been cleared over I 2 C since the last POR occurred This bit has the POR default value of 1, and has not been cleared since the last reset occurred This bit is only reset by POR Microchip Technology Inc. DS C-page 45

46 REGISTER 6-15: CTRL_ACT REGISTER (ADDRESS 21H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Sample_Rate<1:0> SLEEP SING ALERT_PIN ALERT_CC OVF ALERT OVF bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown This register contains an image of the Control register, 01h. The bits in this register reflect the current active value of these settings, whereas the values in register 01h may have been programmed but not activated by one of the REFRESH commands. This register allows the software to determine the actual active setting. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command (in most cases). However, if the users program a conversion rate change followed by REFRESH, the new conversion rate will not become effective until the current conversion cycle is complete. For example, if the old sample rate was 8 Hz, it will take up to 125 ms before the conversion cycle (and the CTRL_ACT register) are updated. This delay can be variable, depending on where we are in the conversion cycle when the REFRESH command is sent. bit 7-6 Sample_Rate<1:0>: shows the value that is currently active since the most recent REFRESH function was received for programmed sample rate in Normal mode (that is, if SLOW pin is not asserted) 00b = 1024 samples/s 01b = 256 samples/s 10b = 64 samples/s 11b = 8 samples/s bit 5 SLEEP: shows the value that is currently active since the most recent REFRESH function was received for the SLEEP bit. 0 = ACTIVE mode 1 = SLEEP mode, no data conversion bit 4 SING: shows the value that is currently active since the most recent REFRESH function was received for the single shot select bit, SING. 0 = Sequential scan mode 1 = Single-shot mode bit 3 ALERT_PIN: shows the value that is currently active since the most recent REFRESH function was received for the ALERT_PIN bit. 0 = Disable the ALERT pin function 1 = Enable the ALERT pin function bit 2 ALERT_CC: shows the value that is currently active since the most recent REFRESH function was received for the ALERT_CC bit. 0 = No ALERT on Conversion Cycle Complete 1 = ALERT function asserted for 5 μs on each completion of the conversion cycle bit 1 OVF ALERT: shows the value that is currently active since the most recent REFRESH function was received for the OVF ALERT bit. 0 = No ALERT if accumulator or accumulator counter overflow has occurred 1 = ALERT pin triggered if accumulator or accumulator counter has overflowed bit 0 OVF: shows the value that is currently active since the most recent REFRESH function was received for the OVF bit. 0 = No accumulator or accumulator counter overflow has occurred 1 = Accumulator or accumulator counter has overflowed DS C-page Microchip Technology Inc.

47 REGISTER 6-16: CHANNEL DIS_ACT (ADDRESS 22H) R-0 R-0 R-0 R-0 U U U U CH1_OFF CH2_OFF CH3_OFF CH4_OFF bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown This register contains an image of the Channel Disable bits in register 1Ch.The bits in this register reflect the value that was activated by the most recent REFRESH function, and is currently active. Whereas the values in register 1Ch may have been programmed but not activated by one of the REFRESH commands, register 22h allows software to determine the actual active setting. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command. bit 7-4 CHn_OFF<7:4>: shows the value that is currently active for these bits. bit 7 0 = CH1 ON. Channel 1 active during conversion cycle 1 = CH1 OFF. Channel 1 inactive during conversion cycle bit 6 0 = CH1 ON. Channel 2 active during conversion cycle 1 = CH1 OFF. Channel 2 inactive during conversion cycle bit 5 0 = CH1 ON. Channel 3 active during conversion cycle 1 = CH1 OFF. Channel 3 inactive during conversion cycle bit 4 0 = CH1 ON. Channel 4 active during conversion cycle 1 = CH1 OFF. Channel 4 inactive during conversion cycle bit 3-0 Not used, always reads 0 REGISTER 6-17: NEG_PWR_ACT (ADDRESS 23H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CH1_BIDI CH2_BIDI CH3_BIDI CH4 BIDI CH1_BIDV CH2_BIDV CH3_BIDV CH4_BIDV bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown This register contains an image of the NEG_PWR register, 1Dh.The bits in this register reflect the current active value of these settings, whereas the values in register 1Dh may have been programmed but not activated by one of the REFRESH commands. This register allows software to determine the actual active setting. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command. bit 7-4 CH1_BIDI<7:4>: these bits show the current active value of the corresponding bits in Register 6-11, NEG_PWR (Address 1Dh). bit 3-0 CH1_BIDV<3:0>: these bits show the current active value of the corresponding bits in Register 6-11, NEG_PWR (Address 1Dh). bit 7 0 = Channel 1 V SENSE ADC converts 0 to +100 mv range with 16-bit straight binary output 1 = Channel 1 V SENSE ADC converts -100 mv to +100 mv range with 16-bit two s complement output bit 6 0 = Channel 2 V SENSE ADC converts 0 to +100 mv range with 16-bit straight binary output 1 = Channel 2 V SENSE ADC converts -100 mv to +100 mv range with 16-bit two s complement output bit 5 0 = Channel 3 V SENSE ADC converts 0 to +100 mv range with 16-bit straight binary output 1 = Channel 3 V SENSE ADC converts -100 mv to +100 mv range with 16-bit two s complement output bit 4 0 = Channel 4 V SENSE ADC converts 0 to +100 mv range with 16-bit straight binary output 1 = Channel 4 V SENSE ADC converts -100 mv to +100 mv range with 16-bit two s complement output Microchip Technology Inc. DS C-page 47

48 REGISTER 6-17: NEG_PWR_ACT (ADDRESS 23H) (CONTINUED) bit 3 bit 2 bit 1 bit 0 0 = Channel 1 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 1 V BUS ADC converts -32V to +32V range with 16-bit two s complement output 0 = Channel 2 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 2 V BUS ADC converts -32V to +32V range with 16-bit two s complement output 0 = Channel 3 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 3 V BUS ADC converts -32V to +32V range with 16-bit two s complement output 0 = Channel 4 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 4 V BUS ADC converts -32V to +32V range with 16-bit two s complement output REGISTER 6-18: CTRL_LAT REGISTER (ADDRESS 24H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Sample_Rate<1:0> SLEEP SING ALERT_PIN ALERT_CC OVF ALERT OVF bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown This register contains an image of the Register 6-15 CTRL_ACT Register (Address 21h). The bits in this register reflect the value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). The values in register 01h may have been programmed but not activated by one of the REFRESH commands, and the values in 21h are currently active. This register allows software to determine the actual active setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is held in the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command. bit 7-6 Sample_Rate<1:0>: shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G) 00b = 1024 samples/s 01b = 256 samples/s 10b = 64 samples/s 11b = 8 samples/s bit 5 SLEEP: shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). 0 = Active mode 1 = SLEEP mode, no data conversion bit 4 SING: shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). 0 = Sequential scan mode 1 = Single-shot mode bit 3 ALERT_PIN: the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). 0 = Disable the ALERT pin function 1 = Enable the ALERT pin function bit 2 ALERT_CC: shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G) for the ALERT_CC bit. 0 = No ALERT on Conversion Cycle Complete 1 = ALERT function asserted for 5 μs on each completion of the conversion cycle DS C-page Microchip Technology Inc.

49 REGISTER 6-18: CTRL_LAT REGISTER (ADDRESS 24H) bit 1 bit 0 OVF ALERT: shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G) for the OVF_ALERT bit. 0 = No ALERT if accumulator or accumulator counter overflow has occurred 1 = ALERT pin triggered if accumulator or accumulator counter has overflowed OVF: shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G) for the OVF bit. 0 = No accumulator or accumulator counter overflow has occurred 1 = Accumulator or accumulator counter has overflowed REGISTER 6-19: CHANNEL DIS_LAT (ADDRESS 25H) R-0 R-0 R-0 R-0 U U U U CH1_OFF CH2_OFF CH3_OFF CH4_OFF bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown This register contains an image of the Register 6-16 Channel DIS_ACT (Address 22h).The bits in this register reflect the value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). The values in register 1Ch may have been programmed but not activated by one of the REFRESH commands, and the values in 22h are currently active. This register allows software to determine the actual active setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is held in the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command. bit 7-4 CHn_OFF<7:4>: the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). bit 7 0 = CH1 ON. Channel 1 active during conversion cycle 1 = CH1 OFF. Channel 1 inactive during conversion cycle bit 6 0 = CH1 ON. Channel 2 active during conversion cycle 1 = CH1 OFF. Channel 2 inactive during conversion cycle bit 5 0 = CH1 ON. Channel 3 active during conversion cycle 1 = CH1 OFF. Channel 3 inactive during conversion cycle bit 4 0 = CH1 ON. Channel 4 active during conversion cycle 1 = CH1 OFF. Channel 4 inactive during conversion cycle bit 3-0 Not used, always read Microchip Technology Inc. DS C-page 49

50 REGISTER 6-20: NEG_PWR _LAT (ADDRESS 26H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CH1_BIDI CH2_BIDI CH3_BIDI CH4 BIDI CH1_BIDV CH2_BIDV CH3_BIDV CH4_BIDV bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown This register contains an image of the Register 6-17 NEG_PWR_ACT (Address 23h).The bits in this register reflect the value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). The values in register 1Dh may have been programmed but not activated by one of the REFRESH commands, and the values in 23h are currently active. This register allows software to determine the actual active setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is held in the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command. bit 7-4 CHn_BIDI<7:4>: the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). bit 3-0 CHn_BIDV<3:0>: the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). bit 7 0 = Channel 1 V SENSE ADC converts 0 to +100mV range with 16-bit straight binary output 1 = Channel 1 V SENSE ADC converts -100mV to +100mV range with 16 bit two s complement output bit 6 0 = Channel 2 V SENSE ADC converts 0 to +100mV range with 16-bit straight binary output 1 = Channel 2 V SENSE ADC converts -100mV to +100mV range with 16-bit two s complement output bit 5 0 = Channel 3 V SENSE ADC converts 0 to +100mV range with 16-bit straight binary output 1 = Channel 3 V SENSE ADC converts -100mV to +100mV range with 16-bit two s complement output bit 4 0 = Channel 4 V SENSE ADC converts 0 to +100mV range with 16-bit straight binary output 1 = Channel 4 V SENSE ADC converts -100mV to +100mV range with 16-bit two s complement output bit 3 0 = Channel 1 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 1 V BUS ADC converts -32V to +32V range with 16-bit two s complement output bit 2 0 = Channel 2 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 2 V BUS ADC converts -32V to +32V range with 16-bit two s complement output bit 1 0 = Channel 3 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 3 V BUS ADC converts -32V to +32V range with 16-bit two s complement output bit 0 0 = Channel 4 V BUS ADC converts 0 to +32V range with 16-bit straight binary output 1 = Channel 4 V BUS ADC converts -32V to +32V range with 16-bit two s complement output DS C-page Microchip Technology Inc.

51 REGISTER 6-21: PRODUCT ID REGISTER (ADDRESS FDh) R-0 R-1 R-0 R-1 R-1 R-0 R-1 R-1 PID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-0 PID<7:0>: contain the Product ID for the PAC1932/3/ _1001 for PAC _1010 for PAC _1011 for PAC1934 (Default shown in table directly above) REGISTER 6-22: MANUFACTURER ID REGISTER (ADDRESS FEh) R-0 R-1 R-0 R-1 R-1 R-1 R-0 R-1 MID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-0 MID<7:0>: the Manufacturer ID register identifies Microchip as the manufacturer of the PAC1932/3/4 This value is 5Dh. REGISTER 6-23: REVISION ID REGISTER (ADDRESS FFh) R-0 R-0 R-0 R-0 R-0 R-0 R-1 R-1 RID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = bit is set 0 = Bit is cleared x = Bit is unknown bit 7-0 RID<7:0>: the Revision register identifies the die revision This register reads 03h Microchip Technology Inc. DS C-page 51

52 7.0 PACKAGE DESCRIPTION 7.1 Package Marking Information UQFN Example PAC 1932 JQ^^ e WLCSP-16 Example Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week 01 ) NNN e3 Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS C-page Microchip Technology Inc.