PAC1934. Four Channel DC Power/Energy Monitor with Accumulator. Applications. Features. Description. Package Types

Transcription

1 Four Channel DC Power/Energy Monitor with Accumulator Features High-Side Current Monitor mv full scale range for current sense voltage,16b resolution default setting - Selectable bidirectional current sense capability, 100 mv to +100 mv range, 16-bit two s complement (signed) data format - External sense resistor sets full scale current range - Very low input current simplifies routing Wide Bus Voltage Range for Voltage Monitor - 0V to 32V input common-mode voltage - 16-bit resolution for voltage measurements, 14b are used for power calculations Real Time Auto-Calibration of Offset and Gain Errors for Voltage and Current, No User Adjustment Required 1% Power Measurement Accuracy over a Wide Dynamic Range On-Chip Accumulation of 28-bit Power Results for Energy Measurement - 48-bit power accumulator register for recording accumulated power data - 24 bit Accumulator Count - User programmable sampling rates of 8, 64, 256 and 1024 samples per second - 17 minutes of power data accumulation minimum at 1024 S/s - >36 hours of power data accumulation minimum at 8 S/s 2.7V to 5.5V Supply Operation - Separate V DD I/O pin for digital I/O V capable SMBus and digital I/O - SMBus 3.0 and I 2 C Fast Mode Plus (1Mb/S) SMBus Address - 16 Options, set with Resistor No Input Filters Required ALERT Features that can be Enabled: - ALERT on accumulator overflow - ALERT on Conversion Complete x 2.17 mm WLCSP Package Applications Notebook and Tablet Computing Networking Automotive Cloud, Linux and Server Computing Industrial Linux Applications Description The PAC1934 device is a four-channel energy monitor, with bus voltage monitor and current sense amplifiers that feed high-resolution ADCs. Digital circuitry performs power calculations and energy accumulation. This enables energy monitoring with integration periods from 1 ms up to 36 hours or longer. Bus voltage, sense resistor voltage and accumulated proportional power are stored in registers for retrieval by the system master or Embedded Controller. The sampling rate and energy integration period can be controlled over SMBus or I 2 C. Active channel selection, one-shot measurements and other controls are also configurable by SMBus or I 2 C. The PAC1934 uses real time calibration to minimize offset and gain errors. No input filters are required for this device. Package Types PAC1934 Top View x 2.17 mm WLCSP A B C SENSE2+ SENSE1- SENSE2- SENSE3- V DD I/O ADDRSEL SENSE1+ PWRDN SLOW/ALERT V DD GND SM_CLK D SENSE3+ SENSE4- SENSE4+ SM_DATA For more details, see Table 3-1 and Section Microchip Technology Inc. DS B-page 1

2 Device Block Diagram VDD GND SENSE 1+ VBUS1 SENSE 1- SENSE 2+ SENSE 2- SENSE 3+ SENSE 3- SENSE 4+ SENSE 4- VBUS2 Sense1+ Sense1- Sense2+ Sense2- VBUS3 Sense3+ Sense3- VBUS4 Sense4+ Sense4- Differential VSENS E Amplifier VBUS Buffer/ Divider 16-bit ADC 16-bit ADC ADC/MUX Clocking & Control Calculation and Calibration Accumlator VBUS Registers VSENS E Registers VPOWE R Registers Accumulator Registers Control Registers I 2 C/SMBus VDD I/O SM_CLK SM_DATA SLOW/ALERT PWRDN High Voltage MUX Resistor Decoder ADDRSEL DS B-page Microchip Technology Inc.

3 1.0 ELECTRICAL CHARACTERISTICS 1.1 Electrical Specifications Absolute Maximum Ratings ( ) V DD pin to 6.0V Voltage on SENSE- and SENSE+ pins to 40V Voltage on any other pin to GND...GND 0.3 to +6.0V Voltage between Sense pins ( (SENSE+ SENSE ) ) mv Input current to any pin except V DD...±100 ma Output short-circuit current... Continuous Junction to Ambient ( J-A ) C/W Operating Ambient Temperature Range to +150 C Storage Temperature Range to +150 C ESD Rating all pins HBM V ESD Rating all pins CDM V Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. ESD Protection Diagram (Floating ESD rail) SLOW/ SM_DATA SM_CLK PWRDN ALERT ADDRSEL VDD I/O VDD GND CLAMP CIRCUIT SENSE1+ SENSE2+ SENSE3+ SENSE4+ SENSE1- SENSE2- SENSE3- SENSE4- (~40v breakdown) This diagram represents the ESD protection circuitry on the PAC1934. These pins are allowed to be at 32V if V DD is at zero. The back to back diodes between the Sense+ and Sense pins have 1 kω resistors in series with them Microchip Technology Inc. DS B-page 3

4 TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: Unless otherwise specified, maximum values are at T A = 40 C to +85 C, V DD = 2.7V to 5.5V, V DD I/O = 1.62V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C V DD = V DD I/O = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE ) = 0V Characteristic Symbol Min. Typ. Max. Unit Conditions Power Supply V DD Range V DD V V DD I/O Range V DD I/O V V DD Pin Active Current V DD Pin Active Current Minimum V DD Rise Rate Maximum V DD Rise Rate I DD µa All 4 measurement channels enabled Samples/s I DD SLOW 16 µa 4 channels enabled, 8 Samples/s V DD_RISE_MIN 0.05 V/ms 0 to 5V in 100 ms V DD_RISE 1000 V/ms 0 to 5V in 5 µs V DD Sleep Current I DD_SLEEP 5 µa Sleep State V DD Power-Down I DD_PWRDN 0.1 µa Power-Down State Current V DD I/O Current I DD I/O 2 µa All States Analog Input Characteristics V BUS Voltage Range V BUS 0.2V 32 V Common mode range for SENSE+ and SENSE pins, referenced to ground (negative range not tested in production) V SENSE Differential Input Voltage Range V SENSE_DIF mv SENSE+, SENSE Pin Input Current SENSE+, SENSE Pin Input current V SENSE Measurement Accuracy V SENSE Gain V SENSE_ Accuracy GAIN_ERR V SENSE Offset V BUS_ Accuracy, referenced OFFSET_ERR to input V SENSE Unidirectional Currents V SENSE ADC Resolution V SENSE Full Scale Range V SENSE LSB Step Size I SENSE +, I SENSE µa V SENSE + = V SENSE = 32V (Input current is the combined current for the two pins) I SENSE +, I SENSE µa V SENSE = 6V, V SENSE = 5.9V ±0.2 ±1 ±0.02 ±0.2 ±0.9 % % ±0.1 mv mv At +25 C typical, 40 to +85 C At +25C typical, 40 to +85 C V SENSE_RES 16 Bits Straight Binary for unidirectional currents V SENSE_FSR mv Unidirectional currents V SENSE_LSB 1.5 µv Unidirectional currents V SENSE Bidirectional Currents V SENSE V SENSE_RES 16 bits 16-bit two s complement (signed) ADC Resolution V SENSE Full Scale Range V SENSE_FSR mv Bidirectional currents DS B-page Microchip Technology Inc.

5 TABLE 1-1: DC CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, maximum values are at T A = 40 C to +85 C, V DD = 2.7V to 5.5V, V DD I/O = 1.62V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C V DD = V DD I/O = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE ) = 0V Characteristic Symbol Min. Typ. Max. Unit Conditions V SENSE LSB Step Size V SENSE_LSB 3 µv Bidirectional currents V BUS Measurement Accuracy V BUS Gain Accuracy V BUS_GAIN_ERR ±0.02 ±0.2 V BUS Offset Accuracy, referenced to input V BUS Unipolar Voltages V BUS ADC Resolution V BUS Unipolar Full-Scale Range V BUS_ OFFSET_ERR ±1 ±2 ±0.5 % % LSB LSB At +25 C typical, 40 to +85 C At +25 C typical, 40 to +85 C V BUS_RES 16 bits Straight Binary for unidirectional currents V BUS_ FSR 0 32 V Unipolar voltage V BUS LSB Step Size V BUS_ LSB 488 µv FSR = 32V, 16-bit resolution V BUS Bipolar Voltages V BUS ADC Resolution V BUS_RES 16 bits 16-bit two's complement (signed) numbers are reported for V BUS measurement result V BUS Bipolar Full-Scale Range V BUS_ FSR V Mathematical scaling. Physics limits the negative input voltage to 0.2V V BUS LSB Step Size V BUS_ LSB 976 µv Bipolar voltages 2017 Microchip Technology Inc. DS B-page 5

6 TABLE 1-1: DC CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, maximum values are at T A = 40 C to +85 C, V DD = 2.7V to 5.5V, V DD I/O = 1.62V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C V DD = V DD I/O = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE ) = 0V Characteristic Symbol Min. Typ. Max. Unit Conditions Power Accumulator Accuracy Accumulator Error ACC_Err 0.2 % V SENSE = 97 mv Accumulator Error ACC_Err 0.2 % V SENSE = 10 mv Accumulator Error ACC_Err 1 % V SENSE = 1 mv Accumulator Error ACC_Err 3 % V SENSE = 100 µv Accumulator Error ACC_Err 5 % V SENSE = 50 µv Active Mode Timing Pull-Up Voltage Range Time to First Communications Transition From Sleep State to Start of Conversion Cycle V PULLUP V Pull-up voltage for I 2 C/SMBus pins and digital I/O pins. Set by V DD I/O. t INT_T ms t SLEEP_TO_ACTIVE 3 ms Digital I/O Pins (SM_CLK, SM_DATA, SLOW/ALERT, PWRDN) Input High Voltage V IH V DD I/O V x 0.7 Input Low Voltage V IL V DD I/O V x 0.3 Output Low Voltage V OL 0.4 V Sinking 8 ma for the ALERT pin and 20 ma for the SMCLK pin Leakage Current I LEAK 1 +1 µa DS B-page Microchip Technology Inc.

7 TABLE 1-2: SMBUS MODULE SPECIFICATIONS Electrical Characteristics: Unless otherwise specified, maximum values are at T A = 40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; Typical values are at T A = +25 C, V DD = 3.3V, V BUS = 32V, V SENSE = (SENSE+ SENSE ) = 0V, V DD I/O = 1.62V to 5.5V Characteristic Sym. Min. Typ. Max. Units Conditions SMBus Interface Input Capacitance C IN 4 10 pf Not tested in production SMBus Timing Clock Frequency f SMB MHz No minimum if Time-Out is not enabled. Spike Suppression t SP 0 50 ns Bus Free Time Stop to t BUF 0.5 µs Per SMBus 3.0 Start Hold Time after Repeated Start Condition t HD:STA 0.26 µs Per SMBus 3.0 Repeated Start t SU:STA 0.26 µs Per SMBus 3.0 Condition Setup Time Setup Time: Stop t SU:STO 0.26 µs Per SMBus 3.0 Setup Time: Start t SU:STA 0.26 µs Data Hold Time t HD:DAT 0 µs Data Setup Time t SU:DAT 50 ns Per SMBus 3.0 (Note 1) Clock Low Period t LOW 0.5 µs Per SMBus 3.0 Clock High Period t HIGH µs Clock/Data Fall Time t FALL 120 ns Not tested in production Clock/Data Rise Time t RISE 120 ns Not tested in production Capacitive Load C LOAD 550 pf Per bus line, C LOAD not tested in production SLOW Pin Pulse Width SLOWpw 100 µs Pulses narrower than 100 µs may not be detected Note 1: A device must internally provide a hold time of at least 300 ns for the SM_DATA signal (with respect to the VIH(min) of the SM_CLK signal) to bridge the undefined region of the falling edge of SM_CLK. T LOW T HIGH T HD:STA T SU:STO SMCLK T RISE T FALL T T HD:DAT HD:STA T SU:DA T T SU:STA SMDATA T BUF P S S - Start Condition S P - Stop Condition P FIGURE 1-1: SMBus Timing Microchip Technology Inc. DS B-page 7

8 NOTES: DS B-page Microchip Technology Inc.

9 2.0 TYPICAL OPERATING CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, maximum values are at T A = 40 C to +85 C, V DD = 2.7V to 5.5V, V BUS = 0V to 32V; typical values are at T A = +25 C, V DD = 3.3V, V BUS = 3.3V, V SENSE = (SENSE+ SENSE ) = 0V, V DD I/O = 1.62 to 5.5V. Error (percent) vDC 25 o C 10uV 100uV 1mV 10mV 100mV Sense Input Voltage Error (percent) vDC -40 o C vDC 0 o C vDC 25 o C vDC 85 o C 5 3.3vDC 125 o C uV 10uV 0.1mV 1mV 10mV 100mV Sense Input Voltage FIGURE 2-1: Input Voltage. V SENSE Error vs. V SENSE FIGURE 2-4: V SENSE Error vs. V SENSE Input Voltage and Temperature % CM3.3v 3.3vDC 25 o C 0.025% CM3.3v 3.3vDC 25 o C Error (%FullScale) % % Error (%FullScale) % % % Sense Input Voltage (mv) % -1mV -0.5mV 0 0.5mV 1mV Sense Input Voltage FIGURE 2-2: V SENSE Error vs. V SENSE Input Voltage Bidirectional Mode. FIGURE 2-5: V SENSE Error vs. V SENSE Input Voltage Bidirectional Mode (Zoom View). 0.05% 0.05% Error (%FullScale) % -0.1% Ch1 3.3vDC -40 o C Ch1 3.3vDC 0 o C Ch1 3.3vDC 25 o C Ch1 3.3vDC 85 o C -0.15% Ch1 3.3vDC 125 o C 0 20mV 40mV 60mV 80mV 100mV Sense Input Voltage Error (%FullScale) 0.025% % CM1v 3.3vDC 25 o C CM3v 3.3vDC 25 o C CM5v 3.3vDC 25 o C CM16v 3.3vDC 25 o C CM32v 3.3vDC 25 o C -0.05% 0 20mV 40mV 60mV 80mV 100mV Sense Input Voltage FIGURE 2-3: V SENSE Error vs. V SENSE Input Voltage vs. Temperature. FIGURE 2-6: V SENSE Error vs. V SENSE and Common Mode Microchip Technology Inc. DS B-page 9

10 Error (percent) vDC 25 o C Error (percent) vDC -40 o C 3.3vDC 0 o C 3.3vDC 25 o C 3.3vDC 85 o C 3.3vDC 125 o C 1mV 10mV 0.1V 1V 10V Input Voltage 0 1mV 10mV 0.1V 1V 10V Input Voltage FIGURE 2-7: Voltage. V BUS Error vs. V BUS Input FIGURE 2-10: V BUS Error vs. V BUS Input Voltage vs. Temperature. 2% 3.3vDC 25 o C 2% Error (percent) 1% 0-1% -2% 10mV 100mV 1V 10V Input Voltage FIGURE 2-8: V BUS Error vs. V BUS Input Voltage (Zoom View). Error (percent) 1% 0 3.3vDC -40 o C 3.3vDC 0 o C -1% 3.3vDC 25 o C 3.3vDC 85 o C 3.3vDC 125 o C -2% 10mV 100mV 1V 10V 32V Input Voltage FIGURE 2-11: V BUS Error vs. V BUS Input Voltage vs. Temperature (Zoom View). 0.05% 3.3vDC 25 o C 0.1% 0 Error (%FullScale) % -0.1% Input Voltage FIGURE 2-9: V BUS Error vs. V BUS Input Voltage. Error (%FullScale) -0.2% -0.4% -0.6% -0.8% 3.3vDC -40 o C 3.3vDC 0 o C 3.3vDC 25 o C 3.3vDC 85 o C 3.3vDC 125 o C -0.5v 0v 0.5v 1v Input Voltage FIGURE 2-12: V BUS Error vs. V BUS Input Voltage vs. Temperature (Bipolar Voltage Mode). DS B-page Microchip Technology Inc.

11 Error (%FullScale) 3.3vDC -40 o C 0.2% 3.3vDC 0 o C 3.3vDC 25 o C 0.1% 3.3vDC 85 o C 3.3vDC 125 o C 0-0.1% -0.2% 0v 5v 10v 15v 20v 25v 30v Input Voltage FIGURE 2-13: V BUS Error vs. V BUS Input Voltage vs. Temperature. DC Offset (LSB's 15b+sign) Temperature ( o C) FIGURE 2-16: Input Offset for V BUS Measurements vs. Temperature. 0 DC Offset (LSB's 15b+sign) Temperature ( o C) FIGURE 2-14: Zero Input Histogram for V BUS (LSBs, 8X Average Results). FIGURE 2-17: Input Offset for V SENSE Measurements vs. Temperature. FIGURE 2-15: Zero Input Histogram for V SENSE (LSBs, 8X Average Results). SMBUS Drive Current (IOL) ma SMBUS Output Voltage (VOL) FIGURE 2-18: vs. V OL. VIO=1.6v VDD=2.6v VIO=5.5v VDD=5.5v I 2 C/SMBus Drive Current 2017 Microchip Technology Inc. DS B-page 11

12 1kSps mode Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Active Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v 16 Sps 256 Sps 1kSps Temperature ( o C) FIGURE 2-19: I DD vs. Temperature and Supply at 1024 Samples/Second. 8 Sps Temperature ( o C) FIGURE 2-22: I DD vs.temperature, V DD, and Sample Rate. 8Sps mode Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Sleep mode Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Temperature ( o C) FIGURE 2-20: I DD in SLOW Mode vs. Temperature and V DD Temperature ( o C) FIGURE 2-23: I DD in SLEEP Mode vs. Temperature and V DD. VIO Current (ua) VDD 2.6v/VIO 1.7v VDD 5.6v/VIO 1.7v VDD 2.6v/VIO 5.6v VDD 5.6v/VIO 5.6v Temperature ( o C) FIGURE 2-21: I DD for V DD I/O pin vs. Temperature and V DD. PowerDown Current (ua) v 2.7v 3.3v 5.0v 5.5v 5.6v Temperature ( o C) FIGURE 2-24: I DD in Power Down Mode vs. Temperature and V DD. DS B-page Microchip Technology Inc.

13 Average Current 1kSps (ua) v CM 1v CM 5v CM 16v CM 32v CM Average Current 1kSps (ua) v 1v 5v 16v 32v Temperature ( o C) FIGURE 2-25: V SENSE Input Current - Active Mode, 1024 Samples/Second Temperature ( o C) FIGURE 2-27: V BUS Input Current - Active Mode, 1024 Samples/Second. Leakage Current (ua) v v 5v v 32v Temperature ( o C) FIGURE 2-26: V BUS Input Leakage Current vs. V DD and Temperature. Leakage Current (ua) v CM 1v CM 5v CM 16v CM 32v CM Temperature ( o C) FIGURE 2-28: V SENSE Input Leakage Current vs. V DD and Temperature Microchip Technology Inc. DS B-page 13

14 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN DESCRIPTIONS PAC1934 WLCSP16 Symbol Pin Type Description A3 SENSE1+ 32V analog in 0-32V range, Connect to supply side of sense resistor A2 SENSE1 32V analog in 0-32V range, Connect to load side of sense resistor A1 SENSE2+ 32V analog in 0-32V range, Connect to supply side of sense resistor B1 SENSE2 32V analog in 0-32V range, Connect to load side of sense resistor D1 SENSE3+ 32V analog in 0-32V range, Connect to supply side of sense resistor C1 SENSE3 32V analog in 0-32V range, Connect to load side of sense resistor D3 SENSE4+ 32V analog in 0-32V range, Connect to supply side of sense resistor D2 SENSE4 32V analog in 0-32V range, Connect to load side of sense resistor B4 GND Ground pin Ground for the IC D4 SM_DATA SMBus data I/O Open drain requires pull-up resistor to V DD I/O C4 SM_CLK SMBus clock Input Clock Input pin A4 V DD Power for IC Positive power supply voltage B2 V DD I/O Sets V IH reference for digital I/O Digital power reference level for digital I/O C2 ADDRSEL Analog I/O pin Address selection for the SMBus Slave address B3 PWRDN Digital input pin Voltage range is set by V DD I/O pin. Active low puts the device in power-down state (all circuitry is powered down including SMBus). C3 SLOW/ALERT Digital I/O pin Voltage range is set by V DD I/O pin. Default function is SLOW, may be programmed to function as ALERT pin (Open Collector when functioning as ALERT, requires pull-up resistor to V DD I/O). 3.1 SenseN+/SenseN (N=1,2,3,4) These two pins form the differential input for measuring voltage across a sense resistor in the application. The positive input (SenseN+) also acts as the input pin for bus voltage. 3.2 Ground (GND) System ground. 3.3 SMBus Data (SM_DATA) This is the bi-directional SMBus data pin. This pin is open drain, and requires a pull-up resistor to V DD I/O. 3.4 SMBus Clock (SM_CLK) This is the SMBus clock input pin. 3.5 Positive Power Supply Voltage (V DD ) Power supply input pin for the device V range, bypass with 100 nf ceramic capacitor to ground near the IC. 3.6 Digital Power Reference Voltage (V DD I/O ) Connect this pin to the power supply voltage for the digital controller driving the SMBus pins and digital input pins for the device, 1.62V-5.5V. Bypass with 100 nf ceramic capacitor to ground near the IC. This pin does not supply power, instead it acts as the V IH reference. 3.7 Address Selection (ADDR_SEL) Connect a resistor from this pin to ground to select SMBus address. 3.8 Enable pin (PWRDN) Power down input pin for the device, active low. 3.9 SLOW/ALERT In default mode, if this pin is forced high, sampling rate is forced to 8 samples/second. When it is forced low, the sampling rate is 1024 samples/second unless a different sample rate has been programmed.this pin may be programmed to act as the ALERT pin, in ALERT mode the pin needs a pull-up resistor to V DD I/O. DS B-page Microchip Technology Inc.

15 4.0 GENERAL DESCRIPTION The PAC1934 is a four-channel, bidirectional, high-side current-sensing device with precision voltage measurement capabilities, DSP for power calculation and a power accumulator. It measures the voltage developed across an external sense resistor (V SENSE ) to represent the high-side current of a battery or voltage regulator. The PAC1934 also measures the SENSE+ pin voltages (V BUS ). Both V BUS and V SENSE are converted to digital results by a 16-bit ADC, and the digital results are multiplied to give V POWER. The V POWER results are accumulated on-chip, which enables energy measurement over the accumulation period. The PAC1934 has an I 2 C/SMBus interface for digital control and reading results. It also has digital supply reference V DD I/O that is to be connected to the same supply as the digital master for the I 2 C/SMBUS, enabling digital I/O voltages as low as 1.62V. A system diagram is shown in Figure 4-1. Sense Resistors V SOURCE 0V 32V Load V SOURCE 0V 32V Load V SOURCE 0V 32V Load V SOURCE 0V 32V Load 2.7V to 5.5V SENSE1+ SENSE2+ SENSE3+ SENSE4+ SENSE1- SENSE2- SENSE3- SENSE4- V DD I/O 1.62V to 5.5V Digital Supply V DD ADDRSEL PAC1934 SM_CLK SM_DATA System Master GND SLOW PWRDN Note: V DD and V DD I/O may be connected together. FIGURE 4-1: PAC1934 System Diagram Microchip Technology Inc. DS B-page 15

16 VDD GND SENSE 1+ VBUS1 SENSE 1- SENSE 2+ SENSE 2- SENSE 3+ SENSE 3- SENSE 4+ SENSE 4- VBUS2 Sense1+ Sense1- Sense2+ Sense2- VBUS3 Sense3+ Sense3- VBUS4 Sense4+ Sense4- Differential VSENS E Amplifier VBUS Buffer/ Divider 16-bit ADC 16-bit ADC ADC/MUX Clocking & Control Calculation and Calibration Accumlator VBUS Registers VSENS E Registers VPOWE R Registers Accumulator Registers Control Registers I 2 C/SMBus VDD I/O SM_CLK SM_DATA SLOW/ALERT PWRDN High Voltage MUX Resistor Decoder ADDRSEL FIGURE 4-2: PAC1934 Functional Block Diagram. FIGURE 4-3: PCB Pattern for Sense Resistor. Figure 4-3 shows the recommended PCB pattern for sense resistor with wide metal for the high-current path. The drawing shows metal, solder paste openings and resistor outline. V SOURCE connects to the +terminal of the high-current path, and the load connects to the terminal of the high-current path. Sense+ and Sense have a Kelvin connection to the current sense resistor to ensure that no metal with high current is included in the V SENSE measurement path. Sense+ and Sense are shown as a differential pair, route them as a differential pair to the Sense inputs at the chip. DS B-page Microchip Technology Inc.

17 4.1 Detailed Description A high-voltage multiplexer connects the input pins to the V BUS and V SENSE amplifiers. The amplifier outputs are sampled simultaneously for each channel, converted by 16 bit ADCs and processed for gain and offset error correction. After each conversion, V BUS and V SENSE are multiplied together to give V POWER. An internal oscillator and digital control signals control the two ADCs and the mux. The mux sequentially connects each channel s amplifiers to the ADC inputs. The PAC1934 measures the source-side voltage, V BUS, and the voltage V SENSE across an external current sense resistor, R SENSE INITIAL OPERATION AND ACTIVE STATE After POR and a start-up sequence, the device is in the ACTIVE state and begins sampling the inputs sequentially. Voltage and current are sampled for all active channels and power is calculated and accumulated. All active channels are sampled at 1024 samples/second by default. Sample rates of 256, 64 or 8 samples/second may be programmed over I 2 C or SMBus. If the SLOW pin is asserted the sample rate is 8 samples per second. For sampling rates lower than 1024 samples/second, the device is in Sleep mode for a portion of the conversion cycle, which results in lower power dissipation. If fewer than four channels are active, power is also reduced. To read accumulator data and reset the accumulators, the REFRESH command is used. To read the voltage, current, power and accumulator data without resetting the accumulators, the REFRESH_V command is used. Changes to the control register (01h) are activated by sending either REFRESH or REFRESH_V. When a new value is written to the Control Register (01h), the new values take effect at the end of the next round-robin sampling cycle following the next REFRESH or REFRESH_V command REFRESH COMMAND The master sends the REFRESH command after changing the Control Register and/or before reading accumulator data from the device. The master controls the accumulation period in this manner. The readable registers for the V BUS, V SENSE, Power, accumulator outputs and accumulator count are updated by the REFRESH command and the values will be static until the next REFRESH command. These readable registers will be stable within 1 ms from sending the REFRESH command, and may be read by the master at any time up until the next REFRESH command is sent. The internal accumulator values and accumulator count will be reset by the REFRESH command, but the sampling of the inputs, data conversion and power integration is not interrupted and will continue as determined by the settings in the control register. Changes written to the control and configuration registers take effect 1 ms after a REFRESH command is sent. Any new commands written within this 1 ms window will be ignored and NACKed to indicate that they are ignored. The values for V BUS and V SENSE measurement results and Power calculation results respond to the REFRESH command in the same fashion as the accumulators and accumulator count. The readable registers will be stable within 1 ms from sending the REFRESH command and may be read by the master at any time. The internal values continue to be updated according to the sampling plan determined by the settings in the CONTROL register. The results that are sent to the readable registers for V BUS, V SENSE and Power are the values from the most recent complete conversion cycle. See Register 6-1 REFRESH Command (Address 00h) REFRESH_G COMMAND The REFRESH_G is identical in every respect to the REFRESH command, but it is used with the I 2 C General Call address ( ). This allows the system to issue a REFRESH command to all of the PAC1934 devices in the system with a single command. Then the data from this REFRESH_G command may be read device by device to capture a snapshot of the system power and energy for all devices. See Register 6-12 REFRESH_G COMMAND (Address 1Eh). Note that the REFRESH_G command can also be used with a valid Slave Address but in this case only the device with this Slave Address will receive the command. In other words it has the same properties as the REFRESH command with the possibility of being compatible with the I 2 C General Call address REFRESH_V COMMAND If the user wants to read V SENSE and V BUS results, the most recent Power calculation, and/or the accumulator values and count without resetting the accumulators, the REFRESH_V command may be sent. Sending the REFRESH_V command and waiting 1 ms ensures that the V SENSE, V BUS, Power, accumulator and accumulator count values will be stable when read by the master. The sampling of the inputs, data conversion and power integration are not interrupted and will continue as determined by the settings in the CONTROL register. The data in these readable registers will remain stable until the next REFRESH or REFRESH_V command.the internal accumulator values and accumulator count are unaffected by the REFRESH_V command. Note that the REFRESH_V command may also be used to activate changes to the CONTROL register, just like the REFRESH command, except with the 2017 Microchip Technology Inc. DS B-page 17

18 REFRESH_V command changes to the control register will be enacted without resetting the accumulators or accumulator count. See Register 6-13 REFRESH_V COMMAND (Address 1Fh) SLEEP STATE The SLEEP state is a lower power state than the ACTIVE state. While in this state, the device will draw a supply current of I SLEEP from the V DD pin. The device automatically goes to this state between conversion cycles when sampling rates lower than 1,024 samples/second are selected, or if fewer than four channels are active. All digital states and data are retained in the SLEEP state. The device can also be put in the SLEEP state by setting the SLEEP bit followed by a REFRESH or REFRESH_V command, and sampling will resume when the SLEEP bit is cleared followed by a REFRESH of REFRESH_V command. The device does not go into SLEEP state based on any other condition such as static conditions on the SMBus pins. If SMBus Timeout is enabled, it is supported in SLEEP mode or ACTIVE mode POWER-DOWN STATE The Power-Down state is entered by pulling the PWRDN pin low. In this state, all circuits on the chip including the SMBus pins are inactive, and the device is in a state of minimum power dissipation. In the Power-Down state, no data is retained in the chip (neither register configuration nor measurement data). When the PWRDN pin is pulled high, integration, measurement and accumulation will begin using the default register settings, as described in paragraph above. The first measurement data may be requested by a REFRESH or REFRESH_V command 20 ms after the PWRDN pin is pulled high PROGRAMMING THE SAMPLE RATE AND THE SLOW PIN The default sampling rate after power-up is 1024 samples/second. Sampling rates of 256, 64 or 8 samples/second may be programmed in the CTRL REGISTER (Address 01h) (Register 6-2). Any time a new sample rate is programmed, it does not take effect until a REFRESH, RERESH_G, or REFRESH_V command is received. When any of these REFRESH commands are received, any round-robin sampling cycle in progress will complete before the new sampling rate takes effect. If one of these lower sample rates is used, power dissipation is reduced. The round-robin sampling and conversion cycle is exactly the same, but the device goes into the sleep state between conversion cycles. See Section 2.0 Typical Operating Curves. If the SLOW pin is pulled high, the device will sample at eight samples/second. No matter what the programmed sample rate, this new SLOW sample rate will take effect on the next conversion cycle (if a round-robin conversion cycle is in process when the SLOW pin goes high, that conversion cycle will complete before the SLOW sample rate takes effect.) If the device is programmed for Single Shot mode, and the SLOW pin is asserted, the first sampling will begin within 125 ms after the SLOW pin is asserted. If the device is in the SLEEP state, asserting the SLOW pin will not cause sampling to start. Whenever the SLOW pin changes state, a limited REFRESH or REFRESH_V command may be executed by the chip hardware (default is REFRESH). Like any other REFRESH command, this resets the accumulators and accumulator count for a REFRESH command, and updates the readable registers for either REFRESH or REFRESH_V. These are limited REFRESH commands because no programmed changes to the control or status registers take effect (control and status registers means registers 01h, 1Ch, 1Dh, and 20h-26h). The readable registers are stable with the new values within 1 ms of the SLOW pin transition. The SLOW register enables selection of REFRESH or REFRESH_V on the SLOW pin transitions, which allows this function to be disabled for either edge, and also tracks both the state of the SLOW pin and transitions on the SLOW pin. See Register 6-14, SLOW (Address 20h). This is the default functionality of the SLOW pin, but it may be reconfigured to function as an ALERT pin (see paragraph Section 4.4 ALERT Functionality ). If the SLOW pin is configured to serve as an ALERT pin, the slower sampling rate of eight samples/second is only available by programming the CONTROL register 01h. 4.2 Conversion Cycles A conversion cycle for the device consists of analog to digital conversion being complete for all channels (including the real-time calibration that is part of each conversion cycle). Immediately following the data conversion, the power results are calculated for that channel and the power value is added to the accumulator. Averaged values for V SENSE and V BUS are also updated internally as part of each conversion cycle. Data conversion and processing is performed for each active channel in sequential fashion until all active channels have been converted, completing the conversion cycle for the device. The sequential sampling of each channel, along with the calculation time and any sleep time needed to set the overall sampling rate, is referred to as a round-robin sampling period. DS B-page Microchip Technology Inc.

19 4.3 Conversion Cycle Controls REDUCING THE NUMBER OF CHANNELS TO BE SAMPLED Program Register 6-10 CHANNEL_DIS and SMBus (Address 1Ch) to reduce the number of channels that are active. The sample rate is unaffected, but power dissipation is reduced if some channels are disabled. Any or all channels may be disabled; if all channels are disabled, the device goes into sleep mode SINGLE SHOT MODE The Control register also allows the device to operate in Single Shot mode. In Single Shot mode, all active channels will sample and convert once, followed by results being calculated. The accumulator and accumulator count operate the same as for continuous conversion mode, accumulating each single shot power calculation and incrementing the accumulator count. The conversion cycle will start when the REFRESH command (or REFRESH_V or REFRESH_G) is sent. After the single shot measurements and calculations are complete, the device will go into SLEEP mode. A REFRESH, REFRESH_G or REFRESH_V command may be sent to read the data. The user needs to wait 3 ms after the REFRESH command before commanding another Single Shot conversion by means of sending one of the REFRESH commands. This is because a 1 ms delay is required between Refresh commands, and coming out of Sleep requires 2 ms ALERT AFTER COMPLETE CONVERSION The Register 6-2 has a bit ALERT_CC that can be used to enable the ALERT_CC function. If this bit is set, the ALERT pin will go low for 5 μs after each complete conversion cycle is complete ALERT ON ACCUMULATOR OVERFLOW If the ALERT function is enabled, and any of the accumulators or the accumulator count overflows, the ALERT pin may be used to notify the system. To enable this trigger for the ALERT pin, bit 1 in the CTRL REGISTER (Address 01h) Register 6-2 must be set. Note that the OVF bit in the CTRL REGISTER (Address 01h) Register 6-2, will be set when these overflows occur CLEARING ALERT AND OVF When the ALERT function has been tripped by accumulator or accumulator count overflow, it will remain asserted until a REFRESH command is received. REFRESH_G will also clear the OVF bit and the ALERT function, but REFRESH_V will not. 4.4 ALERT Functionality The ALERT functionality can serve two purposes: to notify the system that a conversion cycle for all active channels is complete, or to notify the system that the accumulator or accumulator count has overflowed USING THE ALERT FUNCTION To use the ALERT function, configure the SLOW pin to function as ALERT using the Register 6-2. For this configuration, the ALERT pin must have a pull-up to V DD I/O (it will function as an open drain output). If a pull-up resistor is attached to the pin for ALERT functionality, the device will power up in SLOW mode. Any of the four sample rates can be programmed using the CTRL Register 01h. The ALERT function for Accumulator Overflow can also be used without reconfiguring the SLOW pin, by monitoring the OVF bit in the CTRL REGISTER (Address 01h) Register Microchip Technology Inc. DS B-page 19

20 4.5 Voltage Measurement The VBUS voltage for each channel is measured by the SENSE+ pin for each channel. A high-voltage multiplexer is connected to each SENSE+ pin, and the multiplexer sequentially connects each SENSE+ input to and ADC for conversion. The result is stored in a 16-bit V BUS results register and the 14 MSBs are multiplied by the V SENSE number for the V POWER results value. The V POWER results are accumulated in the accumulator. Full-Scale Voltage (FSV) is 32V by default. The device may be programmed for bipolar V BUS measurements. in this bipolar mode, the mathematical range for negative V BUS numbers is 32V, the actual range is limited to about 200mV due to physical factors. This bipolar capability for V BUS enables accurate offset measurement and correction. For bipolar operation, the 16-bit V BUS result is a twos complement (signed) number. The measured voltage at SENSE+ can be calculated using Equation 4-1. EQUATION 4-1: Where: V Source BUS VOLTAGE = 32V V BUS Denominator V SOURCE = The measured voltage on the SENSE+ pin V BUS = The value read from the V BUS Results Registers Denominator = 2 16 for unipolar measurements = 2 15 for bipolar measurements 4.6 Current Measurement The PAC1934 includes high-side current sensing circuits. These circuits measure the voltage (V SENSE ) induced across a fixed external current sense resistor (R SENSE ) and store the voltage as a 16-bit number in the V SENSE Results registers. The PAC1934 current sensing operates with a Full-Scale Range (FSR) of 100 mv in unidirectional mode (default). When sensing unidirectional currents (the default mode), the ADC results are presented in straight binary format. For bidirectional current sensing, the ADC results are in two s complement (signed) format. For bipolar current measurements, the range is ±100 mv, but use FSR = 100 mv in the equations that follow. For best accuracy on current values near zero, it is recommended to use the bidirectional current mode and 8x average current results. 4.7 Selecting R SENSE Values R SENSE can easily be calculated if you know the maximum current you want to sense, as shown in Equation 4-2. Consider that you may need to select a value for IMax that includes current peaks well beyond your nominal current. EQUATION 4-2: Where: CALCULATING R SENSE Full-Scale Current (FSC) can be calculated from Equation 4-3. EQUATION 4-3: FULL-SCALE CURRENT FSC = mv R SENSE Where: The actual current through R SENSE can then be calculated using Equation 4-4. EQUATION 4-4: Rsense = FSR Imax FSR = Full Scale V SENSE voltage input R SENSE = External R SENSE resistor value IMax = Maximum current to measure FSC = Full-scale current R SENSE = External sense resistor value Where: I SENSE = FSC SENSE CURRENT V SENSE Denominator I SENSE = Actual bus current FSC = Full-scale current value (from Equation 4-3) V SENSE = The value read from the V SENSE Results Registers Denominator = 2 16 for unipolar measurements = 2 15 for bipolar measurements DS B-page Microchip Technology Inc.

21 4.8 ADC Measurements, Offset, and 8x Averaging The PAC1934 is primarily desired for energy measurements where many power readings are accumulated. This is inherently an averaging process. Individual voltage and current measurements can also benefit from averaging to reduce noise and offset. Averaged values are internally calculated for V BUS and V SENSE, with a rolling average of the most recent eight values present in the VBUSn_AVG (Register 6-7) and VSENSEn_AVG (Register 6-6) registers. The average is updated internally after every conversion cycle. The readable registers are updated with REFRESH, REFRESH_V, or REFRESH_G commands like all the other readable results registers. These averaged results should be used for the most accurate, lowest noise and lowest offset measurements. The ADC channels use a special offset canceling technique. If the user observes the unaveraged results for near-zero values of V BUS and V SENSE, they may observe a cyclical pattern of offset variation. The user may think this is noise, but in fact it is due to internal circuitry switching through different permutations of offset cancellation circuitry. This small variation in unaveraged offset is canceled in the 8x averaged result. It is also canceled in the Power Accumulator results. The overall effect is offset that is consistently very close to zero LSB over supply and temperature variations. The offset canceling technique is illustrated in Figure 4-4. It is very difficult to accurately observe, as it is a challenge to read the data from every conversion cycle. The effect of capturing data points at a rate that does not correspond exactly to the internal sampling rate of the PAC1934 can make these permutations appear less periodic and deterministic than they are inside the chip. The data conversion uses one of the permute positions 1-4 for each input on each conversion, cycling through all four permutations in four conversions. When averaged the Permute Enabled result shown below is realized, evenly distributed around zero. FIGURE 4-4: Illustration of the Four Permute Combinations that the ADC Cycles through and the Resulting Low Average Offset. Each Bin Represents One Code. Results from both the V BUS and V SENSE ADCs are 17b two's complement (signed) internally. There is an additional bit of resolution that is not accessible from the results register. The NEG_PWR (Address 1Dh) register determines whether the conversion results are reported in the readable registers as unipolar or bipolar numbers. Using bipolar numbers can give more accurate results for very small numbers that may actually be negative for some readings, in addition to measuring bidirectional currents (charging/discharging) and voltages that can dip below ground. Averaged values are also calculated for V BUS and V SENSE. A rolling average of the most recent eight values is present in the VBUSn_AVG (Register 6-7) and VSENSEn_AVG (Register 6-6) registers. These registers require eight conversion cycles after POR before they represent an accurate value, they are updated after every conversion cycle. The readable registers are updated with REFRESH, REFRESH_V or REFRESH_G commands like all the other readable results registers Microchip Technology Inc. DS B-page 21

22 4.9 Power and Energy EQUATION 4-8: ENERGY CALCULATION The Full-Scale Range for Power depends on the external sense resistor used, as shown in Equation 4-5. Energy = Vaccum T PwrFSR Denominator AccCount EQUATION 4-5: Where: PowerFSR POWER FSR CALCULATION = 100 mv R SENSE 32V = 3.2V 2 R SENSE R SENSE = External R SENSE resistor value 100 mv = Full-Scale V SENSE voltage input 32V = Full-Scale V BUS voltage input The device implements Power measurements by multiplying V BUS and the V SENSE to give a result V POWER. V POWER values are used to calculate Proportional Power as shown in Equation 4-6. The Proportional Power is the fractional portion of Power FSR measured in one sample. Bipolar mode is where V BUS is bipolar mode, V BUS is bidirectional mode, or both V BUS and V SENSE are bipolar/bidirectional. Where: Denominator = 2 28 (unipolar mode) = 2 27 (bipolar mode) EQUATION 4-9: ENERGY CALCULATION Where: Energy Vaccum PwrFSR = Denominator fs Denominator = 2 28 (unipolar mode) = 2 27 (bipolar mode) Equation 4-9 shows how to calculate energy using the accumulated power and the sampling rate, f s. EQUATION 4-6: PROPORTIONAL POWER CALCULATION P PROP = Vpower Denominator Where: Denominator = = 2 28 (unipolar mode) 2 27 (bipolar mode) To calculate the actual power from the Proportional Power, multiply by the Power FSR as shown in Equation 4-7. This Actual Power number is the power measured in one sample. EQUATION 4-7: POWER CALCULATION P actual = PowerFSR P PROP These V POWER results are digitally accumulated on chip, and stored in the VACCUM registers. The energy calculation equations 4-8 and 4-9 use a different denominator term depending on unipolar or bipolar mode. Bipolar mode for energy applies when bipolar/bidirectional mode is used for V BUS and/or V SENSE. Equation 4-8 shows how to realize this using the Accumulator results, Accumulator count and the accumulation period, T. In this equation, T must be known from a system clock time stamp or other accurate indicator of the total accumulation period. DS B-page Microchip Technology Inc.

23 4.9.1 ADDITIONAL ACCUMULATOR INFORMATION The math for the Power calculation and accumulation inside the chip is always done in two's complement math, no matter what the user sets the output registers to show. V BUS and V SENSE are 17-bit two's complement (signed) numbers internally. V POWER is the product of V SENSE multiplied by the 14 MSBs of V BUS, and this is a 31 bit two's complement result (signed) internally. In some cases this results in a Power result that is not identical to the product of the V BUS results register multiplied by the V SENSE register. However, the Power result from the Power results register is more accurate than the product of the V BUS register multiplied by the V SENSE register in these cases, as explained below. If V SENSE and V BUS are both programmed to be unsigned (unipolar) in register NEG_PWR (Address 1Dh), 16b without sign are exported to V BUS and V SENSE results registers. If V BUS is programmed to be signed (bipolar) in Register 6-11 NEG_PWR (Address 1Dh), the corresponding data is truncated to 16-bit two's complement (signed) for the readable results register. If V SENSE is programmed to be signed (bipolar) in register NEG_PWR (Address 1Dh), the corresponding results register value is truncated to 16-bit two's complement (signed), but the power calculation uses 17-bit two's complement (signed). Therefore, a mismatch is possible between an externally calculated power value (V BUS times V SENSE ) and the actual power value calculated internally to the chip. The internally calculated (and accumulated) value is more accurate than the externally calculated value in every case. The continuous power integration periods (also called the energy accumulation period) can range from ~1ms to many hours, depending on the number of samples per second selected via SMBus. The number of samples is limited by the size of the Accumulator Count Register to 16,777,216 (2 24 ). This count corresponds to about 273 minutes at 1024 samples/second, or 582 hours at eight samples/second. This Accumulator Count can overflow, and it will not reset when it overflows. When the accumulation registers reach their maximum value, this is called accumulator overflow. The accumulator outputs remain at their maximum value; they do not roll over. The user can calculate the worst-case time to roll over and read them at or before that time or use the built in ALERT functions to detect rollover and read them at that time. Worst-case accumulator overflow time can be calculated assuming that every measurement that is accumulated is a full-scale number. Since the power numbers are 28 bits, and the accumulator is 48 bits, 2 20 samples can be accumulated before overflow if they are all full-scale values. For most applications, they will not all be full-scale numbers; this is especially true if V BUS is not 32V. If V BUS is a lower number, the maximum number of full-scale samples that can be accumulated is scaled by 32V/V BUS. This limitation can limit the accumulation period before overflow to 17 minutes at 1024 samples/second, or 36 hours at eight samples/second, if most values are near full-scale. The Accumulator Count limit described above will still limit the total number of samples to Microchip Technology Inc. DS B-page 23

24 5.0 SMBUS AND I 2 C COMMUNICATIONS PROTOCOL The PAC1934 device communicates over a two-wire bus with a controller using SMBus or I 2 C serial communication protocol. A detailed timing diagram is shown in Figure 1-1. Stretching of the SMCLK signal is supported; however, the PAC1934 will not stretch the clock signal. 5.1 I 2 C/SMBus Addressing and Control Bits SMBUS ADDRESS AND RD / WR BIT The SMBus Address Byte consists of the 7-bit slave address followed by a 1-bit RD / WR indicator. If this RD / WR bit is a logic 0, the SMBus master is writing data to the slave device. If this RD / WR bit is a logic 1, the SMBus master is reading data from the slave device. The PAC1934 I 2 C/SMBus address is determined by a single pull-down resistor connected between ground and the ADDRSEL pin as shown in Table 5-1. The chip translates the resistor value into an address on power-up, and the value is latched until another power-up event takes place. The address cannot be changed on the fly SMBUS DATA BYTES All SMBus data bytes are sent most significant bit first and composed of 8 bits of information. TABLE 5-1: ADDRESS SELECT RESISTOR RESISTOR (1%) SMBUS ADDRESS 0 (Tie to GND) 0010_000(r/w) _001(r/w) _010(r/w) 1, _011(r/w) 2, _100(r/w) 3, _101(r/w) 5, _110(r/w) 8, _111(r/w) 13, _000(r/w) 21, _001(r/w) 34, _010(r/w) 54, _011(r/w) 88, _100(r/w) 140, _101(r/w) 226, _110(r/w) Tie to V DD 0011_111(r/w) SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus data line from a logic 1 state to a logic 0 state while the SMBus Clock line is in a logic 1 state SMBUS ACK AND NACK BITS The SMBus slave will ACK (acknowledge) all data bytes that it receives. This is done by the slave device pulling the SMBus data line low after the eighth bit of each byte that is transmitted SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus data line from a logic 0 state to a logic 1 state while the SMBus clock line is in a logic 1 state. When the PAC1934 detects an SMBus Stop bit, and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications. DS B-page Microchip Technology Inc.

25 5.2 SMBus Time-Out The PAC1934 can support the SMBus Time-Out functionality. This functionality is disabled by default, and can be enabled by writing to the TIMEOUT bit (see Register 6-10: CHANNEL_DIS and SMBus (Address 1Ch). If Time-Out is enabled and the clock is held at logic 0 for t TIMEOUT = ms, the device will time-out and reset the SMBus interface. Communication is restored with a start condition. 5.3 SMBus and I 2 C Compatibility The PAC1934 is compatible with SMBus MHz class and I 2 C Fast-mode Plus. The major differences between SMBus and I 2 C devices are highlighted here. For more information, refer to the SMBus 3.0 and I 2 C specifications. 1. If Time-Out function is enabled, the minimum frequency for SMBus communications is 10 khz. If Time-Out function is disabled (default condition), then there is no minimum frequency for SMBus communications. 2. If SMBus Time-Out is enabled in Register 6-10: CHANNEL_DIS and SMBus (Address 1Ch),the SMBus slave protocol will reset if the clock is held at a logic 0 for t TIMEOUT. I 2 C does not have a time-out, this is the default condition. 3. I 2 C devices do not support the Alert Response Address functionality (which is optional for SMBus).The PAC1934 does not support the Alert Response Address functionality; instead, the ALERT is a GPIO pin that may be monitored by the master or Embedded Controller. 4. I 2 C devices support Block Read and Block Write differently. I 2 C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol for Block Read and Block Write requires that an additional data byte indicating number of bytes to read/write is transmitted. PAC1934 devices support the I 2 C protocol for Block Read by default (no byte count information is sent). If the Byte Count bit is set (see Register 6-10: CHANNEL_DIS and SMBus (Address 1Ch), it will be sent as the first data byte in response to the Block Read command, per SMBus protocol. 5.4 I 2 C/SMBus Protocols The PAC1934 supports Write Byte, Read Byte, Block Read, Send Byte and Receive Byte as valid protocols. It will not respond to the Alert Response Address protocol. It will respond to the I 2 C General Call Address. All of the protocol charts listed below use the convention in Table 5-2. TABLE 5-2: PROTOCOL FORMAT Data Sent to Device Data Sent to the Master # of bits sent # of bits sent 5.5 Auto-Incrementing Pointer The PAC1934 has an auto-incrementing address pointer. The pointer has two loops for auto-incrementing, a READ loop and a WRITE loop. The READ loop includes all of the readable registers all of the configuration and control registers, the results registers, and the Product ID, Manufacturer ID and Revision ID registers. The WRITE loop includes only the writable control and configuration registers. Neither loop includes the REFRESH commands. The READ loop will skip inactive channels, if some channels have been disabled. This automatic channel skipping feature can be disabled by setting the NO SKIP bit in Register 6-10: CHANNEL_DIS and SMBus (Address 1Ch). If the user elects to read disabled channels, they will return FFh and the register address will by NACKed. See Figure 5-1 below for a graphic representation Microchip Technology Inc. DS B-page 25