Technical Customer Documentation SMB455 / 465

Transcription

1 Page 0/44 Document History and Modifications Rev. N Chapter Description / Changes Name Date 0.1 First Issue Sd Chapter 6.10: Update Register Table Sd Chapter 6.4.2: New partitioning of text for WR_GRANGE - Chapter 2.4: Proposal for application schematic - Chapter 0: Update Table of contents - Chapter 5.3.5: Update resistance tolerance for digitals pins - Chapter 2.5.3: Update transfer function for FIR filter - Chapter 6.5: Additional description of HE failure detection - Chapter 6.6.8: Wrap around counter frequency Update of Register Table New partitioning of text for WR_GRANGE Text update regarding external components Update transfer function for FIR filter Noise tolerances included Non-Linearity included Sd Update of tolerance values for sensitivity, zero-g offset, selftest, noise Update of description for DEVSTAT1_REG = 4 Update of timing parameters Sd Änderungsnummer 1039 R AE/ESE3 AE/ESE AE/SCS RtP1/QMM Date Signature Signed: Offenberg Signed: Finkbeiner Signed: Westbeld Signed: Nieder

2 Page 1/44 Single-Channel/Dual-Channel Accelerometer for Airbag Applications SMB455/465 with open SPI Protocol General Use

3 Page 2/44 0. Table of contents 1. Introduction 2. Device Options 2.1. General Description of the Sensor Family Schematic Drawing Theory of Operation 2.2. Dual axis block diagram 2.3. Single axis block diagram 2.4. Application Hint / External Components 2.5. Description of Block Diagram Δ/Σ Converter Decimation Filter FIR Filter (Output) Sensitivity Calibration Offset Cancellation Linear interpolation State Machine & On-Chip Oscillator Signal delays Arming Pin EEPROM 3. Power on phase and initialization 3.1. Self Test 4. Physical Characterization 4.1. Size and Geometry (mechanical drawing, all dimensions in mm) 4.2. Output Signal Orientation Sensing Direction Sensor Signal orientation front crash Signal orientation side crash 4.3. Marking Marking on package Electronic Serial No. (48bit serial number) 4.4. Pin-out and Pin Function 5. Characteristics 5.1. Absolute Maximum Ratings 5.2. Mechanical Characteristics 5.3. Electrical and Sensitivity Parameters Characteristics g range g range g range g range Common parameters (for 35g, 50g and 70g ranges, 25g range tbd) 6. Interface Description 6.1. Introduction 6.2. Communication General Instruction Format 6.3. Acceleration commands Function of SI bits for acceleration commands Function of SO bits for acceleration commands 6.4. Non acceleration commands Range selection

4 Page 3/ Command WR_GRANGE Command RD_GRANGE EOI bit in Device Control Register Offset cancellation 6.5. Error Management Error management for acceleration commands Error management for non acceleration commands 6.6. SPI Instruction Set RD_DEVICE_ID RD_REVISION_ID RD_DEVSTAT1_REG RD_DEVSTAT2_REG RD_SENSOR_DATA WR_DEVCTL RD_DEVCTL RD_READCNT Electrical serial number 6.7. Timing Parameters 6.8. Recommendations 6.9. Internal Counter Register Table 7. Qualification 7.1. Life Expectancy 7.2. Solderprofile leadfree 7.3. Whisker test - for galvanic pure tin surface (not soldered on a PCB) 7.4. X-Ray Inspection 7.5. Washability 7.6. Moulding and Varnishing/Coating 7.7. Handling Instruction 7.8. Leadfree 7.9. Customer key parameters 8. Qualification Plan 9. Technology Information

5 Page 4/44 1. Introduction The SMB455/465 sensor is designed for crash sensing in automotive airbag applications. The SMB455/465 sensor is a in-plane sensor with a measurement range of 25/35/50/70g via g-range SPI command. The sensor provides acceleration data for evaluation by a microcontroller. The digital SPI interface allows bidirectional data transmission. Sensor Type Axis Range Bosch Part N Comment SMB455 X 25/35/50/70g SMB465 X/Y 25/35/50/70g Main features of the sensors are: Digital output with 10bit resolution. Interface: SPI (16bit, 8MHz, global open SPI protocol). On chip 1bit / -ADC. Sampling rate khz Full scale measurement range 25/35/50/70g for both channels. Full self test capability; triggerable positive / negative test response. Fast/slow on-chip offset adjustment during power-on stage/operating mode On-chip digital-lowpass-filter with an corner frequency of 378Hz. Output independent of power supply voltage (non-ratiometric output). 0g output = 0 LSB. Internal error monitoring function. Standard SMD SOIC14n-package. Extended Automotive Temperature Range ( C). 48 bit serial number

6 Page 5/44 2. Device Options Component Guaranteed Comment Name g Range SMB455 ±25g Single axis sensor SMB455 ±35g Single axis sensor SMB455 ±50g Single axis sensor SMB455 ±70g Single axis sensor SMB465 ±35g / ±35g Dual axis sensor SMB465 ±35g / ±50g Dual axis sensor SMB465 ±35g / ±70g Dual axis sensor SMB465 ±50g / ±35g Dual axis sensor SMB465 ±50g / ±50g Dual axis sensor SMB465 ±50g / ±70g Dual axis sensor SMB465 ±70g / ±35g Dual axis sensor SMB465 ±70g / ±50g Dual axis sensor SMB465 ±70g / ±70g Dual axis sensor SMB465 ±25g / ±25g Dual axis sensor SMB465 ±25g / ±35g Dual axis sensor SMB465 ±25g / ±50g Dual axis sensor SMB465 ±25g / ±70g Dual axis sensor SMB465 ±35g / ±25g Dual axis sensor SMB465 ±50g / ±25g Dual axis sensor SMB465 ±70g / ±25g Dual axis sensor Note: SMB455/465 are designed for g-ranges of 25g/35g/50g/70g. For SMB465 all range combinations are selectable. For SMB455 the single channel sensing element CMB457 (70g), for SMB465 the dual channel sensing element CMB467 (70g) are used.

7 Page 6/ General Description of the Sensor Family Schematic Drawing X/Y Comb Structures 14 8 SOIC Plastic Housing ASIC 1 7 The sensors consist of a micromachined sensor chip and an evaluation ASIC both packaged into a surface mountable standard SOIC14 narrow package Theory of Operation Micromachined Sensor Chip On the sensor chip, silicon surface micro-machined comb structures are used as capacitive accelerometers. Each comb structure forms a differential capacitor, consisting of a free-movable seismic mass suspended by silicon spring bars, and fixed counter electrodes. The seismic mass deflects due to an acceleration along the sensing axis. This deflection results in a capacitance change which is evaluated by the ASIC. The sensor uses micro-machined structures on the surface of the sensor chip which are protected and hermetically sealed by a micro-machined silicon cap. ASIC The evaluation ASIC, transforms the capacitance change of the sensor elements into a digital bit stream by a ΣΔ-converter. The sample rate is reduced and formed into a parallel bit word by a digital decimation filter and filtered by a digital FIR filter for final low pass filtering. Bi-directional data transmission with the SMB465/SMB455 using the SPI interface allows to read acceleration data, select the sensitivity ("g-range") and control the offset adjustment and self test modes. The device provides an on-chip, non programmable ID containing general ASIC data.

8 Page 7/ Dual axis block diagram

9 Page 8/ Single axis block diagram

10 Page 9/ Application Hint / External Components SGND 1 14 SGND DNC DNC RESET AP VDDA AGND C2 C3 C1 DGND VDDD CS SCK S SI 7 8 Denom. Used for Parameters Value Tolerance C1 Decoupling VDDD 16V 100nF 10% C2 Decoupling VDDA 16V 100nF 10% C3 Decoupling VDDA 16V 100nF 10% The maximum value for a single blocking capacitor on the supply lines VDDA and VDDD is 100nF. For FMEA reasons and for best performance it is possible to use two or more capacitors in a parallel connection between VDDA-AGND and between VDDD-DGND (connected as short as possible). The characterisation, qualification and product release has been done with the above described application schematic. When designing the PCB the following information shall be considered by the customer: 1. The positioning of the external components, i.e. the layout of the printed-circuit board, can affect some parameters such as EMC performance or noise. 2. The capacitor values of the external components can affect some parameters such as EMC performance or noise. 3. The customer shall ensure that the sensor signals are correctly recognised and interpreted from the receiver ASIC and/or microcontroller in the application including external components 2.5 Description of Block Diagram Δ/Σ Converter The Δ/Σ converter converts differential capacitance change in the micromachined sensor element, corresponding to an acceleration in the sensing axis, is converted into a digital serial bit stream by a Δ/Σ converter at a rate of fosc/16 (~125kHz), where f OSC is the frequency of the system clock Decimation Filter

11 Page 10/44 The decimation filter reduces the sample rate from 125 khz to khz. It is a third-order filter with the following transfer function: 3 H(z) = 1 /16 * z 1 - z FIR Filter (Output) The complete transfer function of decimation and FIR filter compared to a 3 rd order Bessel filter is shown in the diagramm below. The -3dB corner frequency of the complete filter is 378 Hz. For the final low pass filtering, a 14Tap symmetrical FIR filter with a data rate of 7,8125 khz is used. H(z) = (b0 + b1*z^-1 + b2*z^ b13*z^-13) / (b0 + b1 + + b13) The realized coefficients converted to integer are as follows: 9, 25, 52, 87, 125, 157, 176, 176, 157, 125, 87, 52, 25, 9 To get the real value of the coefficients, they have to be multiplied with 2-10.

12 Page 11/ Sensitivity Calibration An adjustable gain amplifier stage is used for sensitivity calibration during the production process. The gain amplifier stage is been adjusted with bits #57-63 for channel x and bits #66-72 for channel y Offset Cancellation The SMB465/SMB455 provides on-chip offset cancellation for each channel to enable automatic offset cancellation for the 0g output level. The offset cancellation will eliminate any offset on the output of the SMB465/SMB455 to 0 lsb using an increment/decrement algorithm. The offset cancellation includes two modes: Fast offset cancellation is used after power-on Slow offset cancellation for continuously running offset cancellation in normal mode. Out [lsb] Initial Offset Out Final Offset 0 t t [ms] Start offset Cancellation Schematic representation of the offset cancellation method in the khz cycle

13 Page 12/44 Principle of the offset cancellation. A) For each calculation cycle the output signal is calculated by subtraction of the current accumulated offset value from the current input value. The offset cancellation algorithm is executed with a frequency of khz. B) Offset cancellation has two operation modes: fast offset cancellation and slow offset cancellation. C) In fast cancellation mode an update of the accumulated offset value is performed in every internal execution cycle (128µsec) in the following way: If the output signal is positive, one lsb is added to the accumulated offset value. If the output signal is negative, one lsb is subtracted from the accumulated offset. If the output signal is equal to zero the accumulated offset value will not be changed. D) The accumulated offset value is stored in a 12 bit variable. The offset subtraction is performed in 12 bit precision; the output is presented in 10 bit resolution. The reduction of the data representation from 12 bit to 10 bit is performed after offset subtraction using a rounding operation. E) In each offset update cycle only one update of the accumulated offset value is performed. F) In slow update mode, in each khz update cycle, a slow offset cancellation counter is incremented or decremented according to the method described in C). If the slow offset cancellation counter reaches 1953, the accumulated offset is incremented by one lsb. If this counter reaches lsb, the accumulated offset value is decremented by one lsb. After each decrement/increment of the accumulated offset, the slow offset cancellation counter is reset to zero. As described above, the accumulated offset is stored in a 12 bit variable. G) In fast update mode this can lead to an offset change by one 12 bit lsb every 128 µsec or one 10 bit (output digits) lsb every 512 µsec. This corresponds to a compensation speed of bit lsb per second. In slow update mode the fastest offset change is thus one 12 bit lsb every 128 µsec * 1953 = 0.25 sec or one 10 bit (output digits) lsb every sec. This corresponds to a compensation speed of one 10bit lsb per second. The compensations speeds in fast and slow offset cancellation mode may vary with the precision of the sensor internal clock. In effect for 10 bit resolution, this means a minimum offset cancellation speed of 1855 lsb /sec and a maximum offset cancellation speed of bit lsb/sec. In slow offset cancellation mode, the minimum fastest speed is 0.95 lsb /sec, the maximum fastest speed is 1.05 lsb /sec. H) The step size in physical units [g] is therefore dependent on the selected g-range. I) The initial value for the offset accumulator after power-on and after reset of the sensor- is nominal 'zero'.

14 Page 13/ Linear interpolation State Machine & On-Chip Oscillator The state machine controls the overall behavior of the sensor, including the overall system timing, the initialisation and on-chip self test, the offset regulation and data communication. The system clock signal with a frequency fosc = 2 MHz is generated by an on-chip oscillator. Note that the on-chip signal delay tolerance is determined by the tolerance of the system clock Signal delays 125kHz 125kHz 7,8125kHz 7,8125kHz 2MHz Sensor S/D (8 µs) Dec-Filter FIR + Gain Register Offs. Reg Interpolation (192 µs) ( ) µs (0,5 µs) (128 µs) SPI Register Note: The on-chip signal delay tolerance is determined by the tolerance of the system clock

15 Page 14/ Arming Pin Default status of the Arming Pin AP after reset: Z high impedance. The arming pin output signal AP on Pin 4 is used additionally for the supplier specific function (EC-TEST). The arming pin feature shall be active when the fast offset cancellation is not active. After a request of acceleration data with or without activated selftest, the sensor data of the requested channel are compared to internal range independent arming pin threshold values. If the threshold values are reached, the arming pin has digital output low during the next data frame when the sensor data of the requested channel are being transmitted. Otherwise (also in case of error transmission) the arming pin stays at Z high impedance. For a dual axis sensor this function shall be independently performed both channels 1 and EEPROM The SMB455/465 features a 96bit programmable array (EEPROM) organised in a 24 x 4 bit structure. Address (dec) Function 0-3 band gap calibration data 4-7 oscillator trimming data (MSB) bit serial number 56 lock bit for band gap, oscillator trimming data and 48bit serial number fine gain channel X 64 sensor type (SMB455=1/465=0) 65 lock bit for fine gain channel x and sensor type fine gain channel Y positive self test trimming channel X negative self test trimming channel X positive self test trimming channel Y negative self test trimming channel Y 89 lock bit for fine gain channel Y and for all self test trimming data 90 oscillator trimming data (LSB) CRC / parity check

16 Page 15/44 3. Power on phase and initialization (1) (2) (3) (4) (5) Powerup time Waiting for g-range selection SPI command Sensor ready (Performs fast offset cancellation) Test phase - configure device control register - arming pin active Normal Operation time t 1 t 2 t 3 t 4 Release of RESET WR_DEVCTL OFFC = 1 Command EOI t1 = 1ms maximum Power up time (time after providing supply Voltage on sensor Vs pins and Reset pin) Power up time (time after providing supply voltage on Reset pin after Reset. (Vs always at supply voltage) t2 = application specific due to range selection command by ECU t3 = minimum fast offset cancellation time > 367ms for 25g t4 = customer specific due to commands by ECU t5 = normal operation after setting EOI 3.1 Self Test The SMB465/SMB455 features a bidirectional on-chip self test, controlled by SPI commands. In the self test mode the seismic mass is deflected by an electrostatic force, generating a static self test response. The self test response is defined in the electrical parameters. Thus, it provides full testing of the complete signal evaluation path including the micromachined sensor structure and the evaluation circuit. Out [lsb] positive self test amplitude negative self test amplitude 0 t switch off negative self test set negative self test amplitude switch off positive self test set positive self test The self test is activated by sending the self test command. The self test can be activated separately for both directions (positive and negative direction). The self test response will remain as a static offset on the output

17 Page 16/44 until the self test is deactivated. Any acceleration applied to the sensor with the self test switched on will be seen on the output as a superposition of both acceleration and self test signal. Software hint: An evaluation of the self test should include the measurement of both directions and channels. The self test response should be verified by comparison with the expected value after switching the test signal on and off. The sensor can be directly switched from positive to negative test signal and vice versa. Note: The offset cancellation is stopped as long as the self test is switched on. After switching off the self test, the offset cancellation is reactivated again also automatically (slow mode only). The self test cannot be activated when the offset cancellation is in fast mode.

18 Page 17/44 4. Physical Characterization 4.1 Size and Geometry (mechanical drawing, all dimensions in mm) The sensor is packaged into an SOIC14n housing according to JEDEC standard MS Output Signal Orientation Sensing Direction Sensor 1 14 Ch2 (y-axis) -a +a +a Ch1 (x-axis) -a 7 8 The sensing direction of the SMB465/SMB455 is in plane with the SOIC14 package and thus in plane with the printed circuit board. An acceleration of the device in the "+a"-direction results in a positive output change, a deceleration in this direction (or acceleration to the opposite side) results in a negative output signal. Example : If the sensor is mounted into a car with the edge between Pins 1 and 14 in driving direction, a frontal crash generates a negative change of the channel 1 output signal due to a negative acceleration in X axis direction. 4.3 Marking Marking on package o o o o o pin 1 location marking Bosch logo product number (last five digits of Bosch part No.) date code and strip mark code assembly lot number

19 Page 18/44 Bosch Logo Date Code NNNNN YYWW - AA XXXXXXXXXX Product Number (Last five digits) Strip Mark ASIC and Sensor Wafer (5 + 5 Digits) Pin-out and Pin Function Pin N Assignment Description 1 SGND1 Substrate of sensor (connect to analog GND, AGND) 2 NC No internal connection (do not connect) 3 RESET Power-on-reset (low active) 4 AP Arming pin (low active) 5 DGND Digital ground 6 VDDD Digital supply voltage 7 SO SPI master in slave out 8 SI SPI master out slave in 9 SCK SPI serial clock 10 CS Chip select (low active) 11 AGND Analog ground 12 VDDA Analog supply voltage 13 NC No internal connection (do not connect) 14 SGND2 Substrate of sensor (connect to analog GND, AGND)

20 Page 19/44 5. Characteristics 5.1 Absolute Maximum Ratings Parameter Min. Nominal Max. Unit. Supply Voltage (4.5V)* Volt Operation Temperature C Storage Temperature C Shock Survival unpowered (x,y,z axis) 2000 g Drop Test to concrete floor (random) 1.5 m * 4.5V for maximum 75h 5.3 Electrical and Sensitivity Parameters Characteristics (T A = -40 C to +105 C, V S = V VDDA-AGND = V VDDD-DGND = 3.30V ± 5%, Acceleration = 0g; unless otherwise noted 5.3 Electrical and Sensitivity Parameters Characteristics (T A = -40 C to +105 C, V S = V VDDA-AGND = V VDDD-DGND = 3.30V ± 5%, Acceleration = 0g; unless otherwise noted Test method Noise Peak to Peak: - Linear Interpolator active - external components according to specified circuitry proposal. - sampling rate 2kHz - SPI-frequency 2MHz Test method Noise RMS & zero g output: - Linear Interpolator active - external components according to specified circuitry proposal. - sampling rate 2kHz - SPI-frequency 2MHz g range Parameter Conditions min typ max units Sensor Guaranteed full scale range ±25 g Sensitivity ( non ratiometric sensor) Sensitivity Frequency = 0Hz Including ratiometric error LSB/g Offset ( non ratiometric sensor) Zero-g output Self Test Including ratiometric error Excluding Noise effects LSB Output change Including ratiometric error Tolerance of self test response % Noise Output Noise RMS Value LSB Output Noise (peak to peak) LSB LSB

21 Page 20/ g range Parameter Conditions min typ max units Sensor Guaranteed full scale range ±35 g Sensitivity ( non ratiometric sensor) Sensitivity Offset ( non ratiometric sensor) Zero-g output Frequency = 0Hz Including ratiometric error Including ratiometric error Excluding Noise effects LSB/g % LSB Self Test Output change Including ratiometric error LSB Tolerance of self test response % Noise Output Noise RMS Value LSB Output Noise (peak to peak) LSB g range Parameter Conditions min typ max units Sensor Guaranteed full scale range ±50 g Sensitivity ( non ratiometric sensor) Sensitivity Offset ( non ratiometric sensor) Zero-g output Self Test Output change Frequency = 0Hz Including ratiometric error Including ratiometric error Excluding Noise effects Including ratiometric error LSB/g % LSB LSB Tolerance of self test response % Noise Output Noise RMS Value LSB Output Noise (peak to peak) LSB

22 Page 21/ g range Parameter Conditions min typ max units Sensor Guaranteed full scale range ±70 g Sensitivity ( non ratiometric sensor) Sensitivity Offset ( non ratiometric sensor) Zero-g output Self Test Frequency = 0Hz Including ratiometric error Including ratiometric error Excluding Noise effects LSB/g % LSB Output change Including ratiometric error Tolerance of self test response % Noise Output Noise RMS Value LSB Output Noise (peak to peak) LSB LSB Common parameters (for 35g, 50g and 70g ranges, 25g range tbd) Parameter Conditions min typ max units Sensitivity Cross-axis sensitivity package alignment error % Non linearity of sensitivity 2 % Frequency Response -3dB frequency FIR 14 TAP ( ratiometric to oscillator frequency ) Hz

23 Page 22/44 Parameter Conditions min typ max units Oscillator Frequency 5% 2 5% MHz Supply current x sensor 8 ma xy sensor 8 ma Offset Cancellation fast offset cancellation Max. slow offset cancellation ratiometric to oscillator frequency ratiometric to oscillator frequency LSB/s LSB/s Digital range 10 bits Range for acceleration data LSB Logic output high (SO) Max static current 2 ma Vs-0.6 Vs Volt Logic output low (SO, AP) Max static current 2 ma Volt Logic input high (all inputs) 2.2 Vs Volt Logic input low (all inputs) Volt Input capacity at high impedance SO 10 pf Hysteresis for digital input pins Volt Internal Resistor SO kohm Internal Resistor SI, CS, SCK SI with pull up resistor kohm Internal Resistor Reset Pin Pull down resistor kohm Internal Resistor AP kohm Low voltage detection Power down threshold Volt Power up threshold 2.9 Volt Undervoltage reset time VDDA or VDDD below threshold µs Reset Pin Activation time (low active) 100 ns Arming Pin activation Active range (Positive signal) LSB Inactive range (Pin remains at Z) LSB Active range (Negative signal) LSB Arming pin activation time CS = 1.0V, AP = 0.6V, C(AP) = 70pF 70 ns

24 Page 23/44 6. Interface Description 6.1 Introduction The SMB465/SMB455 provides a bi-directional 3.3V SPI interface for communication with the ECU at a 16 bit data word size. The sensor always operates in slave mode whereas the MCU provides the master function. The interface consists of 4 ports as shown below. (The SPI communication is working from Vs = 3.6 to Power down threshold) SCK Microcontroller CS SI SPI Digital Accelerometer SO Serial clock (SCK) : Input for master clock signal. This clock determines the speed of data transfer and all receiving and sending is done synchronous to this clock. Chip Select (CS) : CS activates the SPI interface. As long as CS is high, the IC does not accept the clock signal or data and the output SO is in high impedance. Whenever CS is in a low logic state, data can be transferred from and to the microcontroller. Serial Input (SI) : Accelerometer data in is latched by the rising edge of SCK. See figure below. Serial Output (SO) : Accelerometer data out is set by the falling edge of SCK. See figure below 6.2 Communication Communication between slave and master is realised by 16 bit data word, MSB first. A so-called off-frame protocol is used, i.e. that each transfer is completed through a sequence of 2 phases. The answer of a given request is sent within the very next frame. The acceleration data for x-axis, y-axis Channel will be frozen at CS down request and submitted during response.

25 Page 24/ SCK /CS MOSI MSB LSB MISO MSB LSB SCK CS SI Request Response SO Phase 1 Phase General Instruction Format The used SPI instructions can be subdivided into two classes, acceleration and non acceleration commands. 6.3 Acceleration commands These commands are used to request sensor data for channel X or Y. The format of these commands is shown below SCK CS MOSI CH1 CH0 SEN MISO 0 CH1 CH0 P ST1 ST0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format of acceleration commands

26 Page 25/44 For acceleration commands the bit SEN is always set to 1. The function of the individual bits of SI and SO are shown in tables below respectively Function of SI bits for acceleration commands Name Bit position Description Definition CH1:CH0 15:14 Channel select Defines sensor channel requested SEN 13 Sensor bit Defines sensor data request (SE = 1), or non sensor data request (SE = 0) Bit CH1 CH0 SEN Data requested SI x-data CH y-data CH Illegal CH Illegal CH Function of SO bits for acceleration commands Name Bit position Description Definition CH1:CH0 14:13 Channel select Identifies sensor channel source for data in D9:D0 ( X or Y ) P 12 Parity Ensures odd parity for bits 15:0 of SO ST1:ST0 11:10 Status Identifies contents in D9:D0 (sensor data, self-test data, error response) D9:D0 9:0 Data Sensor data / self-test data / error response Bit :0 0 CH1 CH0 P ST1 ST0 D9:D0 / error response Device status Not used **

27 Page 26/44 So P 0 1 Sensor data for channel x P 0 1 Sensor data for channel y P 1 0 Self-test data for channel x P 1 0 Self-test data for channel y P P HE P HE P CNC P CNC P CNC P ND P ND RE Device in self-test mode or self-test switched off for t < 4ms 0 Request error if 1. command is not wr_grange Hardware error Ch2 455/465-Ch3 455/465-Ch4 (Condition not correct) No data available Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z EEPROM error ** Not used means that the slave does not send such a message 6.4 Non acceleration commands These commands are used to write/read control and status registers SCK CS MOSI OP1 OP0 SEN A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MISO 0 OP1 OP0 P ST1 ST0 ES1 ES0 D7 D6 D5 D4 D3 D2 D1 D0 Format of non acceleration commands

28 Page 27/44 The function of the individual bits of SI and SO are shown respectively. Name Bit position Description Definition OP1:OP0 15:14 Opcode Defines operation read/write SEN 13 Sensor bit Defines sensor data request (SE = 1), or non sensor data request (SE = 0) A4 : A0 12:8 Address For read or write operation D7 : D0 7:0 Data For write operation Bit : 8 7 : 0 OP1 OP0 SEN A4 : A0 D7 : D0 / - Request SI A4 : A0 D7 : D0 Write register A4 :A0 - Read register Function of SI bits for non acceleration commands Name Bit position Description Definition OP1:OP0 14:13 Opcode Identifies contents of Read or Write data in D9:D0 Copied from SI if request is granted else Request Error RE P 12 Parity Ensures odd parity for bits 15:0 of SO ST1:ST0 11:10 Status Always 11 for non acceleration commands ES1:ES0 9:8 Exception Always 10 for non acceleration commands status D7:D0 7:0 Data error response / slave status / read data / Bit : 0 0 OP1 OP0 P ST1 ST0 ES1 ES0 D7: D0 / error / data Response P RE 0 Request error SO P SE 0 0 SPI error P Slave status Write response P Read data Read response Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z EEPROM error

29 Page 28/44 Function of SO bits for non acceleration commands Application Hint: It is recommended to evaluate requests of write accesses in the ECU. It can be ensured that the write access was successfully executed Range selection After release of reset, the device awaits the SPI command WR_GRANGE specifying the g-ranges of x- (SMB455, SMB465) and y-channel (SMB465). The g-range selection command shall be the first SPI command sent from the microcontroller after releasing the reset. All other SPI commands at that phase are leading to an error message request error and are not executed by the device Command WR_GRANGE OpCode OP1 OP0 SEN A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Bit MOSI MY1 RY1 MY0 RY0 MX1 RX1 MX0 RX0 MISO P MY1 RY1 MY0 RY0 MX1 RX1 MX0 RX0 If WR_GRANGE command is received the device checks the correctness of range selection data (comparison range bits to mirror range bits). If deviation is detected the command is not executed and the device sends error message request error. DEVSTAT-Flag GRANGE in DEVSTAT-REG1 will NOT be set. Upon receipt of a valid g-range selection SPI command the g-range selection bits are stored in 4 range bits of the RAM (RX0/1, RY0/1) (see g-range selection table) and has to be copied to 4 mirror range bits of RAM (MX0/1, MY0/1). Upon receipt of a valid g-range selection SPI command the sensor starts automatically initialization phase 3. The content of the range bits and mirror range bits is accessible for the application via an SPI read command Command RD_GRANGE OpCode OP1 OP0 SEN A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Bit MOSI MISO P MY1 RY1 MY0 RY0 MX1 RX1 MX0 RX0 During normal operation the content of the range bits is continuously (at rate 2MHz) compared against the mirror range bits. Any deviation sets the hardware error (HE). DEVSTAT-Flag GRANGE in DEVSTAT- REG1 will be set. Selection of g-range Channel x Channel y MY1 RY1 MY0 RY0 MX1 RX1 MX0 RX0 70g X X X X g X X X X g X X X X g X X X X g X X X X 50g X X X X 35g X X X X

30 Page 29/44 25g X X X X g-range selection table (X can be either 0 or 1) EOI bit in Device Control Register EOI is bit Nr. 5 in device control register. Default value after reset: 0 The EOI bit is used for finishing initialization phase 4 and setting the sensor in normal mode The EOI bit shall be set by the customer after a minimum fast offset cancellation time. If this minimum fast offset cancellation time is neglected by setting EOI bit to early, remaining raw offset will occur in normal sensor mode. The EOI bit can only be reset to 0 by giving a low signal to the RESET pin or by under voltage reset. If the master (microcontroller) requests EOI = 1 by using command WR_DEVCTL, bits 4:0 in this command will be ignored and the following actions will be performed on device control register: o o o o o EOI bit is set to 1 (EOI = 1) and can not be reset to 0 again using WR_DEVCTL in case of active self test : self test is permanently switched off (ST2:ST0 = 000) and offset cancellation is switched on and set into slow mode If no self test active and offset cancellation in fast mode: offset cancellation is set into slow mode (OFFC = 1) and self test is permanently disabled (ST2:ST0 = 000) If no self test active and offset cancellation in slow mode: offset cancellation stays in slow mode (OFFC = 1) and self test is permanently disabled (ST2:ST0 = 000) linear interpolation: bit LIN holds its value and cannot be changed anymore If bit EOI in device control register is set to 1, further WR_DEVCTL commands are not executed and request error (RE) is sent. Bit SI EOI LIN OFFC ST2 ST1 ST0 SO P EOI LIN OFFC ST2 ST1 ST Offset cancellation Offset cancellation starts automatically after g-range selection and runs continuously. Bit OFFC in device control register controls the mode of the offset cancellation as following: OFFC = 0: fast mode activated/retriggered OFFC = 1: slow mode activated After reset default value OFFC = 0 The sensor can be switched between fast and slow offset cancellation mode without limitations when (EOI=0 and ST=0). Relation between offset cancellation and self test for EOI = 0 It is not possible to enable self test in fast offset cancellation mode. If the master (microcontroller) requests enabling self test and setting offset cancellation in fast mode simultaneously by using command WR_DEVCTL the sensor will send request error (RE) and the command will not be executed.

31 Page 30/44 If the master (microcontroller) requests enabling self test and setting offset cancellation in slow mode simultaneously by using command WR_DEVCTL the self test will be triggered and the offset cancellation will be set into slow mode and switched off temporarily during selftest. If the master (microcontroller) requests switching off the self test after a self test phase using command WR_DEVCTL the self test will be disabled. The OFFC bit in WR_DEVCTL command will be ignored and the offset cancellation will be switched on in slow mode. After disabling the self-test the sensor needs 4 ms to return to resting state.

32 Page 31/ Error Management The device replays with an error response if one of the following errors has occurred: EEPROM error EE, Hardware error HE, SPI error SE, Request error RE Condition not correct error CNC No data available error ND Table below shows the setting conditions of EE, HE, SE, RE, CNC, and ND Flag EE RE SE HE CNC ND Setting condition This flag is set for both acceleration and non acceleration commands. It is sent if the content of the EEPROM has an error. This error is detected by cyclic redundancy check (CRC). The EEPROM contains calibration data for the band gap, oscillator frequency, fine gain for channel x and y, testsignal trimming, sensor type selection and CRC This flag is also set if connection AGND is interrupted (AGND pin lifted): SO will go to high impedance This flag is set for both acceleration and non acceleration commands. It is set to 1 if: - the applied command codes are not used - write/read test register commands (extended mode commands) have been received in normal mode. - the 1 st command after reset is not WR_GRANGE - Attempt to send WR_GRANGE more than 1 time - the GRANGE bits and their correspondent mirror bits don t match (coincide) - If the EOI-bit in the device control register is set to 1 and the command WR_DEVCTL is sent by the master. In this case WR_DEVCTL will not be executed and RE is set to 1. - If the master (microcontroller) requests self test and sets the offset cancellation in fast mode simultaneously by using the command WR_DEVCTL, the sensor will send request error (RE) and the command will not be executed. This flag is set in the 1 st message after reset (no request). Non acceleration commands are allowed during fast offset cancellation. This flag is set for both acceleration and non acceleration commands. It is set to 1 for request (SI) frame violation (incorrect number of SCK pulses more or less than 16 pulses). The Message includes SE has always the format of non acceleration commands This flag is set only for acceleration commands It is set to 1 if a hardware error has occurred; see table 7 and 8 for details. If HE occurred, the sensor data cannot be read anymore. Also, a HE for one channel X makes it impossible to read the data of the other channel. This flag is set only for acceleration commands. It is set to 1 if: - sensor data for channel no. 3 or 4 has been requested (CH1 = 1, CH0 = 0 or CH1 = 1, CH0 = 1) for SMB465 / SMB455 or - channel no. 2 (channel y) for SMB455 (single channel) This flag is set only for acceleration commands. It is set to 1 if sensor data for channel x or y has been requested during fast offset cancellation is active.

33 Page 32/ Error management for acceleration commands During an acceleration command different errors EE, SE, RE, HE, ND and CNC can be detected. The EEPROM error (EE) has the highest priority, hardware error (HE) has the lowest priority. If an SPI error occurs during an acceleration command the device sends a non acceleration error response including SE set to 1. Table below shows the device response for all possible combinations of EE, SE, RE, HE, ND and CNC. If the slave sends HE, the microcontroller can request the device status registers. This registers gives information about the reason of setting the HE flag. HE is set to 1 if one or more of the bits in this device status registers is set to 1. HE ND CNC RE SE EE Device response detected detected detected detected detected detected Normal response (sensor data) EE response SE response RE response CNC response ND response HE response 0: error not detected 1: error detected register Bit Name Description DEVSTAT1_REG 0 OC1 Set to 1 if the offset cancellation of channel x out of range (capture range 683 LSB (25g), 488 LSB (35g), 341 LSB (50g), 244 LSB (70g), maximum possible offset before cancellation). Reversibility: HE will be cancelled and OC1 will be reset if the offset returns within the capture range limits. 1 OC2 Set to 1 if the offset cancellation of channel y out of range (capture range 683 LSB (25g), 488 LSB (35g), 341 LSB (50g), 244 LSB (70g), maximum possible offset before cancellation). Reversibility: HE will be cancelled and OC2 will be reset if the offset returns within the capture range limits. 2 OCC1 Set to 1 if the offset cancellation for channel x is in wrong mode (fast instead of slow) 3 OCC2 Set to 1 if the offset cancellation for channel y is in wrong mode (fast instead of slow)

34 Page 33/44 4 No internal n/a clock No register update, SPI information will not change. Change from non acceleration data to acceleration data and vice versa is not possible. Change from x-axis data to y-axis data and vice versa is not possible. Error will not be written in DEVSTAT1_REG 5 Set to 1 if the device is in extended mode. In this mode some read/write commands are defined for production relevant tests. Extended mode These commands are allowed only in this mode. If one of these commands has been received in normal mode (not in extended mode) the flag RE will be set to 1. The device can be set into extended mode through a write register command 6 SPIEC Set to 1 if the multiplexer of sensor data has an error (selecting channel x instead of channel y) 7 GRANGE Set to 1 if g-range failure occurs register Bit Name Description 0 n.a. n.a 1 DGND The connection of the digital (DGND) ground pads is monitored and checked against interruption. If the DGND loose connection to the ground potential, the DGND failure flags in the Device Status Register 2 will be and made available over SPI DEVSTAT2_REG If the connection AGND is interrupted ( AGND pin lifted ) the same effect as for EEPROM Error (EE) takes place: the SO pin will go high impedant. When the failure modes in device status register are no longer effective the dedicated failure bits are reset immediately. This will lead to reset the flag HE immediately.

35 Page 34/ Error management for non acceleration commands During a non acceleration commands EE, SE, RE can be detected. EE has the highest priority, and RE the lowest one. The table below shows the device response for all possible combinations of EE, SE and RE. RE SE EE Device response detected detected detected Normal response EE response SE response RE response 6.6 SPI Instruction Set RD_DEVICE_ID The Device ID is defined unique to allow identification of different IC-typed by software. Bit SI SO P DEVICE-ID for SMB Device ID SMB465: 44 hex, bin Device ID SMB455: 42 hex, bin RD_REVISION_ID The Device Revision number may be utilised to distinguish different revisions of the SMB465/SMB455. The contents is divided into an upper 4 bit field (SWR) reserved to define revisions corresponding to specific software releases and a lower 4 bit field (MSR) utilised to identify the actual mask set. Both (SWR and MSR) will start with 0000b and are increased by 1 every time a modification affecting the respective field was made.

36 Page 35/44 Bit SI SO P SWR MSR RD_DEVSTAT1_REG This command is used to read the device status register 1. Bit SI SO P Device status register RD_DEVSTAT2_REG This command is used to read the device status register 2. Bit SI SO P Device status register RD_SENSOR_DATA Read 10 bits data from channel X or Y, for details see chapter Bit SI 0 cadr SO 0 0 cadr P 0 1 Sensor data from sensor or SO 0 0 cadr P 1 0 Sensor selftest data Cadr (channel address): used to address the selected channel 0 : channel X 1 : channel Y Acceleration data is processed and transmitted as a signed 10 bits word (2 s complement). Zero g level is 000 hex. The maximum acceleration word is +480 the minimum is 480 LSB. If the result of the internal A/D conversion is exceeding this range, the value is clipped to the limits. So the biggest (positive) acceleration value corresponds to 1E0 hex, the biggest (negative) deceleration value corresponds to 220 hex :

37 Page 36/44 Dec Hex Acceleration Data FF Not used : : : : : : E1 Not used E0 Maximum positive value of acceleration : : g value -1 3FF : : Maximum negative value of acceleration F Not used : : : : : : Not used If the device is set in self-test mode then, the slave sends self-test data instead of sensor data. If a hardware or SPI error has occurred, the slave sends an error response as described in error management WR_DEVCTL This instruction can be used to execute one or more of the following actions: 1. Change offset compensation mode of both sensor channels 2. Trigger the internal self-test function of the sensor 3. Switch off / on the linear interpolation This command is allowed only after the initialization phase. If this command is received in the initialization phase the slave responses with request error RE. Bit SI EOI LIN OFFC ST2 ST1 ST0 SO P EOI LIN OFFC ST2 ST1 ST0 ST2:ST1:ST0 x x 0 Self-test disabled for both channels Positive deflection for both channels Negative deflection for both channels Positive deflection for x-channel and negative deflection for y-channel Negative deflection for x-channel and positive deflection for y-channel

38 Page 37/44 Switching off selftest is delayed 4ms in device control register. LIN: 0: switch off linear interpolation of both channels 1: switch on linear interpolation of both channels Default setting: linear interpolation switched on If switched off, the sampling rate per channel is khz, this is the base mode. If switched on, linear interpolation on both channels is activated. The interpolation does a linear interpolation between every two measurement samples (a new sample every 128µs at khz). Increasing the update frequency of the SPI output register to 2 MHz gives a new calculated sample every 0.5µs. The total signal run time will increase 128µs compared to the signal conditioning without linear interpolation. Action on device control register by command WR_DEVCTL Request from Action on device control register microcontroller using WR_DEVCTL EOI OFF C ST Default after reset, fast offset cancellation active Selftest in fast offset cancellation mode, not executed, Request error Slow offset cancellation active Selftest triggered, Slow offset cancellation disabled during selftest Fast offset cancellation changed in slow offset cancellation OFFC = 1, ST0 = 0 accepted, Freeze DEVCTL register Fast offset cancellation changed in slow offset cancellation OFFC = 1; no selftest triggered ST0 = 0, Freeze DEVCTL register OFFC = 1 and ST0 = 0 accepted, Freeze DEVCTL register OFFC = 1 accepted, no selftest triggered ST0 = 0, Freeze DEVCTL register RD_DEVCTL Instruction to read the device control register. Bit SI SO P EOI LIN OFFC ST2 ST1 ST RD_READCNT Instruction to read the device CLK counter register. The SMB465/SMB455 features an 8 bit internal counter register (wrap around) which is increased every 256 cycles of the internal system clock (wrap around counter frequency of khz).

39 Page 38/44 Bit SI SO P D7 D6 D5 D4 D3 D2 D1 D0 D0-D7: Device CLK count register Electrical serial number This command is used to read the 48bit serial number. RD_SN0 Bit SI SO P D7 D6 D5 D4 D3 D2 D1 D0 RD_SN1 Bit SI SO P D15 D14 D13 D12 D11 D10 D9 D8 RD_SN2 Bit SI SO P D23 D22 D21 D20 D19 D18 D17 D16 RD_SN3 Bit SI SO P D31 D30 D29 D28 D27 D26 D25 D24 RD_SN4 Bit SI SO P D39 D38 D37 D36 D35 D34 D33 D32 RD_SN5 Bit SI SO P D47 D46 D45 D44 D43 D42 D41 D40

40 Page 39/ Timing Parameters Timing Reference: 0.2 Vs 0.8 Vs (Vs = V VDDD-DGND ) Num Parameter Symbol Min. Max. Unit - SPI Operating frequency f OP MHz A Clock (SCK) high time t WSCKlh 49 - ns B Clock (SCK) low time t WSCKl 49 - ns C SCK period t SCK ns D Clock (SCK) fall time t f ns E Clock (SCK) rise time t r ns F Data input (MOSI) setup time t su 37 - ns G Data input (MOSI) hold time t hi 49 - ns H Data output (SO) access time t a - 43 ns I Data output (SO) valid after SCK t V - 35 ns J Data output (SO) lag time t lag 0 - ns

41 Page 40/44 K Data output (MISO) disable time t dis ns L Enable (SS) lead time t lead 62 - ns M Enable (SS) lag time t lag 62 - ns N Sequential transfer delay t td µs O Internal write cycle time us P Clock enable time (Tele) T CLE 50 - ns Q Clock delay time (Teld) T CLD 50 - ns 6.8 Recommendations It is recommended to test following errors during power up of the ECU: - RE: The response while sending the first command after release of reset must be RE - CNC: condition not correct via requesting sensor data of Illegal channel (see Chapter 6.3) - ND: no data available via requesting sensor data during initialisation phase It is recommended to test following commands during power up of the ECU: - RD-DEVICE_ID: Read Device ID via checking the response (see chapter 6.6.1) - RD_REVISION_ID: Read Revision ID via checking the response (see chapter 6.6.2) - RD_DEVSTAT1_REG: Read Device Status Register via checking the response (see chapter 6.6.3) - RD_SENSOR_DATA: Read Sensor Data via checking the response (see chapter 6.6.4); checking plausibility of transmitted sensor data. (e.g Selftest and offset value in initialization phase) - RD / WR_DEVCTL: Read/Write Device Control Register via checking the response including right status of linear interpolation (see chapter and 6.6.6) It is recommended to evaluate all possible error responses (acceleration and non acceleration commands) all the time. After getting error responses the ECU has to start defined operations, like turn on a warning lamp (depending on ECU-system). 6.9 Internal Counter The SMB465/SMB455 provides an on chip count register. This counter register can be read out via specific SPI command (see chapter RD_READCNT ). The value is frozen by the slope of the CS signal. The counter is an internal wrap around counter which is increased every 256 cycles if the internal system clock (2MHz; +/-5%). The overflow is reached after 255 increments. By reading the register two times with a well defined delay the second counter value can be calculated and compared with the second register value. The difference between this values multiplied with the 128µs (1/(2MHz/255)) gives the deviation of the internal clock frequency. This feature can be used in order to control the internal clock frequency.

42 Page 41/ Register Table