LSI/CSI LS8297 LS8297CT STEPPER MOTOR CONTROLLER

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Osborn Greene
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1 LSI/CSI LS9 LS9CT UL LSI Computer Systems, Inc. Walt Whitman oad, Melville, NY 4 (3) FAX (3) -040 A300 PE MOTO CONTOLLE April 009 FEATUES: Controls Bipolar and Unipolar Motors Cost-effective, low current, pin compatible replacement for L9 Torque ripple compensated half-steps - LS9CT Half and full step modes Normal/wave drive Direction control eset input Step control input Enable input PWM chopper circuit for current control Two over current sensor comparators with external references input All inputs and outputs TTL/CMOS compatible (TTL for V operation) Supply current < 400uA 4. to V Operation (VDD VSS). LS9 (DIP), LS9-S (SOIC), LS9-TS (TSSOP) LS9CT (DIP), LS9CT-S (SOIC), LS9CT-TS (TSSOP) See Figure DESCIPTION: The LS9 Stepper Motor Controller generates four phase drive signal outputs for controlling two phase Bipolar and four phase Unipolar motors. The outputs are used to drive two H-bridges for the two motor windings in the Bipolar motor or the four driver transistors for the two center- tapped windings in the Unipolar motor. The motor can be driven in full step mode either in normal drive (two-phase-on) or wave drive (one-phase-on) and half step mode. The LS9 provides two inhibit outputs which are used to control the driver stages of each of the motor phases. The circuit uses, FD/EV and HALF/FULL inputs in a translator to generate controls for the output stages. A dual PWM chopper circuit using an on-chip oscillator, latches and voltage comparators are used to regulate the current in the motor windings. For each pair of phase driver outputs (PHA, PHB, and PHC, PHD) each pulse of the common internal oscillator sets the latch and enables the output. If the current in the motor winding causes the voltage across a sense resistor to exceed the reference voltage, VEF, at the comparator inputs, the latch is reset disabling the output until the next oscillator pulse. The CONTOL input determines whether the chopper acts on the phase driver outputs or the inhibit outputs. When the phase lines are chopped, the non-active phase line of each pair (PHA, PHB or PHC, PHD) is activated rather than de-activating the active line to reduce dissipation in the load sensing resistors. efer to Figure B for Bipolar motors. If PHA is high and PHB is low, current flows through Q, motor winding, Q4 and sense resistor s. When chopping occurs, PHB is brought high and circulating current flows through Q and D3 and not through s resulting in less power dissipation in s. Current decay is slow using this method. When the Control input is brought low, chopping occurs by bringing low. In this case circulating current flows through D, motor winding and D3 and through the power supply to ground causing the current to decay rapidly. For Unipolar motors, only inhibit chopping is used. efer to Figure. When is brought low SYNC V SS HOME PHA PHB PHC INH PHD ENABLE LSI FIGUE current in either half of the center tapped motor winding recirculates through the diode across it. LS9CT is the torque ripple compensated version of the LS9. Torque imbalance resulting from alternating onephase on, two-phase on sequence of the half-step mode (see Figure 4) is eliminated in the LS9CT by switching the sense reference voltage between 0% and 0.% in alternate steps. INPUT/OUTPUT DESCIPTION: PIN ASSIGNMENT TOP VIEW LS9 LS9CT Input An C input with the resistor connected to VDD and the capacitor connected to ground determines the oscillator chopper rate. When connected as an oscillator, the oscillator output appears as a negative-going pulse at the Sync pin. If the Oscillator pin is tied to ground, the Sync pin becomes an input. Osc frequency, fosc = /0.9C SYNC As an output the Sync can be used to drive Sync pins of other LS9s. This eliminates the need for C components for any other LS9 controllers used in the system. As an input the Sync can be driven by the LS9 that has the C oscillator components or by any other system external clock ESET HALF/FULL FWD/EV VEF SENSE SENSE VDD CONTOL

2 PHA/PHB/PHC/PHD Phase drive output signals for power stages. In a Bipolar motor PHA and PHB are used for one H-bridge while PHC and PHD are used for the other. /INH Outputs These outputs are active low inhibit controls for motor drive outputs. controls driver stage using PHA and PHB signals while INH control driver stage using PHC and PHD signals. When the Control input is low, these outputs are chopped using the internal oscillator for current regulating. CONTOL Input When high, the phase outputs, PHA, PHB, PHC and PHD are chopped. When low, and INH are chopped. Normally, inhibit outputs are chopped. Phase chopping might be used with a Bipolar motor that does not store much energy to prevent fast current decay and a low useful torque. ENABLE Input When Enable input is low,, INH, PHA, PHB, PHC and PHD are brought low. HOME Output An open drain output that indicates when the LS9 is in its initial state with PHA, PHB, PHC, PHD = logic states 0 respectively. efer to Figure 4. In the active state the open drain device is off. Input An active low pulse on this input causes the motor to advance one step. The step occurs on the rising edge of the step signal. FD/EV Input A logic on this input causes the motor to advance through the stepping sequence of Fig. 4. A logic 0 on this input cause the motor to reverse the sequence. ESET Input An active low on this input cause the motor to be restored to the home position (0). HALF/FULL Input When high, half-step operation is selected. When low, fullstep operation is selected. One-phase on full step is selected by selecting full when stepping sequence is at an even state. Two-phase on full step operation is selected when stepping sequence is at an odd state. efer to Figure 4. SENSE/ SENSE Inputs Inputs for load current sense voltages from power stages using PHA and PHB drive signals or PHC and PHD drive signals, respectively. VEF eference voltage for chopper circuit which determines the peak load current. VDD VSS PHA PHB PHC INH PHD 4 9 +V HALF/FULL 9 ENABLE ESET 0 TANSLATO OUTPUT LOGIC FWD/EV CONTOL Q S FF S Q FF HOME 3 x0.0 MUX + - SYNC VEF SENSE SENSE FIGUE. LS9/LS9CT BLOCK DIAGAM 9-09-

3 ABSOLUTE MAXIMUM ATINGS Symbol Parameter Value Unit VS Supply Voltage V Vi Input Signals V TSTG, TJ Storage and Junction Temperatures -40 to +0 C ELECTICAL CHAACTEISTICS: (efer to Block Diagram, Figure, and Timing Diagram, Figure 3) TA = + C, VDD = +V unless otherwise specified. Parameter Symbol Minimum Typical Maximum Unit Condition (Pin ) Supply Voltage VDD 4. - V - Quiscent Supply Current IDD ua Outputs floating (Pins,,, 9, 0) Input Voltage Low VIL 0-0. V - Input Voltage High VIH - VDD V - Input Current II na VI = VIL Input Current II na VI = VIH (Pin ) Enable Input Voltage Low VENL V - Enable Input Voltage High VENH - VDD V - Enable Input Current IEN na VEN = VENL Enable Input Current IEN na VEN = VENH (Pins 4,,, 9) Phase Output Voltage Low VOL V IO = -ma Phase Output Voltage High VOH V IO = ma (Pins, ) Inhibit Output Voltage Low VInhL V IO = -ma Inhibit Output Voltage High VInhH V IO = ma (Pin 3) Leakage Current ILeak - - ua VO = VDO = V Saturation Voltage VSat V I = ma (Pins, 4, ) Comparators Offset Voltage VOff - - mv VEF = V Comparator Bias Current IO 0 - ua - (Pin ) Input eference Voltage VEF 0-3 V - Input Current IEF - - ua VEF = 3V Clock Time Step tstp us - Pulse Width Set up time ts - - us - Hold time th us - eset time t - - us - eset to Step delay tstp - - us - (Pin ) Oscillator: Sawtooth Low VSOL -. - V - Sawtooth High VSOH V - Frequency f khz = kω, C = 3.3nF

4 Parameter Symbol Minimum Typical Maximum Unit Condition (Pin ) Sync: Sync Output Voltage Low VSyncL V IO = -ma Sync Output Voltage High VSyncH V IO = ma Sync Input Pulse Width TSPW us = kω, C = 3.3nF Sync Input Switching Point TSSP V Pin <.0V Sync Input Current IIS ua Pin <.0V, VIN = VDD tstp FWD/EV HALF/FULL ts th ESET t tstp FIGUE 3. Input Timing Diagram

5 A B C 0 HOME D INH FIGUE 4A. HALF- MODE A B C 0 HOME 00 D 0 INH 0 FIGUE 4B. NOMAL DIVE MODE (TWO-PHASE-ON) A B C D 00 INH FIGUE 4C. WAVE DIVE MODE (ONE-PHASE-ON) FIGUE 4. MOTO DIVING SEQUENCES The LS9 generates phase sequences for half-step mode, normal drive mode and wave drive mode. Advancing occurs on the positive edge of the input signal. HOME is defined as PHA, PHB, PHC, PHD being 0, respectively. The State Diagrams showing the phase output polarities for all states are shown above for clockwise rotation. For counter clockwise rotation, the sequences are reversed. ESET restores the phases to 0 and State. 9-0-

6 V V M 9 4 MCU 9 0 VDD HALF/FULL CONTOL ESET FD/EV ENABLE INH PHA PHB PHC 4 VDD VS OUT INH PHA OUT PHB OUT3 PHC 3 PE MOTO WINDINGS PHD 9 PHD OUT4 4 V DD k LS9 LS9CT L9 3.3nF VSS SENSE SENSE VEF 4 SENSEB SENSEA VSS Note: The SENSE resistors on L9 should be chosen so that IMAX = V EF/, where IMAX is the maximum motor winding current. See Note FIGUE A. Typical Application Schematic for a Two-Phase Bipolar Motor Using a Single Motor Driver IC V M PHA Q D D3 Q3 PHB Q D D4 Q4 SENSE FIGUE B. One half of L9 Drive Stage

7 V V M MCU 9 0 V DD PHA HALF/FULL PHB CONTOL ESET FD/EV SENSE ENABLE Q 3 4HC0 Q V DD k LS9 LS9CT 3.3nF V M PHC PHD INH 9 9 4HC0 Q3 Q4 V SS SENSE VEF NOTE: Q, Q, Q3, Q4 are MOSFET Power Transistors suitable for V Gate Drive Typical P/Ns = ILZ44N and IF30 FIGUE. TYPICAL APPLICATION SCHEMATIC FO A FOU-PHASE UNIPOLA MOTO USING DISCETE MOSFET TANSISTOS

8 +V SYNC SYNC SYNC LS9 LS9 LS9 LS9CT LS9CT LS9CT C FIGUE. Synchronizing Multiple LS9s The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use

LSI/CSI LS8397 STEPPER MOTOR CONTROLLER. LSI Computer Systems, Inc Walt Whitman Road, Melville, NY (631) FAX (631)

LSI/CSI LS8397 STEPPER MOTOR CONTROLLER. LSI Computer Systems, Inc Walt Whitman Road, Melville, NY (631) FAX (631) LSI/SI LS39 UL LSI omputer Systems, Inc. Walt Whitman Road, Melville, NY 4 (3) -0400 FAX (3) -040 A300 PER MOTOR ONTROLLER April 009 FEATURES: ontrols Bipolar and Unipolar Motors L9 operation with added