IX9915NTR + _. Low Voltage Error Amplifier with a 350V Darlington Transistor INTEGRATED CIRCUITS DIVISION. Features. Description.

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1 Low Voltage rror Amplifier with a 350V Darlington Transistor Features Precision reference, error amplifier, and a high voltage Darlington transistor in a single package 1.299V±1% to 85º) rror amplifier supply voltage range: 1.3V to 12.5V over temperature reakdown voltage of Darlington transistor: 350V Applications LD lamps Low voltage power supply feedback A-to-D off-line power supplies D-to-D converters Description The integrates an error amplifier with a precision reference and a 350V Darlington transistor in a single package. The error amplifier can be operated from 1.3V to 12.5V over the operational temperature range. The breakdown voltage of the Darlington transistor is 350V. The integrated combination of a 4-terminal 431 type shunt regulator with a high voltage Darlington transistor is ideal for use in LD lamp bleeder control circuits. Ordering Information Part N NTR Description 8-pin SOI, Tube (100/Tube) 8-pin SOI, Tape & Reel (2000/Reel) lock Diagram V RF F DS--R01 1

2 1. Specifications Package Pinout Pin Description Absolute Maximum Ratings lectrical haracteristics Test Diagrams Performance Data Functional Description Regulation Voltage ompensation Design xample Manufacturing Information Moisture Sensitivity SD Sensitivity Soldering Profile oard Wash Mechanical Dimensions R01

3 1. Specifications 1.1 Package Pinout 1.2 Pin Description F N/ Pin# Name Description 1 F Input Voltage 2 Output urrent 3 Darlington ase 4 N/ Not onnected 5 Darlington ollector 6 Darlington mitter 7 Supply Input 8 Supply Return 1.3 Absolute Maximum Ratings 1 Derate linearly 2.83 mw/. Parameter Symbol Ratings Unit ollector-mitter Voltage V O 350 V mitter-ollector Voltage V O 2 V ollector urrent I 200 ma Supply Voltage (Referenced to ) 15 V Output D urrent I 20 ma Power Dissipation (Shunt Regulator) P A 30 mw Power Dissipation, Darlington Transistor 1 P D 250 mw Total Power Dissipation 1 P T 250 mw SD Rating (Human ody Model) - 2 kv Operating Temperature T OPR -40 to 85 Storage Temperature T STG -55 to 130 Unless otherwise specified, Absolute Maximum electrical ratings are at 25. Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Typical values are characteristic of the device at 25, and are the result of engineering evaluations. They are provided for information purposes only, and are not part of the manufacturing testing requirements. R01 3

4 1.4 lectrical haracteristics Parameter Symbol onditions Min Typ Max Unit Input (Unless Otherwise Specified) Supply voltage T A =-40 to V Reference voltage 1 V RF =1.6V, I =10mA (Fig. 1) T A = V T A =-40 to Deviation of V RF over temperature 2 V RF(DV) =1.6V, I =10mA, T A =-40 to 85 (Fig. 1) mv Ratio of V RF variation to change V RF / 1.3V < < 12.5V, I =10mA (Fig. 1) mv/v F input bias current I I =1.6V, I =10mA (Fig. 1) A Deviation of I I over temperature 2 I I(DV) =1.6V, I =10mA, (Fig. 1) T A =-40 to A Quiescent bias current I Q =1.6V, V F = V RF, I =0mA (Fig. 3) A rror amplifier Off-State current I (off) V = =12.5V, V F =0V (Fig. 2) A Shunt Transconductance 3 g m ( I / V F ) =1.6V, I = 0.2mA to 10mA, f=1khz S Darlington (Unless Otherwise Specified) ollector-emitter voltage breakdown V O I =100 A V ollector current I V =200V, R =1M (Fig. 4) na ase-emitter On voltage V (ON) I =40mA, V =2V V ollector-emitter saturation voltage V (SAT) I =100mA, I =150 A V urrent gain h F I =40mA, V =2V Reference voltage measured at Pin F under the specified conditions. 2 Deviation parameters V RF(DV) and I I(DV) are defined as the difference between the minimum and maximum values obtained over the rated temperature range. g m 3 With two external resistors, the total shunt transconductance of the circuit is defined as: g m = Test Diagrams Figure 1: V RF, I I, V RF /, g M Test ircuit I I Q F I I V RF 4 R01

5 Figure 2: I (OFF) Test ircuit F Figure 3: I Q Test ircuit I I Q F I I V F Figure 4: I Test ircuit R V F R01 5

6 1.6 Performance Data V RF (V) V RF vs. Temperature I I (na) F Input ias urrent vs. Temperature (I =10mA) Temperature (º) Temperature (º) 1.2 Off-State urrent vs. Temperature (V =13.2V, V F =0V) 0.25 Saturation Voltage vs. Temperature (I =10mA) I Off urrent (na) V (sat) (V) Temperature (º) Temperature (º) 6 R01

7 2. Functional Description is the functional equivalent of a 4-terminal 431 type precision shunt regulator and a high voltage Darlington transistor in the same package. The typical application for is shown in Figure 5. Figure 5 Application Diagram Dimmer Switch I 3 V RG Rectifier R 3 A Supply - V LIN I H R 0 I I Q I 1 F V RF R This is a simplified application circuit that shows how the can be used in an LD lamp control circuit. The high voltage Darlington transistor will bleed the current when V LIN is lower than the predetermined voltage. The 4-terminal 431 type shunt regulator is used to monitor V LIN voltage and control the Darlington transistor bleeding the current (ON) or not (OFF). When V LIN reaches the predetermined voltage, the shunt regulator starts to regulate to drive V going low, and turns off the Darlington transistor to make sure this bleeder circuitry only burns a little power at the higher V LIN voltage. Maximum bleeding current I H can be controlled by properly choosing R and V RG. Regulation of V RG is made possible by applying a scaled sample of its voltage to pin F, the error amplifier's non-inverting input. The error amplifier compares this scaled voltage against an internal high accuracy reference voltage and generates an output current which in turn regulate V RG through the resistor R 3. As V RG increases, the error amplifier's input voltage V F will also increase. Ramping of V F beyond the internal reference voltage causes the error amplifier to sink more I, which in turn decreases V RG. Likewise, a reduction of V RG results in a lessoning of I causing V RG to increase. 2.1 Regulation Voltage When connected as shown in the application circuit above and properly configured, the will regulate V RG such that V F is equal to V RF (1.299V). To achieve this, the values of the voltage divider resistors, and, must be set in the following manner: R V RG V RF = ecause V RG regulation occurs when V F =V RF any change in bias current through at the desired regulated voltage level will cause a regulation error. As shown in the lectrical haracteristics table the error amplifier input at pin F has an input bias current (I I ) specification that reduces the current into. (I I is R01 7

8 always into pin F). This error causes the regulated output voltage to increase which increases the current through by an amount equal to I I, thereby restoring the current through to its original value. Reducing the V RG error created by the input bias current to less than 1% is accomplished by setting the value of using the following formula: V RG A Where: 2.2 ompensation 50 A = 100 I I MAX The dominate pole of the error amplifier is around 13kHz. In a typical system with a low-bandwidth requirement, it doesn't need any external compensation. Frequency response of the system can be optimized for the specific application by placing a compensation network between the and F pins of the. For designs with more critical bandwidth requirements, measurement of the loop response must be made and compensation adjusted as necessary. If taking R 0 =40k, the gain of the comparator is around 82d. That is to say, once the error amplifier starts to regulate, the Darlington transistor will be shut off by this comparator. So, I can be ignored for affecting the predetermined voltage: V LIN-TH V RG I 1 I Q R 3 (2) Almost full power supply voltage will cross over R 3, taking R 3 =100k to minimize its power consumption: V rms 2 P = k Substituting: I Q =75 A, I 1 =V RF /, V LIN-TH =25V into formula (2): 9.6k V RG = V RF 20k 2.3 Design xample A design example for the bleeder circuitry in LD lamp exhibits the detailed steps. In this example, it will target the predetermined voltage V LIN-TH =25V and maximum bleeding current I H-MAX =25mA. In order to flow the maximum bleeding current I H-MAX through the Darlington transistor: V RG = I H MAX R V (1) If taking R =100 : V RG = I H MAX R V = 25mA V = 4V In fact, the components in the dashed rectangle function as a comparator, its gain: R 0 g m A = V RF V RG 1.299V = = = V g m = 1S (typical) 8 R01

9 3. Manufacturing Information 3.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated ircuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IP/JD J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IP/JD J-STD-033. Device Moisture Sensitivity Level (MSL) lassification N MSL SD Sensitivity This product is SD Sensitive, and should be handled according to the industry standard JSD Soldering Profile Provided in the table below is the lassification Temperature (T ) of this product and the maximum dwell time the body temperature of this device may be (T - 5)º or greater. The classification temperature sets the Maximum ody Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other processes, the guidelines of J-STD-020 must be observed. Device lassification Temperature (T ) Dwell Time (t p ) Max Reflow ycles N seconds oard Wash IXYS Integrated ircuits Division recommends the use of no-clean flux formulations. oard washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). leaning or drying methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the device must not be exposed to flux or solvents that are hlorine- or Fluorine-based. R01 9

10 3.5 Mechanical Dimensions N 8-Pin SOI Package 0.31 / 0.51 (0.012 / 0.020) 8x TOP VIW P Land Pattern 1.55 (0.061) 5.80 / 6.20 (0.228 / 0.244) / 4.00 (0.150 / 0.157) 3.75 (0.148) 1.75 MAX (0.069 MAX) PIN # MIN (0.049 MIN) x / 5.00 (0.189 / 0.197) A GAUG PLAN SATING PLAN A 0.25 (0.010) / 0.25 (0.004 / 0.010) 0.40 / 1.27 (0.016 / 0.050) 0.60 (0.024) 0.10 / 0.25 (0.004 / 0.010) 0.10 (0.004) Dimensions MIN / MAX Notes: 1. ontrolling dimension: millimeters. 2. All dimensions are in mm (inches). 3. This package conforms to JD Standard MS-012, variation AA, Rev. F. 4. Dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15mm per end. 5. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. 6. Lead thickness includes plating NTR Tape & Reel DIA. (13.00 DIA.) Top over Tape Thickness MAX. (0.004 MAX.) 0 =5.30 (0.209) W=12.00 (0.472) K 0 = 2.10 (0.083) A 0 =6.50 (0.256) P1=8.00 (0.315) mbossed arrier User Direction of Feed Dimensions mm (inches) mbossment NOT: Tape dimensions not shown comply with JD Standard IA For additional information please visit IXYS Integrated ircuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. xcept as set forth in IXYS Integrated ircuits Division s Standard Terms and onditions of Sale, IXYS Integrated ircuits Division assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated ircuits Division s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated ircuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS--R01 opyright 2018, IXYS Integrated ircuits Division All rights reserved. Printed in USA. 3/23/ R01